RAM LAKHAN SINGH YADAV COLLAGE

SESSION : 2024 - 2027

SUBMITED BY :

NAME :- DIWANSHU KUMAR

CLASS :- BCA

ROLL NO :- 32

SUBJECT :- COMPUTER SYSTEM

ARCHITECTURE

SESSON :- 2024 - 2027

SIGNATURE.......................
 ***CONTENTS***

UNIT NAME PAGE

NO. NO.

INTRODUCTION
01 3-5

DATA REPRESANTATION AND

02 3-13
BASIC
COMPUTER ARITHMETIC

03 BASIC COMPUTER ORGANIZATION 13-18

AND DESIGN

04 CENTRAL PROCESSING UNIT 19-29

05 MEMORY ORGANIZATION 30-31

06 INPUT-OUTPUT ORGANIZATION 32-33

 *COMPUTER SYSTEM AECHITECTURE*

1. INTRODUCTION (MCQS)
(1). RTL stands for :
a) Random transfer language
b) Register transfer language
c) Arithmetic transfer language
d) All of a these

(2). Which language is termed as the symbolic depiction used for indicating
the series:
a) Random transfer language
b) Register transfer language
c) Arithmetic transfer language
d) All of a these

(3). The register that includes the address of the memory unit is termed as_:
a) MRA b) PC
c) IR d)None of these

(4). The register of a program counter is signified as _____:

a) MRA b) PC
c) IR d)None of these

(5). In register transfer the instruction register as:

a) MRA b) PC
c) IR d) None of these

(6). In register transfer the processor register as:

a) MRA b) PC
c) IR d) RI

(7). A counter is incremented by one and memory unit is considered as a

Collection of _______:

a) transfer register b) storage register

c) RTL d) All of these

(8). Which is the straight forward register transfer the data from register
to another register to another register temporarily :

a) Digital system b) Register

c) Data d) Register transfer operations
(9). The binary information of source register chosen by:
a) Demultiplexer b) multiplexer
c) both d) none

(10). Control transfer passes the function via control_:

a) Logic b) Operation
c) Circuit d) All of these

(11). Register are assumed to use positive-edge-triggered:

a) Flip-flop b) Logic
c) Circuit d) Operation

(12). Every bit of register has:

a) 2 common line b) 3 common line
c) 1 common line d) none of these

(13). The bits are shifted and the first flip-flop receives its
binary information from the__:

a) serial output b) serial input

c) both d) none

(14). The variable of _____ correspond to hardware register:

a) RAM b) RTL
c) ALU d) MAR

(15). How is selects the register that receives the information from
the output bus:
a) Decoder
b) Encoder
c) MUX
d) All of these

(16). How many source register propagate through the multiplexers:

a) 1
b) 2
c) 3
d) 4
(17). Arithmetic instruction are used to perform operation on:

a) Numerical data
b) non-numerical data
c) Both
d) None
(18). How many basic arithmetic operation:

a) 1
b) 2
c) 3
d) 4

(19). which are arithmetic operation are:

a) Addition
b) Subtraction
c) Multiplication
d) Division
e) All of these

(20). ________is just like a circular array:

a) Data
b) Register
c) ALU
d) CPU

(21). Which control refers to the track of the address of instructions:

a) Data control
b) Register control
c) Program control
d) None of these

(22). In program control the instruction is set for the statement in a:

a) Parallel
b) Sequence
c) Both
d) none

(23). A flow chart is drawn from top to bottom and ____:

a) Right to Left
b) Only right
c) Left to Right
d) Only left

(24). Which logic gate produces a HIGH output only when all its inputs are
HIGH?
a) OR
b) AND
c) NAND
d) NOR
(25). . What is the output of a NOT gate if the input is 1?

a) 0
b) 1
c) Depends on the voltage
d) Undefined

(26). Which gate is known as the universal gate?

a) AND
b) OR
c) XOR
d) NAND

(27). The output of an XOR gate is HIGH when:

a) Both inputs are HIGH

b) Both inputs are LOW
c) Inputs are different
d) Inputs are the same

(28). If the inputs to a NOR gate are 0 and 1, the output is:

a) 1
b) 0
c) Depends on the gate voltage
d) Undefined

(29). What is the primary function of a decoders in digital system ?

a) Encoded data
b) Decode daa from binary to decimal
c) perform arithmetic
d) perform memory addressing

(30). How many output line does a 3 to 8 decoder have ?

a) 3
b) 8
c) 16
d) 2
(31). Which logic gate is primarily used in design of decoders ?

a) OR gate
b) XOR gate
c) AND gate
d) NOR gate

(32). What is enable input in a decoder used for ?

a) To disable specific outputs

b) To activate the decoders
c) To perform addition
d) To select the decoder type

(33). A 2 to 4 decoder requires how many input line and output line, respectively

a) 2 and 4
b) 2 and 8
c) 4 and 2
d) 3 and 8

(34). What is the function of multiplexer ?

a) convert analog signals to digital signals

b) select one input from multiple inputs
c) adds multiple signals
d) store binary data

(35). How many selected lines are required for an 8 to 1 muitiplexer?

a) 8
b) 4
c) 3
d) 2

(36). Which circuit is used ti implement a multiplexer?

a) Full adder
b) Encoder
c) Demultiplexer
d) Logic gate

(37). the number of input for a 4 to 1 multiplexer is :

a) 1
b) 2
c) 4
d) 8
(38). Wich of the following is NOT an application of a multiplexer?

a) Data routine
b) Parallel to serial conversion
c) arithmetic calculation
d) Time – division multiplexer

(39). What is a flip-flop?

a) A combinational circuit
b) A sequential circuit
c) A storage device
d) Both b and c

(40). Which flip-flop is called a "basic memory element"?

a) SR flip-flop
b) JK flip-flop
c) D flip-flop
d) T flip-flop

(41). In a JK flip-flop, what happens when both J = 1 and K = 1?

a) Reset
b) Set
c) No change
d) Toggle

(42). Which flip-flop removes the indeterminate state of the SR flip-flop?

a) JK flip-flop
b) D flip-flop
c) T flip-flop
d) Master-slave flip-flop

(43). What is the characteristic equation of a T flip-flop?

a) Q(next) = Q
b) Q(next) = T
c) Q(next) = T ⊕Q
d) Q(next) = T • Q

(44). The D flip-flop is commonly known as a:

a) Toggle flip-flop
b) Delay flip-flop
c) Reset flip-flop
d) Memory flip-flop
(45). How many flip-flops are needed to construct a 4-bit counter?
a) 2
b) 4
c) 8
d) 16

(46). What is the main advantage of a master-slave flip-flop?

a) Operates at high speed
b) Removes race conditions
c) Requires fewer gates
d) Does not use clock pulses

(47). What is the propagation delay in flip-flops?

a) Time taken to set a flip-flop
b) Time taken for the output to respond to a change in input
c) Time taken to reset a flip-flop
d) Time taken to generate clock pulses

(48). Which flip-flop is used to construct a shift register?

a) SR flip-flop
b) JK flip-flop
c) D flip-flop
d) T flip-flop

(49). Which of the following is NOT a combinational circuit?

a) Multiplexer
b) Decoder
c) Flip-flop
d) Full adder

(50). What is the function of a multiplexer in a combinational circuit?

a) Data storage
b) Select one input from many inputs
c) Generate binary code
d) Convert binary to decimal

(51). How many output lines are there in a 3-to-8 decoder?

a) 3
b) 8
c) 6
d) 16

(52). Which logic gate gives an output of 1 only when both inputs are 1?

a) AND
b) OR
c) NAND
d) NOR
(53). What is the output of an OR gate if both inputs are 0?

a) 0
b) 1
c) Undefined
d) Both 0 and 1

(54). Which gate is a combination of an AND gate followed by a NOT gate?

a) NOR
b) NAND
c) XOR
d) XNOR

(55). The output of a NOT gate is:

a) The same as input

b) The complement of the input
c) The input multiplied by 2
d) The same as an AND gate

(55). Which of the following is a universal logic gate?

a) AND
b) OR
c) NAND
d) NOR

(56). If A = 0 and B = 1, what is the output of A XOR B?

a) 0
b) 1
c) Undefined
d) Depends on other inputs

(57). Which Boolean expression is equivalent to A + A' = 1?

a) Identity Law
b) Complement Law
c) Idempotent Law
d) Dominance Law

(58). The Boolean expression A + A.B is equivalent to:

a) A
b) B
c) A.B
d) A + B
(59). Which of the following laws states that A + 0 = A?

a) Identity Law
b) Null Law
c) Complement Law
d) Dominance Law

(60). Which of the following is the dual of the Boolean expression A + B?

a) A.B
b) A + B'
c) A' + B
d) A.B'

(61). Which of the following is a combinational logic circuit?

a) Flip-Flop
b) Latch
c) Adder
d) Counter

(62). A half adder is used to perform which operation?

a) Addition of two single-bit binary numbers

b) Subtraction of two binary numbers
c) Multiplication of two binary numbers
d) None of the above

(63). Which of the following is a key characteristic of a combinational circuit?

a) Depends on previous outputs

b) Has memory elements
c) The output is a function of the current inputs only
d) Can store information

(64). Which circuit is used to implement a full adder?

a) Half adder
b) XOR gate
c) AND and OR gates
d) Half adder and OR gate
(65). Which of the following is used for simplification of Boolean expressions?

a) Karnaugh Map
b) Flip-Flops
c) D flip-flop
d) Registers

(66). The Boolean expression A + A.B can be simplified to:

a) A
b) B
c) A + B
d) A.B

(67). Which law allows the simplification of A + A'B to A + B?

a) Absorption Law
b) Complement Law
c) Idempotent Law
d) Distributive Law

(68). Which flip-flop is used for data storage in registers?

a) D Flip-Flop
b) T Flip-Flop
c) SR Flip-Flop
d) JK Flip-Flop

(69). What is the characteristic of a T flip-flop?

a) It stores one bit of data

b) It toggles its state when the T input is high
c) It operates only with an active-low clock signal
d) It has no memory feature

(70). What does the JK flip-flop overcome that the SR flip-flop cannot handle?

a) It cannot have a forbidden state

b) It has only two states
c) It has only one input
d) It does not require a clock
(71). Which of the following is a type of counter that can store multiple bits of
information?

a) Binary counter
b) BCD counter
c) Decade counter
d) All of the above

(72). A decade counter counts from 0 to:

a) 9
b) 15
c) 7
d) 10

(73). Which memory is non-volatile ?

a) RAM
b) ROM
c) CACHE
d) REGISTER

(74). Which os the following is true about RAM ?

a) it is non-volatile
b) it remain data even when the power is off
c) it is faster than ROM
d) it is read only memory

(75). Which of the following is a flip-flops?

a) jk
b) RAM
c) ROM
d) Cache
2. DATA REPRESENTATION AND BASIC
COMPUTER ARITHMETIC**
(1). Group of binary bits(0&1) is known as:
a) Binary code
b) Digit code
c) Symbolic representation
d) None of these

(2). A group of 4 binary bits is called:

a) Nibble
b) Byte
c) Decimal
d) Digit
(3). BCD uses binary number system to specify decimal numbers:

a) 1-10
b) 1-9
c) 0-9
d) 0-10

(4). what is the BCD for a decimal number 559:

a) [0101 0101 1001]BCD

b) [0101 0001 1010]
c) [0101 1001 1001]
d) [1001 1010 0101]

(5). ________are the codes thatrepresent alphabetic characters, punctuation

marks and other special characters:

a) Alphanumeric codes
b) ASCII codes
c) EBCDIC codes
d) All of these

(6). Abbreviation ASCII stands for:

a) American standard code for information interchange

b) Abbreviation standard code for information interchange
c) Both
d) None of these

(7). How many bit of ASCII code:

a) 6
b) 7
c) 5
d) 8
(8). Which code used in transferring coded information from
keyboards and to computer display and printers:

a) ASCII
b) EBCDIC
c) Both
d) None of these

(9). Which code used to represent numbers, letters, punctuation marks as

well as control characters:

a) ASCII
b) EBCDIC
c) Both
d) None of these

(10). abbreviation EBCDIC stand for:

a) Extended binary coded decimal interchange code

b) External binary coded decimal interchange code
c) Extra binary coded decimal interchange code
d) None of these

(11). How many bit of EBCDIC code:

a) 7
b) 8
c) 5
d) 9

(12). Which code the decimal digits are represented by the 8421 BCD
code preceded by 1111:

a) ASCII
b) EBCDIC
c) Both
d) None of these

(13). Which is method used most simple and commonly:

a) Parity check method

b) Error detecting method
c) Both
d) None of these

(14). Which is the method of parity:

a) Even parity method

b) Odd parity method
c) Both
d) None of these
 (15). The ability of a code to detect single errors can be stated in term of the __:

a) Concept of distance
b) Even parity
c)Odd parity
d) None of these

(16). The first n bit of a code word called __________ may be any of the 2n n-
bit string minimum error bit:

a) Information bits
b) String bits
c) Error bits
d) All of these

(17). A code in which the total number of 1s in a valid (n+1) bit code word
is even, this is called an __________:

a) Even parity code

b) Odd parity code
c) Both
d) None of these

(18). A code in which the total number of 1s in a valid (n+1)bit code word
is odd and this code is called an__:

a) Error detecting code

b) Even parity code
c) Odd parity code
d) None of these

(19). a code is simply a subset of the vertices of the _____:

a) n bit
b) n cube
c) n single
d) n double

(20). Which method is used to detect double errors and pinpoint erroneous bits:

a) Even parity method

b) Odd parity method
c) Check sum method
d) All of these

(21). A code that is used to correct error is called an _________:

a) Error detecting code

b) Error correcting code
c) Both
(22). 0 and 1 are know as ___________:
a) Byte
b) Bit
c) Digits
d) Component

(23). 0 and 1 abbreviation for:

a) Binary digit
b) Octal digit
c) Both
d) None of these

(24). How many bit of nibble group:

a) 5
b) 4
c) 7
d) 8

(25). How many bit of bytes:

a) 3
b) 4
c) 6
d) 8

(26). A number system that uses only two digits, 0 and 1 is called the_:

a) Octal number system

b) Binary number system
c) Decimal number system
d) Hexadecimal number system

(27). In which computers, the binary number are represented by a set of

binary storage device such as flip flop:

a)Microcomputer
b) Personal computer
c) Digital computer
d) All of these

(28). A binary number can be converted into _________:

a) Binary number
b) Octal number
c) Decimal number
d) Hexadecimal number
(29). Which system is used to refer amount of things:

a) Number system
b) Number words
c) Number symbols
d) All of these

(30). _________are made with some part of body, usually the hands:

a) Number words
b) Number symbols
c) Number gestures
d) All of these

(31). __________are marked or written down:

a) Number system
b) Number words
c) Number symbols
d) Number gestures

(32). A number symbol is called a ___________:

a) Arabic numerals
b) Numerals
c) Both
d) None of these

(33). 0,1,2 ,3 ,4,5,6 ,7,8 and 9 numerals are called:

a) Arabic numerals
b) String numerals
c) Digit numerals
d) None of these

(34). How many system of arithmetic, which are often used in digital system:

a) 5
b) 6
c) 3
d) 4

(35). Which are the system of arithmetic, which are often used in digital system:

a) Binary digit
b) Decimal digit
c) Hexadecimal digit
d) Octal digit
e) All of these
(36). In any system, there is an ordered set of symbols also known as_:

a) Digital
b) Digit
c) Both
d) None of these

(37). Which is general has two parts in number system:

a) Integer
b) Fraction
c) Both
d) None of these

(38). MSD stand for:

a) Most significant digit

b) Many significant digit
c) Both a and b
d) None of these

(39). LSD stand for:

a) Less significant digit

b) Least significant digit
c) Loss significant digit
d) None of these

(40). The _____ and ________ of a number is defined as the number of

different digits which can occur in eachposition in the system:

a) Base
b) Radix
c) Both
d) None of these

(41). Which system has a base or radix of 10:

a) Binary digit
b) Hexadecimal digit
c) Decimal digit
d) Octal digit

(42). Each of ten decimal degits______.

a) 1 through 10
b) 0 through 9
c) 2 through 11
d) All of these
(43). The binary number system is also called a __________:

a) Base one system

b) Base two system
c) Base system
d) Binary system

(44). The two symbols 0 and 1 are known as:

a) Bytes
b) Bits
c) Digit
d) All of these

(45). In which counting, single digit are used for none and one:

a) Decimal counting
b) Octal counting
c) Hexadecimal counting
d.) Binary counting

(46). In which numeral every position has a value 2 times the value f the
position to its right:

a) Decimal
b) Octal
c) Hexadecimal
d) Binary

(47). A binary number with 4 bits is called a_:

a) Bit
b) Bytes
c) Nibble
d) None of these

(48). A binary number with 8 bits is called as a_:

a) Bytes
b) Bits
c) Nibble
d) All of these

(50). In which digit the value increases in power of two starting with 0 to left of
the binary point and decreases to the right of the binary point starting
with power -1:

a) Hexadecimal
b) Decimal
c) Binary
(51). Which system is used in digital computers because all electrical and
electronic circuits can be made to respond to the states concept:

a) Hexadecimal number
b) Binary number
c) Octal number
d) Decimal number

(52). Which addition is performed in the same manner as decimal addition:

a) Binary
b) Decimal
c) Both
d) None of these

(53). ______in all digital systems actually performs addition that can handle
only two number at a time:

a) Register
b) circuit
c) digital
d) All of these

(54). Which machine can perform addition operation in less than 1 ms:

a) Digital machine
b) Electronic machine
c) Both
d) None of these

(55). ________is the inverse operation of addition:

a) Addition
b) Multiply
c) Subtraction
d) Divide

(56). ________of a number from another can be accomplished by adding the

complement of the subtrahend to the minuend:

a) Subtraction
b) Multiply
c) Divide
d) All of these

(57). Complement the subtrahend by converting all __________and all___:

a) 1’s to 0’s
b) 0’s to 1’s
(58). . The binary number system uses which digits?

a) 0 and 1
b) 0 to 9
c) 0 to 7
d) 0 to 15

(59). What is the decimal equivalent of the binary number 1011?

a) 9
b) 10
c) 11
d) 12

(60). What is the base of the hexadecimal number system?

a) 2
b) 8
c) 10
d) 16

(61). What is the octal equivalent of the binary number 110101?

a) 65
b) 55
c) 45
d) 35

(62). Which number system is commonly used in digital electronics?

a) Decimal
b) Binary
c) Octal
d) Hexadecimal

(63). Which of the following is NOT a positional number system?

a) Binary
b) Decimal
c) Roman
d) Octal

(64). The 1's complement of 1010 is:

a) 0101
b) 1101
c) 0101
d) 1010
(65). Which operation is simplified using 2’s complement representation?

a) Multiplication
b) Division
c) Subtraction
d) Addition

(66). The 2's complement of the binary number 1100 is:

a) 0011
b) 0100
c) 1111
d) 0100

(67). What is the range of signed numbers in 4-bit 2’s complement

representation?

a) -7 to +7
b) -8 to +7
c) -7 to +8
d) 0 to +15

(68). Which representation is used for fractional numbers in computers?

a) Fixed-point representation
b) Floating-point representation
c) Hexadecimal representation
d) Binary-coded decimal representation

(69). In IEEE 754 single-precision format, how many bits are used for the
exponent?

a) 8
b) 16
c) 23
d) 32

(70). What is a drawback of fixed-point representation?

a) Limited precision
b) Cannot represent integers
c) Uses more memory
d) Cannot perform arithmetic operations

(71). Which part of a floating-point number represents its scale or magnitude?

a) Mantissa
b) Exponent
c) Sign bit
d) Base
(72). What is the sum of 1011 and 1101 in binary?
a) 11000
b) 10110
c) 10000
d) 11100

(73). What is the result of subtracting 1010 from 1101 in binary?

a) 0011
b) 0111
c) 1011
d) 1111

(74). When adding two binary numbers, a carry is generated when:

a) 0 + 0 = 1
b) 1 + 1 = 10
c) 1 + 0 = 10
d) 0 + 1 = 1

(75). What is the result of comparing two binary numbers 1101 and 1011?

a) 1101 is greater
b) 1011 is greater
c) Both are equal
d) Cannot be compared
3. BASIC COMPUTER ORGANIZATION AND DESIGN

(1). _____ is a command given to a computer to perform a specified operation

on some given data:

a) An instruction
b) Command
c) Code
d) None of these

(2). An instruction is guided by_____ to perform

work according:

a) PC
b) ALU
c) Both a and b
d) CPU

(3). Two important fields of an instruction are:

a) Opcode
b) Operand
c) Only a
d) Both a & b

(4).Each operation has its _____ opcode:

a) Unique
b) Two
c) Three
d) Four

(5).which are of these examples of Intel 8086 opcodes:

a) MOV
b) ADD
c) SUB
d) All of these

(6). _______specify where to get the source and destination operands for
the operation specified by the _______:

a) Operand fields and opcode

b) Opcode and operand
c) Source and destination
d) CPU and memory
(7). The source/destination of operands can be the_______ or one of the
general-purpose register:

a) Memory

b) One
c) both
d) None of these

(8). The complete set of op-codes for a particular microprocessor defines the
______ set for that processor:

a) Code
b) Function
c) Module
d) instruction

(9). Which is the method by which instructions are selected for execution:

a) Instruction selection
b) Selection control
c) Instruction sequencing
d) All of these

(10). The simplest method of controlling sequence of instruction execution

to have each instruction explicitly specify:

a) The address of next instruction to be run

b) Address of previous instruction
c) Both a & b
d) None of these

(11). As the instruction length increases ________ of instruction addresses

in all the instruction is_:

a) Implicit inclusion
b) Implicit and disadvantageous
c) Explicit and disadvantageous
d) Explicit and disadvantageous

(12). ______is the sequence of operations performed by CPU in processing an

instruction:

a) Execute cycle
b) Fetch cycle
c) Decode
d) Instruction cycle

(13). The time required to complete one instruction is called:

a) Fetch time
 b) Execution time
c) Control time
(14). _____is the step during which a new instruction is read from the memory:

a) Decode
b) Fetch
c) Execute
d) None of these

(15). ________is the step during which the operations specified by the
instruction are executed:

a) Execute
b) Decode
c) Both a& b
d) None of these

(16). Decode is the step during which instruction is__:

a) Initialized
b) Incremented
c) Decoded
d) Both b & c

(17). The instruction fetch operation is initiated by loading the contents of

program counter into the______ and sends_____ request to memory:

a) Memory register and read

b) Memory register and write
c) Data register and read
d) Address register and read

(18). The contents of the program counter is the _______ of the instruction to be
run:

a) Data
b) Address
c) Counter
d) None of these

(19). Which unit acts as the brain of the computer which control other
peripherals and interfaces:

a) Memory unit
b) Cache unit
c) Timing and control unit
d) None of these

(20). It contains the ____________stack for PC storage during subroutine

calls and input/output interrupt services:

a) Seven- level hardware

 b) Eight- level hardware
c) One- level hardware
d) Three- level hardware

(21). Which unit works as an interface between the processor and all the
memories on chip or off- chip:

a) Timing unit
b) Control unit
c) Memory control unit
d)All of these

(22). ________ is given an instruction in machine language this instruction

is fetched from the memory by the CPU to execute:

a) ALU
b) CPU
c) MU
d) All of these

(23). Which cycle refers to the time period during which one instruction is
fetched and executed by the CPU:

a) Fetch cycle
b) Instruction cycle
c) Decode cycle
d) Execute cycle

(24). How many stages of instruction cycle:

a) 5
b) 6
c) 4
d) 7

(25). Which are stages of instruction cycle:

a) Fetch
b) Decode
c) Execute
d) Derive effective address of the instruction
e. All of these

(26). Which instruction are 32 bits long , with extra 16 bits:

a) Memory reference instruction

b) Memory reference format
c) Both
d) None of these

(27). Which is addressed by sign extending the 16-bit displacement to 32-bit:

 a) Memory address
b) Effectivememory address
c) Both a and b
d) None of these

(28). Which are instruction in which two machine cycle are required:

a) Instruction cycle
b) Memory reference instruction
c) Both
d) None of these

(29). Which instruction are used in multithreaded parallel processor architecture:

a) Memory reference instruction

b) Memory reference format
c) Both
d) None of these

(30). ____________ is an external hardware event which causes the CPU to

interrupt the current instruction sequence:

a) Input interrupt
b) Output interrupt
c) Both
d) None of these

(31). ISR stand for:

a) Interrupt save routine

b) Interrupt service routine
c) Input stages routine
d) All of these

(32). Which interrupt services save all the register and flags:

a) Save interrupt
b) Input/output interrupt
c) Service interrupt
d) All of these

(33). IRET stand for:

a) Interrupt enter
b) Interrupt return
c) Interrupt delete
d) None of these

(34). Which are benefit of input/output interrupt:

a) It is an external analogy to exceptions
b) The processor initiates and perform all I/O operation
c) The data is transferred into the memory through interrupt handler
 d) All of these

(35). Which are the not causes of the interrupt:

a) In any single device

b) In processor poll devices
c) It is an external analogy to exception
d) None of these

(36). Which are the causes of the interrupt:

a) In any single device

b) In processor poll devices
c) In a device whose ID number is stored on the address bus
d )All of these

(37). Which are the functioning of I/O interrupt:

a) The processor organizes all the I/O operation for smooth functioning
b) After completing the I/O operation the device interrupt the processor
c) Both
d) None of these

(39). What is the main function of a bus in a computer system?

a) To store data permanently

b) To connect components and transfer data
c) To execute instructions
d) To perform arithmetic operations

(40). Which of the following is NOT a type of bus in a computer system?

a) Data bus
b) Address bus
c) Control bus
d) Logic bus

(41). The data bus is used to:

a) Transmit addresses between components

b) Carry control signals
c) Transfer data between memory and processor
d) Synchronize clock signals

(42). The width of the address bus determines the:

a) Data transfer rate

b) Number of memory locations addressable
c) Speed of the processor
d) Type of bus arbitration
(43). The width of the address bus determines the:

a) Data transfer rate

b) Number of memory locations addressable
c) Speed of the processor
d) Type of bus arbitration

(44). What does the control bus carry?

a) Instructions for arithmetic operations

b) Data between CPU and memory
c) Control signals for coordination and communication
d) Memory addresses

(45). Which bus is bi-directional in most computer systems?

a) Address bus
b) Data bus
c) Control bus
d) Instruction bus

(46). The technique used to resolve bus contention is called:

a) Bus synchronization
b) Bus arbitration
c) Bus encoding
d) Bus multiplexing

(47). What is an interconnection structure in a computer system?

a) A network used to connect computers

b) The mechanism for connecting various system components
c) The structure of the CPU
d) The architecture of memory

(50). Which of the following is NOT an interconnection structure?

a) Single bus structure
b) Multibus structure
c) Crossbar switch
d) Stack architecture

(51). What is the primary drawback of a single-bus structure?

a) High cost
b) Low flexibility
c) Bottleneck due to limited data transfer capacity
 d) Complexity in design

(55). What type of interconnection structure uses a separate path for each device
to communicate?

a) Bus
b) Crossbar switch
c) Daisy chain
d) Ring

(56). In a time-shared bus, how is bus access granted to multiple devices?

a) Priority-based access
b) Random allocation
c) Time-division multiplexing
d) By polling

(57). Which interconnection structure is most scalable for large systems?

a) Single bus
b) Multistage network
c) Daisy chain
d) Point-to-point

(58). A point-to-point interconnection structure:

a) Involves direct links between devices

b) Uses a shared communication medium
c) Has a central controlling device
d) Requires only one communication channel

(59). What is the purpose of an arbiter in a bus-based interconnection structure?

a) To assign memory addresses

b) To manage bus contention
c) To increase clock speed
d) To decode instructions

(60). A register is a:
a) High-speed storage area
b) Part of the ALU
c) Primary memory
d) Type of secondary memory
(61). Which register holds the address of the next instruction to be executed?

a) Program Counter (PC)

b) Instruction Register (IR)
c) Memory Address Register (MAR)
d) Accumulator (AC)

(62). Which register temporarily stores the data being transferred to or from
memory?

a) MAR
b) Memory Buffer Register (MBR)
c) PC
d) IR

(63). The register used to store intermediate results during computations is

called:

a) MAR
b) Accumulator
c) IR
d) General-purpose register

(64). What is the primary purpose of the stack pointer register?

a) To store instruction addresses

b) To manage function calls and returns
c) To hold the current instruction
d) To point to the top of the stack

(65). A bus in a computer system is used to:

a) Transfer data between components

b) Store data permanently
c) Execute instructions
d) Perform arithmetic operations

(66). Which bus carries the memory addresses?

a) Data Bus
b) Address Bus
c) Control Bus
d) Instruction Bus

(67). The control bus is responsible for:

a) Transferring data
b) Addressing memory
c) Synchronizing operations
d) Holding instructions
(68). A system bus typically consists of:

a) Address, data, and control buses

b) Data and instruction buses only
c) ALU and registers
d) Cache memory and control unit

(69). What determines the width of the data bus?

a) The number of registers

b) The size of data transferred simultaneously
c) The speed of the CPU
d) The size of the address bus

(70). An instruction set is:

a) A collection of operations a CPU can perform

b) A list of hardware components
c) A programming language
d) A memory organization method

(71). What does the opcode in an instruction represent?

a) Operation to be performed
b) Data location
c) Memory address
d) Control signals

(72). Which type of instruction moves data from one location to another?

a) Arithmetic instruction
b) Logical instruction
c) Data transfer instruction
d) Control instruction

(73). In RISC architecture, instructions are typically:

a) Complex and variable-length

b) Simple and fixed-length
c) Fixed-length and microprogrammed
d) Executed in parallel
(74). Control flow instructions are used for:

a) Arithmetic operations
b) Logical operations
c) Changing the sequence of execution
d) Data storage

(75). During the decode phase of the instruction cycle, the instruction is:

a) Executed by the ALU

b) Stored in memory
c) Interpreted to determine the operation
d) Fetched from memory
 4. CENTRAL PROCESSING UNIT
(1). How many types of micro oprations:

a) 2
b) 4
c) 6
d) 8

(2). Which are the operation that a computer performs on data that
put in register:

a) Register transfer
b) Arithmetic
c) Logical
d) All of these

(3). Which micro operations carry information from one register to another:

a) Register transfer
b) Arithmetic
c) Logical
d) All of these

(4). Micro operation is shown as:

a) R1->R2
b) R1<-R2
c) Both
d) None

(5). operation on stored numeric data available in_:

a) Register
b) Data
c) Both
d) None

(6). In arithmetic operation numbers of register and the circuits for addition at

a) ALU
b) MAR
c) Both
d) None

(7). Which operation are implemented using a binary counter or combinational

circuit:
a. Register transfer b. Arithmetic
c. Logical
d. All of these
(8). Which operation is binary type, and are performed on bits string
that is placed in register:

a. Logical micro operation

b. Arithmetic micro operation
c. Both
d. None

(9). Which operation refer bitwise manipulation of contents of register:

a. Logical micro operation

b. Arithmetic micro operation
c. Shift micro operation
d. None of these

(10). Which symbol will be used to denote an micro operation:

a. (^)
b. (v)
c. Both
d. None

(11). which symbol will be denote an AND micro operation:

a. (^)
b. (v)
c. Both
d. None
(12). Which operation are associated with serial transfer of data:

a. Logical micro operation

b. Arithmetic micro operation
c. Shift micro operation
d. None of these

(13). The bits are shifted and the first flip-flop receives its binary information

a. Serial output
b. Serial input
c. Both
d. None

(14). How many types of shift micro operation:

a. 2
b. 4
c. 6
d. 8
(15). Which shift is a shift micro operation which is used to shift a signed
binary number to the left orright:
 a. Logical
b. Arithmetic
c. Both
d. None of these

(16). Which shift is used for signed binary number:

a. Logical
b. Arithmetic
c. Both
d. None of these

(17). Arithmetic left shift is used to multiply a signed number by_:

a. One
b. Two
c. Three
d. All of these

(18). The variable of_______ correspond to hardware register:

a. RAM
b. RTL
c. ALU
d. MAR

(19). The control unit and arithmetic logic unit are know as the ___________:

a. Central program unit

b. CPU
c. Central primary unit
d. None

(20). Which unit is comparable to the central nervous system in

the human body:

a. Output unit
b. Control unit
c. Input unit
d. All of these

(21). ___________ of the primary memory of the computer is limited:

a. Storage capacity
b. Magnetic disk
c. Both
d. None of these
(22). Information is handled in the computer by

a. Electrical digit
b. Electrical component
c. Electronic bit
 d. None of these
(23). 0 and 1 are know as ___________:

a. Byte
b. Bit
c. Digits
d. Component

(24). 0 and 1 abbreviation for:

a. Binary digit
b. Octal digit
c. Both
d. None of these

(25). How many bit of nibble group:

a. 5
b. 4
c. 7
d. 8

(26). How many bit of bytes:

a. 3
b. 4
c. 6
d. 8

(27). Which is the most important component of a digit computer that processes
interprets the instruction and the data contained in computer programs:

a. MU
b. ALU
c. CPU
d. PC

(28). Which part work as a the brain of the computer and performs most of the
calculation:

a. MU
b. PC
c. ALU
d. CPU

(29). Which is the main function of the computer:

a. Execute of programs
b. Execution of programs
c. Both
d. None of these
(30). How many major component make up the CPU:

a. 4
b. 3
c. 6
d. 8

(31). Which register holds the current instruction to be executed:

a. Instruction register
b. Program register
c. Control register
d. None of these

(32). Which register holds the next instruction to be executed:

a. Instruction register
b. Program register
c. Program control register
d. None of these

(33). Which register holds the next instruction to be executed:

a. Instruction register
b. Program register
c. Program control register
d. None of these

(34). Each instruction is also accompanied by a_:

a. Microprocessor
b. Microcode
c. Both
d. None of these

(35). Which are microcomputers commonly used for commercial

data processing, desktop publishing and engineering application:

a. Digital computer
b. Personal computer
c. Both
d. None of these

(36). Which microprocessor has the control unit, memory unit and
arithmetic and logic unit:

a. Pentium IV processor
b. Pentium V processor
c. Pentium III processor
d. None of these
(37). The processing speed of a computer depends on the
__________of the system:
a. Clock speed
b. Motorola
c. Cyrix
d. None of these

(38). 1. _______is the first step in the evolution of programming languages:

a. machine language
b. assembly language
c. code language
d. none of these

(39). Mnemonic refers to:

a. Instructions
b. Code
c. Symbolic codes
d. Assembler

(40). Mnemonic represent:

a. Operation codes
b. Strings
c. Address
d. None of these

(41). To represent addresses in assembly language we use:

a. String characters
b. Arrays
c. Structure
d. Enum

(42). ________generation computers use assembly language:

a. First generation
b. Third generation
c. second generation
d. fourth generation

(43). Assembly language program is called:

a. Object program
b. Source program
c. Oriented program
d. All of these

(44). To invoke assembler following command are given at command line:

a. $ hello.s -o hello.o
 b. $as hello.s –o o
c. $ as hello –o hello.o
d. $ as hello.s –o hello.o

(45). By whom address of external function in the assembly source file

supplied by ______ when activated:

a. Assembler
b. Linker
c. Machine
d. Code

(46). An______ -o option is used for:

a. Input file
b. External file
c. Output file
d. None of these

(47). The assembler translates ismorphically______ mapping from

mnemonic in these statements tomachine instructions:

a. 1:1
b. 2:1
c. 3:3
d. 4:1

(48). Assembler works in______ phases:

a. 1
b. 3
c. 2
d. 4

(49). The assembler in first pass reads the program to collect symbols defined
to collect symbols definedfsets in a table_

a. Hash table
b. Symbol table
c. Both a& b
d. None of these

(50). In second pass, assembler creates _______in binary format for

every instruction in program and then refers to the symbol table
to giving every symbol an______ relating the segment.

a. Code and program

b. Program and instruction
c. Code and offset
d. All of these
(51). which of the 2 files are created by the assembler:

a. List and object file

b. Link and object file
c. Both a & b
d. None of these

(52). A stack in a digital computer is a part of the_:

a. ALU
b. CPU
c. Memory unit
d. None of these

(53). In stack organization address register is known as the:

a. Memory stack
b. Stack pointer
c. Push operation
d. Pop operation

(54). In register stack a stack can be organized by a ______number of register:

a. Infinite number
b. Finite number
c. Both
d. None

(55). Which operation are done by increment or decrement the stack pointer:

a. Push
b. Pop
c. Both
d. None

(56).. In register stack a stack can be a finite number of_:

a. Control word
b. Memory word
c. Transfer word
d. All of these

(57). The stack pointer contains the address of the word that is currently on__:

a. Top of the stack

b. Down of the stack
c. Top and Down both
d. None

(60). In register stack items are removed from the stack by using the_operation:
 a. Push
b. Pop
c. Both
d. None

(61). Which register holds the item that is to be written into the stack
or read out of the stack:

a. SR
b. IR
c. RR
d. DR

(62). In register stack the top item is read from the stack into:

a. SR
b. IR
c. RR
d. DR

(63). In conversion to reverse polish notation the ___and___ operations are

performed at the end:

a. Add and subtract

b. Subtract and multiplication
c. Multiplication and subtract
d. All of these

(64). EA stands for:

a. Effective add
b. Effective absolute
c. Effective address
d. End address

(65). In which addressing the operand is actually present in instruction:

a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

(66). In which addressing the simplest addressing mode where an operand

is fetched from memory is_:

a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

(67). which addressing is a way of direct addressing:

 a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

(68). In which mode the main memory location holds the EA of the operand

a. Immediate addressing
b. Direct addressing
c. Register addressing
d. Indirect addressing

(69). In which instruction are used to perform Boolean operation on

non-numerical data:

a. Logical and bit manipulation

b. Shift manipulation
c. Circular manipulation
d. None of these

(70). In the case of a left arithmetic shift , zeros are Shifted to the ______:

a. Left
b. Right
c. Up
d. Down

(71). In the case of a right arithmetic shift the sign bit values are shifted to the_:

a. Left
b. Right
c. Up
d. Down

(72). . What does CISC stand for in computer architecture?

a) Complex Instruction Set Computer

b) Combined Integrated System Computing
c) Central Instruction System Computer
d) Complex Instruction Storage Circuit

(73). Which of the following is a key characteristic of CISC architecture?

a) Fewer instructions with simple execution

b) Large number of complex instructions
c) Fixed instruction length
d) Requires a large number of registers
(74). One advantage of CISC architecture is:

a) Simpler control unit design

b) Faster execution of instructions
c) Reduced program size due to complex instructions
d) Higher clock speed

(75). Which of the following processors is an example of CISC architecture?

a) ARM
b) Intel x86
c) MIPS
d) SPARC
 5. MEMORY ORGANIZATION
(1). In memory transfer location address is supplied by____ that
puts this on address bus:

a) ALU
b) CPU
c) MAR
d) MDR

(2). How many types of memory transfer operation:

a) 1
b) 2
c) 3
d) 4

(3). Operation of memory transfer are:

a) Read
b) Write
c) Both
d) None

(4). In memory read the operation puts memoryaddress on to a register known

as :

a) PC
b) ALU
c) MAR
d) All of these

(5). Which operation puts memory address in memory address register and
data in DR:

a) Memory read
b) Memory write
c) Both
d) None

(6). ______of primary memory of the computer is limited:

a) Storsge capacity
b) Magnetic disk
c) Both
d) None of these
(7). Instruction formats contains the memory address of the _____.

a) Memory data
b) Main memory
c) CPU
d) ALU

(8). Memory -mapped ___is used this is just another memory address.

a) Input
b) Output
c) Both
d) None

(10). UMA stand for :

a) Uniform memory access

b) Unit memory access
c) Both
d) None

(11). NUMA stand for :

a) Number uniform memory access

b) Not uniform memory access
c) Non uniform memory access
b) All of these

(12). . What is the primary purpose of cache memory?

a) To store large amounts of data permanently

b) To speed up data access for the CPU
c) To replace RAM
d) To store backup files

(13). Cache memory is typically:

a) Slower than RAM but faster than secondary storage

b) Faster than RAM but slower than CPU registers
c) Slower than secondary storage
d) Equal in speed to secondary storage

(14). Which of the following is true about cache memory?

a) It is non-volatile
b) It is placed between the CPU and main memory
c) It is used for long-term storage
d) It is larger than RAM
(15). What type of cache is integrated directly into the processor chip?

a) L1 cache
b) L2 cache
c) L3 cache
d) Virtual cache

(16). Which cache level is typically the largest in size?

a) L1 cache
b) L2 cache
c) L3 cache
d) None of the above

(17). The mapping technique where each block of main memory maps to a
specific cache line is called:

a) Associative mapping
b) Direct mapping
c) Set-associative mapping
d) Random mapping

(18). Which mapping technique allows a block of memory to be stored in any

cache line?

a) Fully associative mapping

b) Direct mapping
c) Set-associative mapping
d) Random mapping

(19). In set-associative mapping, a cache is divided into:

a) Sets
b) Blocks
c) Words
d) Pages

(20). What happens when the CPU references a memory location not present in
the cache?
a) Cache hit
b) Cache miss
c) Segmentation fault
d) Page fault
(21). What does the term "cache hit ratio" refer to?

a) The percentage of memory accesses found in the cache

b) The percentage of cache blocks replaced
c) The number of accesses to main memory
d) The amount of data transferred to the cache

(22). Which replacement policy replaces the block that has not been used for the
longest time?

a) FIFO (First-In-First-Out)
b) LRU (Least Recently Used)
c) Random Replacement
d) MRU (Most Recently Used)

(23). What is "write-through" in cache memory?

a) Writing data only to the cache

b) Writing data to both cache and main memory simultaneously
c) Writing data only to main memory
d) Writing data only when the block is replaced

(24). In a "write-back" policy, data is written to the main memory:

a) Immediately after being written to the cache

b) Only when the cache block is replaced
c) Only during a cache miss
d) At fixed intervals

(25). Which type of cache is closer to the CPU?

a) L1 cache
b) L2 cache
c) L3 cache
d) RAM

(26). Which factor does NOT affect cache performance?

a) Cache size
b) Block size
c) Mapping technique
d) Hard disk speed
(27). Cache coherence is an issue in:

a) Single-core processors
b) Multi-core processors
c) Virtual memory
d) Secondary storage

(28). The smallest unit of data that can be transferred between cache and main
memory is called:

a) Word
b) Block
c) Set
d) Page

(29). Which mapping technique provides a compromise between direct mapping

and fully associative mapping?

a) Set-associative mapping
b) Random mapping
c) Multi-level mapping
d) Hierarchical mapping

(30). What is the main disadvantage of increasing cache size?

a) Increased power consumption

b) Decreased hit ratio
c) Increased cache miss rate
d) Decreased data transfer rate

(31). In a two-level cache system, if L1 cache has a hit rate of 95% and L2 cache
has a hit rate of 90%, the overall hit rate is approximately:

a) 85%
b) 90.5%
c) 99.5%
d) 95.5%
(32). What is the purpose of memory mapping in a cache?

a) To reduce the size of the memory

b) To organize and locate data in the cache
c) To increase CPU clock speed
d) To eliminate cache misses

(33). In direct mapping, each block of main memory maps to:

a) A specific cache line

b) Any cache line
c) A set of cache lines
d) Multiple cache lines

(34). What is the major drawback of direct mapping?

a) High complexity
b) Increased cost
c) Higher conflict misses
d) Requires associative memory

(35). In fully associative mapping, a block can be placed in:

a) A specific cache line

b) Any cache line
c) A fixed set of cache lines
d) None of the above

(36). Which mapping technique is a compromise between direct and fully

associative mapping?

a) Random mapping
b) Set-associative mapping
c) Sequential mapping
d) Virtual mapping

(37). In set-associative mapping, a cache is divided into:

a) Blocks
b) Sets
c) Words
d) Pages
(39). In a 2-way set-associative cache, each set contains:

a) 1 line
b) 2 lines
c) 4 lines
d) All cache lines

(40). The tag field in a cache address is used to:

a) Select the cache line within a set

b) Identify the block stored in the cache
c) Store the data in the cache
d) Represent the address of main memory

(41). Which of the following is NOT true about fully associative mapping?

a) It eliminates conflict misses

b) It is expensive to implement
c) Each block can go to only one cache line
d) It uses more complex hardware

(42). Which mapping technique uses both index and tag bits?

a) Fully associative mapping

b) Direct mapping
c) Set-associative mapping
d) Sequential mapping

(43). Associative memory is also known as:

a) Virtual memory
b) Content-addressable memory (CAM)
c) Secondary memory
d) Cache memory

(44). What is the key feature of associative memory?

a) Data is accessed by address

b) Data is accessed by content
c) Data is stored sequentially
d) Data is stored randomly

(45). Which memory organization is used in associative memory?

a) Row-column organization
b) Tag-data organization
 c) Bit-slice organization
d) Content-based organization

(46). Associative memory is most commonly used in:

a) Secondary storage
b) Cache memory
c) Page tables
d) Registers

(46). What is the major drawback of associative memory?

a) Slow access time

b) High cost
c) Low capacity
d) Limited compatibility

(47). The associative memory matches stored data with a given:

a) Address
b) Content or key
c) Register value
d) Tag

(48). Which technique is used to resolve conflicts in associative memory?

a) LRU replacement
b) Hashing
c) Direct mapping
d) Segmentation

(49). The time required to search an associative memory is:

a) Proportional to the size of the memory

b) Constant
c) Linear
d) Exponential

(50). Associative memory is faster than RAM because:

a) It has a higher clock speed

b) It performs parallel searches
c) It uses less power
d) It has a larger storage capacity

(51). Which of the following is a key advantage of associative memory?

a) Low cost
b) High speed for searching data by content
c) Unlimited storage capacity
d) Sequential access of data
(52). What is cache memory primarily used for?

a) Long-term data storage

b) Temporary storage to reduce access time
c) Permanent backup of data
d) To execute instructions directly

(53). What is the technique called where frequently accessed data is stored in
cache memory?

a) Prefetching
b) Spooling
c) Caching
d) Paging

(54). What is the replacement policy in cache memory?

a) It determines which block to replace when the cache is full

b) It specifies the size of the cache
c) It defines the data to be removed from main memory
d) It organizes the memory hierarchy

(55). Which of the following is NOT a cache replacement policy?

a) Least Recently Used (LRU)

b) First-In, First-Out (FIFO)
c) Most Frequently Used (MFU)
d) Random Access Replacement

(56). The hit ratio in cache memory is defined as:

a) The ratio of CPU usage to memory usage

b) The percentage of successful cache accesses
c) The time taken to access data in cache
d) The ratio of cache size to main memory size

(57). What is the main advantage of a write-back cache over a write-through

cache?

a) Higher reliability
b) Faster write operations
c) Simplified implementation
d) Reduced complexity
(58). What does the term “dirty bit” in cache memory indicate?

a) The cache block contains invalid data

b) The cache block has been modified but not written to main
memory
c) The cache block is empty
d) The cache block is full

(59). Which level of cache is closest to the CPU?

a) L1 Cache
b) L2 Cache
c) L3 Cache
d) RAM

(60). Which factor directly affects the speed improvement offered by cache
memory?

a) Cache size and hit ratio

b) Cache color and material
c) Cache write policy only
d) Number of I/O devices connected

(61). Associative memory is also known as:

a) Virtual memory
b) Content Addressable Memory (CAM)
c) Secondary memory
d) Random Access Memory (RAM)

(62). In associative memory, data is accessed based on:

a) Its address
b) Its content
c) Its location in memory
d) A specific algorithm

(63). What is the main advantage of associative memory?

a) It is cheaper than RAM

b) Faster search based on data content
c) Requires no power to operate
d) Large storage capacity
(64). Which operation is performed faster in associative memory compared to
regular memory?

a) Sequential access
b) Content search
c) Random access
d) Batch processing

(65). What is the primary drawback of associative memory?

a) Slow access speed

b) High cost per bit
c) Small storage size
d) Complex data structure

(66). In associative memory, the match logic compares:

a) Data bits only

b) Address bits only
c) Both data and address bits
d) Control signals

(67). Which of the following is an application of associative memory?

a) Virtual memory paging

b) Translation Lookaside Buffer (TLB)
c) Long-term data storage
d) Disk scheduling

(68). Associative memory is commonly used in:

a) Cache memory
b) Main memory
c) Secondary memory
d) Instruction registers

(69). Which of the following is a cache mapping technique?

a) Virtual mapping
b) Direct mapping
c) Cluster mapping
d) Random mapping
(70). In direct mapping, each block of main memory maps to:

a) A single cache line

b) Multiple cache lines
c) A specific set of cache lines
d) Random cache lines

(71). What is the primary disadvantage of direct mapping?

a) High cost
b) High complexity
c) Frequent conflicts between blocks
d) Slow memory access

(72). In fully associative mapping, a block can be placed in:

a) A specific cache line

b) Any cache line
c) The first available cache line
d) Only one cache level

(73). Which mapping technique combines features of both direct and

associative mapping?

a) Segmented mapping
b) Set-associative mapping
c) Hybrid mapping
d) Block mapping

(74). Set-associative mapping divides the cache into:

a) Blocks of fixed size

b) Sets containing multiple lines
c) Segments with overlapping data
d) Randomly assigned regions

(75). What determines the number of cache lines in set-associative mapping?

a) Number of sets
b) Cache size
c) Number of blocks
d) Associativity degree
 6. Input-Output Organization
(1). Advantages of isolated I/O are:

a. Commonly usable
b. Small number of I/O instructions
c. Both a & b
d. None of these

(2). In _______ addressing technique separate address space is used for

both memory and I/O device:

a. Memory-mapped I/O
b. Isolated I/O
c. Both a & b
d. None of these

(3). _______is a single address space for storing both memory and I/O devices:

a. Memory-mapped I/O
b. Isolated I/O
c. Separate I/O
d. Optimum I/O

(4). Following are the disadvantages of memorymapped I/O are:

a. Valuable memory address space used up

b. I/O module register treated as memory addresses
c. Same machine intersection used to access both memory and I/O device
d. All of these

(5). Who determine the address of I/O interface:

a. Register select
b. Chip select
c. Both a & b
d. None of these

(6). 2 control lines in I/O interface is:

a. RD, WR
b. RD,DATA
c. WR, DATA
d. RD, MEMORY

(7). In I/O interface RS1 and RS0 are used for selecting:
 a. Memory
b. Register
c. CPU
d. Buffer

(8). If CPU and I/O interface share a common bus than transfer of data
b/w 2 units is said to be:

a. Synchronous
b. Asynchronous
c. Clock dependent
d. Decoder independent

(9.) Modes of transfer b/w computer and I/O device are:

a. Programmed I/O
b. Interrupt-initiated I/O
c. DMA
d. Dedicated processor such as IOP and DCP
e. All of these

(10). Which of the following is an example of an input device?

a) Printer
b) Keyboard
c) Monitor
d) Speaker

(11). Which of the following is an output device?

a) Mouse
b) Monitor
c) Scanner
d) Microphone

(12). Which device is used to store data permanently and is an example of an

output device?

a) Printer
b) Flash drive
c) Hard drive
d) Scanner

(13). What is the primary function of an input device?

a) To process data
b) To provide output
 c) To convert human-readable data into machine-readable form
d) To store data permanently

(14). Which of the following is an example of a storage device that also serves
as an input and output device?

a) Monitor
b) Hard drive
c) Keyboard
d) Printer

(15). A device that allows communication between humans and computers is

known as:

a) Storage device
b) Control device
c) I/O device
d) Processing device

(16). Which of the following devices is used to capture graphical data?

a) Mouse
b) Monitor
c) Scanner
d) Printer

(17). Which of the following devices is used to listen to audio output from a
computer?

a) Microphone
b) Speakers
c) Webcam
d) Printer

(18). A keyboard is primarily used as:

a) An output device
b) A storage device
c) An input device
d) A control device

(19) . The function of a display monitor is to:

a) Capture user input

b) Store data
 c) Provide graphical output
d) Convert audio signals into visual signals

(20). The main function of an I/O module is to:

a) Manage data transfer between memory and CPU

b) Handle communication between external devices and CPU
c) Perform data processing operations
d) Store instructions

(21). What is the main purpose of an I/O controller?

a) To directly execute instructions

b) To control external devices and manage data transfer
c) To provide error-checking mechanisms
d) To store data permanently

(22). Which of the following is a task of an I/O module?

a) Buffer data
b) Perform arithmetic calculations
c) Directly access main memory
d) Perform logical operations

(25). Which of the following is NOT typically performed by an I/O module?

a) Interrupt handling
b) Error detection
c) Arithmetic operations
d) Data transfer control

(26). Which signal does the I/O module send to the CPU after a successful data
transfer?

a) Acknowledge signal
b) Interrupt signal
c) Request signal
d) Control signal

(27). In an I/O module, which register holds the data being transferred to/from
an I/O device?
a) Status register
b) Control register
 c) Data register
d) Address register

(28). What is the function of the status register in an I/O module?

a) To store data
b) To store control commands
c) To indicate the current status of an I/O operation..
d) To store memory addresses

(29). Which of the following methods can an I/O module use to communicate
with the CPU?

a) Using interrupt signals

b) Direct memory access
c) Through data transfer on the bus
d) All of the above

(30). Which of the following tasks is NOT done by an I/O module?

a) Handling device communication

b) Error checking
c) Performing calculations
d) Buffering data

(31). What is the primary benefit of using an I/O module in a computer system?

a) Increased memory capacity

b) Improved CPU performance
c) Efficient handling of data transfer between devices and CPU
d) Faster processing of instructions

(32). In programmed I/O, who controls the data transfer?

a) The CPU
b) The I/O module
c) The operating system
d) The DMA controller

(33). Which of the following is a disadvantage of programmed I/O?

a) It allows for fast data transfer

 b) It requires a lot of CPU time
c) It involves minimal CPU interaction
d) It is simple to implement

(34). In programmed I/O, when does the CPU initiate the I/O operation?

a) When the I/O device is ready

b) When the I/O operation is complete
c) At fixed intervals
d) After every interrupt

(35). Which of the following I/O operations is typically used in programmed

I/O?

a) Memory-mapped I/O
b) Polling for I/O status
c) DMA transfer
d) Direct addressing

(36). Which of the following is used by the CPU to control programmed I/O
operations?

a) Data registers
b) Control registers
c) Status registers
d) Address registers

(37). In programmed I/O, the CPU communicates with the I/O device using
which of the following?

a) Direct memory access

b) Control and data registers
c) Virtual memory
d) DMA bus

(38). What does the CPU do in programmed I/O when a device is busy?

a) Perform other tasks

b) Wait and keep polling
c) Generate interrupts
d) Send a signal to the device

(40). In programmed I/O, data transfer is initiated by:

a) The device
 b) The CPU
c) The I/O module
d) The DMA controller

(41). Which of the following is true about programmed I/O?

a) The CPU can perform other tasks while waiting for I/O
b) It involves high CPU involvement in I/O transfers
c) It uses a separate DMA controller for data transfer
d) The CPU automatically processes data as it is received

(42). Which technique is commonly used in programmed I/O to handle multiple

I/O operations?
a) Interrupt-driven I/O
b) Polling
c) Direct memory access
d) Multiple processing units

(43). What is the main advantage of using DMA for I/O?

a) Reduces CPU involvement in data transfer

b) Increases CPU load during data transfer
c) Speeds up data access from secondary storage
d) Provides better memory access speed

(44). In DMA, which component initiates the data transfer?

a) The I/O device

b) The CPU
c) The DMA controller
d) The operating system

(45). During a DMA operation, the CPU is:

a) Actively involved in managing data transfer

b) Free to perform other tasks
c) Handling all memory accesses
d) Not used at all

(46). Which of the following is the primary role of the DMA controller?

a) To monitor memory accesses

b) To control and manage data transfers directly between memory
and I/O devices
c) To handle CPU interrupts
d) To manage CPU registers
(47). Which signal does the DMA controller use to request the system bus?

a) Interrupt signal
b) Bus request signal
c) Acknowledge signal
d) Ready signal

(48). What happens when the DMA controller takes control of the bus?

a) It processes an interrupt
b) It transfers data directly between memory and I/O devices
c) The CPU is suspended
d) The memory is accessed by the CPU

(49). What is the advantage of DMA over programmed I/O?

a) It reduces the CPU workload

b) It increases CPU involvement
c) It requires less memory
d) It provides higher data accuracy

(50). Which DMA transfer mode allows the DMA controller to take control of
the bus for the entire data transfer?

a) Cycle stealing
b) Block transfer
c) Demand transfer
d) Burst transfer

(51). In DMA, what happens once the data transfer is complete?

a) The DMA controller releases the bus

b) The CPU resumes control of the bus
c) An interrupt is triggered
d) The memory is automatically cleared

(52). Which mode in DMA allows for the CPU to be involved in the data
transfer process?
a) Block transfer
b) Cycle stealing
c) Burst transfer
d) Direct memory addressing
(53). In DMA, which component is responsible for controlling the data transfer
process?

a) I/O module
b) CPU
c) DMA controller
d) Operating system

(54). Which of the following DMA modes transfers a large block of data without
interruption?

a) Cycle stealing
b) Block transfer
c) Burst transfer
d) Interrupt-driven transfer

(55). What is the role of the DMA request signal?

a) It informs the CPU of a pending interrupt

b) It indicates that a device is ready for data transfer
c) It notifies the DMA controller to request the bus
d) It signals the completion of the data transfer

(56). What is the major disadvantage of DMA compared to programmed I/O?

a) Higher CPU overhead

b) Slower data transfer
c) More complex to implement
d) Limited to single device operations

(57). . Which of the following is an input device?

a) Printer
b) Keyboard
c) Monitor
d) Speaker

(58). External devices are categorized into three parts:

a) Input, output, and processing
b) Input, output, and storage
c) Primary, secondary, and tertiary devices
d) Peripheral, internal, and secondary devices
(59). Which of the following devices is considered an output device?

a) Mouse
b) Scanner
c) Monitor
d) Microphone

(60). What is the function of an external storage device?

a) Process data
b) Execute instructions
c) Store data permanently
d) Manage cache memory

(61). The speed of I/O devices is typically:

a) Faster than CPU operations

b) The same as CPU operations
c) Slower than CPU operations
d) Independent of CPU operations

(62). What is the main role of an I/O module?

a) To execute instructions
b) To act as an interface between the CPU and I/O devices
c) To store data temporarily
d) To enhance processing speed

(63). Which of the following is NOT a function of an I/O module?

a) Device communication
b) Data buffering
c) Instruction decoding
d) Error detection

(64). What does an I/O module use to communicate with the CPU?

a) ALU
b) Registers
c) System bus
d) Cache memory
(65). The I/O module transfers data between external devices and:

a) Cache memory
b) Main memory
c) ALU
d) ROM

(66). Which of the following is an I/O module used for?

a) Instruction fetching
b) Communication between devices and the system
c) Program execution
d) Clock synchronization

(67). In programmed I/O, the CPU:

a) Continuously polls the device for its status

b) Directly executes I/O operations
c) Delegates I/O tasks to the DMA
d) Uses interrupts for device status checking

(68). Programmed I/O is efficient when:

a) Data transfer is large and continuous

b) The device is slower than the CPU
c) The device is faster than the CPU
d) The CPU is idle

(69). What is a major disadvantage of programmed I/O?

a) High memory consumption

b) CPU remains idle during I/O operations
c) Wastes CPU cycles due to busy-waiting
d) Limited device compatibility

(70). In programmed I/O, data transfer is controlled by:

a) DMA controller
b) CPU
c) Peripheral device
d) Cache memory
(71). Which of the following is NOT true about programmed I/O?

a) It uses polling
b) CPU checks device status regularly
c) It is suitable for high-speed devices
d) It requires CPU intervention for each data transfer

(72). In interrupt-driven I/O, the CPU is notified by the device when:

a) The device is idle

b) The device completes the task
c) The CPU sends a polling signal
d) The cache memory is full

(73). Interrupt-driven I/O eliminates:

a) CPU intervention
b) The need for external devices
c) Polling by the CPU
d) Error detection in I/O operations

(74). What is the main advantage of interrupt-driven I/O?

a) Reduced hardware complexity

b) Faster CPU processing
c) Efficient use of CPU cycles
d) Simplified programming

(75). Interrupt-driven I/O is more efficient than programmed I/O because:

a) It avoids busy-waiting
b) It does not involve the CPU
c) It works only with high-speed devices
d) It uses cache memory