26 FIELD EFFECT RANSISTOR

26.1. What is a FET?

transistor. It is a three-terminal uninel.
The acronym 'FET' stands for field effect olar
device in which current is controlled by an
electric field as is done in vacuum t0lid
s. Bro
FETs:
speaking, there are two types of
(a) junction field effect transistor (JFET),
metal-oxide semiconductor FET (MOSFET).
(b)
It is also called insulated-gate FET (IGFET).
It may be further subdivided into
MOSFET i.e., DE MOSFET,
(i) depletion-enhancement MOSFET.
(i) enhancement-only MOSFET i.e., E-only N-channel devices.
Both of these can be either P-channel or
The FET family tree is shown below:

FET

Metal-oxide Semiconductor FET

Junction FET (JFET)
(MOSFET/IGFET)

DE MOSFET E-only MOSFET

N-Channel P-Channel

D +DD D-VDD
N-Channel P-Chan
DO+DD

OS

s
N-Channel P-Channel s
D 9+pDb D9-VDD

400
A Yiansistors
rs
401

nctionFET(JFET)

Basic Construction

Eio, 26.1. it can be fabricated with either an N-channel or.P-channel though

Ownally preferred. For fabricating an N-channel JFET, first a narrow bar of N-type
I sg e n e r a l

rial is taken and then

then two P-type junctions are diffused on pposite sides of
nd

T
o n d u c t o r m a t e r i a l

26.1 (a)).
26.1 ( a l These junctions form two P-N diodes or gates and the area between
(ig.
part Gate
dle Gate
Drain Drain

N-channel P-channel

Source Source

OD OD

N P

N-channel P-channel

OS
OD OD

GO GO-

os
Fig. 26.1
c a l l e d channel. The two P-regions are internally connected and a single lead is
I c h is called gate terminal. Ohmic contacts (direct electrical connections) are made
wo ends of the bar-one lead is called source terminal S and the
lential difference is established between drain and source,
other
current
drain
flows
terminal
along the
D.
length
a thr
ity carri ugh the channel located between the two P-regions. The curent consists of only
ept thoe which, in the present case, are electrons. P-channel FET is similar in construc-
g h thes P-type bar and two N-type junctions. The majority carriers are holes which
loy channel located between the two N-regions or gates.
DWing FET
Soureei snotation
ome
is worth remembering:
the terminal through which majority carriers enter the bar. Since carriers
rom it, it is called the source.
402
Basi
2. Drain. It is the terminal through which majority carriers leave the ba,
voltage Vps drives the drain current Ip. The dran-
3. Gate. These are two internally-connected heavily-doped regions m
junctions. The gate-source voltage Vas reverse-biases the gates,
4. Channel. It is the space between two gates through which majority
source to drain when Vps is applied.
aiority carriers pa
Schematic symbols for N-channel and P-channel JFET are shown in Fio e
26.1inFig.
kept in mind that arrow always points to N-type material.
gate (e).
(6) Theory of Operation
While discussing the theory of operation of a JFET, it should be kept in.
n
1. Gates are always reverse-biased. Hence, gate current Ig 1S practically zertha
2. The source terminal is always connected to that end of the drain supplv.
wt
charge carriers. In an N-channel JFET, source terminal ch Dto
necessary
negative end of the drain voltage supply (for obtaining electrons). In a pee tovide
is connected to the positive end of the drain voltage supply for getting hol channel y
through the channel.
Let us now consider an N-channel JFET and discuss its working when eitha
ther Vcs o
both are changed.
)When Ves = 0 and Vps = 0D
In this case, drain current Ip = 0, because Vps = 0. The depletion region
junctions are of equal thickness and symmetrical as shown in Fig. 26.2 (a). regions around te
() When Ves = 0 and Vps is increased from zero
For this purpose, the JFET is connected to the Vpp supply as shown in Fig. 26.2 (h
trons (which are the majority carriers) flow from S to D, whereas conventional de
flows through the channel from D to S. Now, the gate-to-channel bias at any pointalongthe
is =1 VosI+I Vslie., the numerical sum of the two voltages. In the presentcase, chan
Vas 0. Hence gate-chan-
Extemal
nel reverse bias is provided QD Do-
by Vps alone. Since the
value of VDS keeps decreas-
ing (due to progressive
N
drop alongthe channel) as
we go from D to S, the
gate-channel bias also de- P P
creases accordingly. It has
maximum value in the
drain-gate region and mini-
mum in the source-gate re- Vos=O
gion. Hence, depletion
regions penetrate more
deeply into the channel in oS
the drain-gate region than VpsVpo
in the source-gate region. as= Voss=0
This explains why the de
pletion regions become (a) (6)
wedge shaped when VpS is Fig. 26.2
applied Fig. 26.2 (b)).
As Vps is gradually in-
creased from zero, Ip increases proportionally as per Ohm's law. It is found that tor sn
o eia
values of ps, the N-type channel material acts like a resistor of constant valuentefo
Vos being smal, the depletion regions are not large enough to have any Sign s
channel cross-section and, hence, its resistance. Consequently, Ip increases lineay
creased from zero onwards (Fig. 26.6). critical1
This ohmic relationship between Vps and Ip continues til1 Vps reaches a certau
 the gate is diffused
into Little inerease in
concentration, drain
P-type
PN junetion. This is with increasing current is
the N channel, creating
a

electrode which will

control drain-to-source
an avalanche effect
voltagobserved
«

the terminal or
eurrent In, from S to
D. is caused (to be
due to
diode tage Unt
de hrae until
breakdown
the flow of drain If now the
explained later).
gate is made
to the source and the aive wis
negative with tesper
again varied fromdrain-source u Te
21-3. CHARACTERISTIC
once
CURVES OF THE JFET the curve is of a similar
zero
up to bre oltage in
down. shape but akdown,
negative shift,
diagram Apparently,
It can be seen from the preceding a ifted
that application of a voltage Vns
from drain gate has reduced drain voltaue
age on the
current,
to source will cause
electrons to flow through negative voltage the grid of amuch as a
on

the channel. The amount of

curreni In will crease plate current. tube will
value of Vns of the F ET cannot be However, the oper
be determined, initially, by the explained as
since it isjustthe ohmic resistance of the bar
the tbube is
explained, by just considering electrons,
from S to D that is limiting current.
But saying that the and
and
negative gate repelled eletr.
what effect will a voitage Vcs from gate to since it is possible to have a
source have on this drain current for a given in which a positive gate
P-channel FET,crons,
voltage will also redti
drain-to-source voltage? drain current. See Fig. 21-4.
Let us assume first that VGs 0 V. (The
gate is shorted to the source.) The PN junction
is not reverse biased. As Vps is inereased,
drain current will increase also in a nearly
linear mnanner until, at some voltage between
2V and 8 V, a saturation effect is noted, and
a "knee" develops in the characteristic curves
as shown in Fig. 21-3.
VGO
t
GS

GS 0 V
GS Uv

4tKnee 'D
5 mA
-0.2 V
+0.5 V

-04V
+1.0V

-0.6 V
-0.8 V +1.5 V

10 15 20 26
Drain to-5ource voltaye, yoits
-25 V
' s f o r a

curv
Fig. 21-3. Typical characteristic curves of an characteristic

Nchannel FET. Fig. 21-4. Symbol n d

Pchannel FET.
 FIELD-EFFECT TRANSISTOR AMPLIFIERs
359

the P-channel type, in which

However,
in
are he current carriers, a
altogether and cuts off drain current. This
(positi
value of gate voltage is
holes could be considered as appropriately called
gate repelling the
positive
pinch-off voltage, Vp, and is referred to
in the
holes. specifications as Vcs(ofn: Por example,
a 2N3819
214. PRINCIPLES OF
N-channel FET has a
-8 V, at which VGs(off) 01
Ip 2 nA (nanoampere)
OF THE JFET VDS 15 V. when
OPERATION
The mechanism of current
the control ofdrain current through control is
Actually
a Con-
dependent upon the degree to which theclearly
the channel is not a repelling effect but electric field (due to the
or narrowing OI the channel effect. charge in the deple
stricting tion region) extends into the
the gate achieve this? channel and
How does
Consider what happens to the PN junction provides the effect of decreasing the conduct
between gate and source under reverse biased ivity through the transistor. Hence the name
of or
conditions, as depicted in Fig. 21-5. field effect transistor, FET.

Assume for the present no voltage is applied 21-5. EFFECT OF

VDS
between D and S. With a small reverse bias, ON CHANNEL CONDUCTIVITY
sayVGs1V, the depletion region at the The depletion region is not
junction is quite narrow. Electrons have been symmetrical
around the PN junction when a
drawn from the junction in the N-type material, voltage is
leaving bound, immobile positive ions in that applied from drain to source, but is wider (W
region of the channel, effectively reducing the is smaller in the
previous diagrams) the closer
one moves toward the drain. This is
width and conductivity of the channel.
(Sim- explained
ilarly negative ions are left in the P-type by considering the answer to the following
material near the question.
junction.) As the reverse Why, when Vcs was zero (no reverse bias
bias is increased to -3 V and -6
tion
V, the deple on the gate), did the drain current
region or space-charge region widens, Ip begin to
level off in the characteristic curves when
reaching ever further into the channel and Vps
Testricting the passage of electrons from S to exceeded a certain value?
D when a Consider the JFET with G shorted to S and
voltage is applied. Finally, a value
of a very restricted model of the
device, as shown
voltage from gate to source can be
applied that pinches off in Fig. 21-6.
channel conduction

9D

w
3v v
N N

Fig. 21-5. Effect ofreverse bias on the width of the channel