Part 1: Introduction to VHDL

1. What does VHDL stand for, and what are its primary uses?
2. What are the key differences between VHDL and Verilog?
3. Explain the basic structure of a VHDL code.
4. What is the purpose of the 'entity' and 'architecture' in a VHDL description?
5. What are the data types supported by VHDL? List at least 5.
6. Define the term ‘signal’ in VHDL. How does it differ from a ‘variable’?
7. Explain the difference between ‘combinational’ and ‘sequential’ logic in
VHDL.
8. What is a process in VHDL, and how is it used?
9. What are the differences between ‘signal assignment’ and ‘variable
assignment’ in VHDL?
10. What is the role of the ‘library’ and ‘use’ clauses in VHDL code?
11. What is the significance of the ‘wait’ statement in VHDL?
12. How do you simulate a VHDL design?
13. Explain the concept of ‘configuration’ in VHDL.
14. What is the role of the 'testbench' in VHDL simulations?
15. What are the key operators in VHDL for logic operations? Provide examples.

Part 2: Combinational Circuit Design using VHDL

1. What is a combinational circuit? How is it different from a sequential circuit?

2. Design a 2-input AND gate using VHDL.
3. Write a VHDL code for a 4-input OR gate.
4. How would you design a 2-bit binary adder using VHDL? Provide the code.
5. Explain how multiplexers are designed using VHDL. Write the VHDL code
for a 4-to-1 multiplexer.
6. Write VHDL code to implement a 2-to-4 decoder.
7. Design a 4-bit binary subtractor in VHDL using basic logic gates.
8. What is the role of the 'when-else' statement in VHDL for combinational logic?
9. Explain the concept of ‘if-then-else’ statements in VHDL. Provide an example
using a 3-input AND gate.
10. How can you implement a 3-bit priority encoder in VHDL?
11. Write the VHDL code for a 4-bit full adder using structural modeling.
12. Design a 4-bit magnitude comparator using VHDL.
13. How do you implement a binary-to-BCD (Binary-Coded Decimal) converter
using VHDL?
14. What are the advantages of using the ‘with-select’ statement in VHDL for
designing combinational circuits?
15. How would you design a simple 2-bit ALU (Arithmetic Logic Unit) in VHDL?
16. Write the VHDL code for an even-parity generator for an 8-bit input.
17. Describe how a 1-bit full-adder can be implemented in VHDL.
18. How do you perform simulation and verification for combinational circuits in
VHDL?

Part 3: Advanced Design & Application

1. How would you implement a 4-bit counter in VHDL?

 2. Explain how VHDL can be used for FSM (Finite State Machine) design and
give an example.
3. Describe the concepts of ‘behavioural’ and ‘structural’ modeling in VHDL.
Which one would you prefer for designing combinational circuits and why?
4. Write a VHDL description of a 2-bit comparator with an equal-to comparison.
5. Design a 3-to-8 line decoder with VHDL using ‘case’ statements.
6. What are the synthesis and simulation tools available for VHDL? Explain the
process.
7. What is meant by ‘optimizing VHDL code for synthesis’?
8. Discuss the importance of testbenches in VHDL. Provide an example of a
simple testbench for a 4-bit adder.
9. How do you handle timing constraints and delays in VHDL designs?
10. Write a VHDL code to implement a 4-bit shift register with parallel load.

Level 1: Remembering (Recall of Facts)

1. What is the purpose of the entity in VHDL?

2. Name at least five data types available in VHDL.
3. What are the differences between a signal and a variable in VHDL?
4. List the operators used for logical operations in VHDL.
5. Define a ‘process’ in VHDL and give a simple example.

Level 2: Understanding (Comprehending Meaning)

1. Explain the role of the architecture in VHDL and how it relates to the entity.
2. Describe the difference between combinational and sequential logic in terms
of VHDL modeling.
3. What is the significance of the wait statement within a VHDL process?
4. How does the if-then-else statement work in VHDL for designing
combinational circuits?
5. Why are testbenches important in VHDL simulation, and what are their basic
components?

Level 3: Applying (Using Knowledge in New Situations)

1. Write a VHDL code for a 4-input XOR gate and explain the process of coding
it.
2. Design a 3-to-8 line decoder using VHDL. Describe the steps and logic behind
your design.
3. How would you implement a 4-bit binary subtractor in VHDL? Provide the
code and explain how it works.
4. Given a 2-bit magnitude comparator, write the VHDL code for it, and show
how it can be simulated.
5. Implement a 4-bit adder using the ‘structural modeling’ method in VHDL and
explain the interconnections between the components.

Level 4: Analyzing (Breaking Information into Parts)

1. Analyze the differences in simulation results between signal assignment and

variable assignment in a VHDL process. Provide an example for each.
 2. Given a 4-bit input binary value, identify the process to convert it to BCD
using VHDL. Discuss the key operations required in this process.
3. Compare the two VHDL coding styles: behavioral vs. structural modeling.
Which one is more efficient for designing a multiplexer and why?
4. Analyze the behavior of a 4-bit ripple-carry adder and discuss the propagation
delay associated with each stage.
5. You are designing a priority encoder. Break down the steps involved in the
VHDL description, and explain how each input affects the output.

Level 5: Evaluating (Making Judgments Based on Criteria)

1. Evaluate the performance trade-offs between using behavioral modeling and

structural modeling in VHDL for designing a complex digital circuit.
2. Given a design of a 2-bit ALU, assess the efficiency of the code. What
optimizations would you suggest for reducing logic gates and improving
performance?
3. After simulating a VHDL design for a 4-bit full-adder, you notice some
incorrect outputs. How would you evaluate the root cause of this issue and
rectify it in the code?
4. In a scenario where the simulation results are correct, but the synthesized
hardware shows incorrect behavior, evaluate the possible causes of
discrepancies.
5. Considering a design for a 16-bit shift register, evaluate the possible delays
and timing issues involved in using different VHDL synthesis tools. How
would you mitigate these issues?

Level 6: Creating (Putting Information Together in New Ways)

1. Create a VHDL code for a 4-bit ALU that performs addition, subtraction,
AND, and OR operations. The ALU should be able to select the operation
based on a 2-bit control signal.
2. Design a VHDL-based 3-stage pipeline for a digital signal processing (DSP)
circuit. Explain how you would implement each stage using structural
modeling.
3. Propose a novel VHDL solution to design a 4-bit encoder with priority logic.
Create the code and justify your design decisions.
4. Write VHDL code for a system that generates an 8-bit pseudo-random
sequence using a linear-feedback shift register (LFSR). Explain the design
principles and key features of your solution.
5. Create a VHDL testbench for verifying the correctness of a 4-to-1 multiplexer.
The testbench should include various test cases with expected results and
handle different edge cases.

Challenging Combinational Circuit Design Questions

 Write a VHDL implementation of a 16-bit Carry-Lookahead Adder (CLA).

Discuss how it improves over the Ripple Carry Adder.
 Design a VHDL-based comparator that compares two 8-bit inputs and outputs
a "greater than," "less than," or "equal" result. Justify the use of various VHDL
constructs in your design.
  Design and implement a 4-bit BCD adder using VHDL. Compare this design
with a standard binary adder in terms of complexity and timing.
 Create a 2-bit Johnson counter in VHDL. Write the code, and explain how you
would simulate and test it.
 Design a VHDL module that implements a 4-input majority function and
explain how it can be used in error correction codes.

1. Adder

Question 1:
Write a VHDL code to implement a 1-bit half adder. The adder should take two
inputs A and B and provide two outputs: the sum and the carry.

Question 2:
Write a VHDL code for a 4-bit full adder. The full adder should handle carry-in and
produce both sum and carry-out. Implement the adder using a structural description.

2. Subtractor

Question 3:
Write a VHDL code to design a 4-bit binary subtractor using half adders and full
adders. Your design should also include the borrow output.

Question 4:
Implement a 4-bit BCD subtractor in VHDL. Handle cases where the result is
negative by performing two’s complement on the negative result.

3. Decoder

Question 5:
Write VHDL code for a 2-to-4 line decoder. The decoder should have 2 input lines
and 4 output lines, where each output corresponds to one of the possible input
combinations.

Question 6:
Design a 3-to-8 line decoder using VHDL. The decoder should activate one of the
eight outputs based on the 3-bit input.

4. Encoder

Question 7:
Write VHDL code to implement a 4-to-2 priority encoder. The encoder should have
4 inputs and 2 outputs, and it should include a valid output to indicate when any input
is active.

Question 8:
Implement a 8-to-3 encoder in VHDL. The encoder should output a 3-bit value
corresponding to the active input. Also, provide a validity signal (valid) to indicate
whether any input is active.
5. Tri-state Buffer

Question 9:
Write a VHDL code to design a tri-state buffer. The buffer should take an input
signal and a control signal. If the control signal is high, the buffer should pass the
input signal to the output; otherwise, the output should be in a high-impedance state.

Question 10:
Design a 3-state buffer in VHDL, where the output is connected to an external bus.
The output should be in high impedance when the control signal is low, and it should
output the input value when the control signal is high.

6. Multiplexer (Mux)

Question 11:
Write VHDL code to implement a 2-to-1 multiplexer (MUX). The multiplexer
should take 2 data inputs (A, B), 1 control signal (S), and output the selected input
based on S.

Question 12:
Design a 4-to-1 multiplexer (MUX) using VHDL. The multiplexer should take 4
data inputs (I0, I1, I2, I3), 2 control signals (S1, S0), and output the selected input
based on the values of S1 and S0.

7. Demultiplexer (Demux)

Question 13:
Write VHDL code to implement a 1-to-4 demultiplexer (DEMUX). The demux
should take 1 input data line and 2 control signals, and route the data to one of the 4
output lines based on the control signals.

Question 14:
Implement a 2-to-4 demux in VHDL. The demux should take 1 input and use 2
control signals to distribute the input to one of 4 output lines.

8. Parity Generator

Question 15:
Design a parity generator in VHDL that generates even parity for an 8-bit input.
The output should be a parity bit that ensures the total number of 1’s in the 8-bit data
plus the parity bit is even.

Question 16:
Write VHDL code for a parity generator that generates odd parity for a 4-bit input.
The output should be a single parity bit such that the total number of 1’s is odd.

9. Parity Checker
Question 17:
Write a VHDL description for a parity checker that checks if the 8-bit input has even
parity. The output should be 1 if the parity is correct, and 0 if it is incorrect.

Question 18:
Implement a parity checker in VHDL for an 8-bit input that checks whether the
input has odd parity. The output should indicate whether the parity is valid or not (1
for valid, 0 for invalid).

10. Comparator

Question 19:
Write VHDL code for a 2-bit magnitude comparator. The comparator should
compare two 2-bit values and output 1 if the first value is greater than the second, 0 if
they are equal, and -1 if the first value is smaller.

Question 20:
Design a 4-bit equality comparator in VHDL. The comparator should output 1 if
two 4-bit inputs are equal and 0 if they are not.

Bonus Question (Challenging)

Question 21:
Design a 2-bit ALU (Arithmetic Logic Unit) using VHDL. The ALU should perform
the following operations based on a 2-bit control signal:

 00: AND
 01: OR
 10: ADD
 11: SUBTRACT
Include both the output and a zero flag that is set if the result is zero.

1. Behavioral Modeling

Behavioral modeling in VHDL describes the functionality of a circuit without

specifying its structure.

Question 1:

Write a behavioral VHDL description for a 4-bit AND gate. The gate should take
two 4-bit inputs and return a 4-bit output. Explain how the if statement or the when
clause is used to describe the function in this model.

Question 2:

Design a 4-bit binary adder using behavioral modeling in VHDL. Use the +
operator to add two 4-bit inputs and generate a 4-bit sum output with a carry bit.
Explain how the carry is handled in this approach.

Question 3:
Write a behavioral description in VHDL for a 2-to-1 multiplexer (MUX). Use the
when-else statement to select the output based on the control input. Discuss how this
differs from a structural description.

Question 4:

Implement a 4-bit subtractor using behavioral modeling in VHDL. The subtractor

should subtract one 4-bit input from another and provide both the result and the
borrow output.

Question 5:

Design a 4-bit binary multiplier using behavioral modeling in VHDL. The

multiplier should take two 4-bit inputs and return an 8-bit output. Explain the logic
behind your design.

2. Structural Modeling

Structural modeling defines the interconnections between lower-level components or

modules.

Question 6:

Write a structural VHDL description for a 1-bit full adder using half adders.
Connect the half adders appropriately and explain the interconnection of signals.

Question 7:

Design a 4-bit magnitude comparator using structural modeling in VHDL.

Decompose the design into smaller components like bitwise comparators and
explain how the structural elements are connected.

Question 8:

Implement a 4-to-1 multiplexer (MUX) using structural VHDL modeling. First,

design a 2-to-1 multiplexer and use it to build the 4-to-1 multiplexer by cascading
smaller components. Provide the interconnections between them.

Question 9:

Write a structural description for a 4-bit ripple-carry adder. Decompose the adder
into full adder modules and connect them sequentially to create the 4-bit adder.
Explain the interconnections and signal flow between the modules.

Question 10:

Design a 3-to-8 decoder using structural VHDL. Break the decoder design into
smaller components (such as AND gates and inverters) and describe how they are
connected to create the final output.
3. Dataflow Modeling

Dataflow modeling specifies how data moves through a system and is typically used
for combinational logic designs, focusing on the flow of signals.

Question 11:

Write a dataflow VHDL description for a 2-input AND gate. Use the and operator
in a concurrent assignment statement and explain how the data is passed through the
gate in the model.

Question 12:

Design a 4-bit OR gate using dataflow modeling in VHDL. Use the or operator for
the dataflow description. Explain how the output is derived from the inputs.

Question 13:

Implement a 4-to-1 multiplexer (MUX) using dataflow modeling. Use the with-
select statement to select the appropriate input based on the control lines. Explain how
the selection process works in dataflow modeling.

Question 14:

Write a dataflow VHDL description for a 4-bit binary adder. Use the + operator to
add the two 4-bit inputs and describe how the data flows to generate the sum and
carry outputs.

Question 15:

Design a 2-bit comparator using dataflow modeling in VHDL. Use the = operator
for equality checking and explain how the data flow controls the output based on the
comparison.

4. Mixed-Modeling Approach

Some designs may involve a combination of different modeling styles to optimize

design or enhance readability.

Question 16:

Create a 4-bit counter using a combination of behavioral and structural VHDL

modeling. Use the behavioral approach to describe the counting behavior and the
structural approach to connect the flip-flops.

Question 17:

Design a 4-bit shift register using a mixed-modeling approach. Use dataflow

modeling for the shifting operation and structural modeling to interconnect the
individual flip-flops.
Question 18:

Write a mixed-modeling description for a 2-bit ALU that can perform AND, OR,
and ADD operations. Use behavioral modeling for the arithmetic and logical
operations, and structural modeling for connecting the individual components.

Question 19:

Design a priority encoder using a combined approach of dataflow and behavioral

modeling. Use dataflow modeling to express the logic for encoding, and behavioral
modeling to handle the prioritization of inputs.

Question 20:

Write VHDL code for a 4-bit binary multiplier using dataflow modeling to describe
the individual bitwise AND operations and a structural approach to combine the
partial products.

Question 21:

Compare and contrast behavioral, structural, and dataflow modeling in VHDL.

Discuss the advantages and disadvantages of each approach when designing complex
combinational circuits such as a 4-bit ALU or a 5-to-32 decoder.

Question 22:

For a combinational circuit design, which VHDL modeling style would you use and
why? Discuss the trade-offs when choosing between behavioral modeling, dataflow
modeling, and structural modeling for a design like a 5-bit counter.