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DFT Basics FAQs

The document outlines the fundamentals of Design for Testability (DFT), including its necessity, testing levels, and definitions of key concepts such as testability, yield, and various testing strategies. It discusses the differences between RTL and gate-level netlists, as well as the importance of observability and controllability in DFT. Additionally, it covers various testing methodologies, challenges in DFT with technology node changes, and the significance of testing chips.

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Ambarish Ramesh
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14 views1 page

DFT Basics FAQs

The document outlines the fundamentals of Design for Testability (DFT), including its necessity, testing levels, and definitions of key concepts such as testability, yield, and various testing strategies. It discusses the differences between RTL and gate-level netlists, as well as the importance of observability and controllability in DFT. Additionally, it covers various testing methodologies, challenges in DFT with technology node changes, and the significance of testing chips.

Uploaded by

Ambarish Ramesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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DFT Basics

1. What is the need of DFT? Why DFT?


2. What are the levels of testing ic’s ?
3. Define Testing and Testability.
4. Explain about ASIC flow.
5. Explain DFT flow.
6. Difference between RTL and Gate level netlist.
7. What is the difference between DFT and Verification?
8. What is Fuctional testing and Structural testing.
9. What is observability and controllability? (or) two pillers of DFT.
10.What is yield?
11.How do you design a logic which is DFT friendly?
12.Define defect, fault, error. Explain with an example.
13.What is Adhoc testing?
14.What is metastability, skew, latency? Explain with schematics.
15.What is clock jitter?
16.What is pad, pin, port?
17.Define false path, critical path, multicycle path?
18.What is slack?
19.What is glitch?
20.What is clock gating and what is the necessity of it? Explain ICG with
waveform?
21.What is a linked library and targeted library?
22.What is a top-down and bottom-up approach?
23.Does DFT Vectors test the functionality of the design also?
24.What are Graybox and Blackbox.
25.What are the different DFT strategies?
26.What all things in DFT want to take care when technology node
changes?
27.Which format of pattern is used for ATE?
28.Why do we need to test our chips?
29.Why is Tester frequency slower than Functional Frequency?
30.What is meant by test plan?

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