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Lecture 1

The document outlines the course structure for a Computer Architecture class, detailing the topics to be covered in each lecture and the rules for participation. It includes information on lab work, project evaluation criteria, and the marking system for assessments. Additionally, it emphasizes the importance of interaction during lectures and provides a reading list for students.

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4 views

Lecture 1

The document outlines the course structure for a Computer Architecture class, detailing the topics to be covered in each lecture and the rules for participation. It includes information on lab work, project evaluation criteria, and the marking system for assessments. Additionally, it emphasizes the importance of interaction during lectures and provides a reading list for students.

Uploaded by

dowymoragy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computer Architecture

Lecture 1: Course Overview


Dr. Ahmed Soltan
[email protected]

Please turn your


mobiles to silent
Lecture Course Overview
Lecture 1: Course Overview and exemplars
Lecture 2: Performance evaluation
Lecture 3: Control and data path hardware for a processor
Lecture 4: Pipelining
Lecture 5: Fast memory and storage systems.
Lecture 6: HDL 1
Lecture 7: HDL 2
Lecture 8: Digital building blocks
Lecture 9: Digital building blocks 2
Lecture 10: Memory array
Lecture 11: Assembly language
Ground Rules

• I am here to teach - you are here to learn


• I will do my best, I ask you to do the same!
• We all come in on time!
• Please consider the lectures interactive. If you don’t
understand something – ask.
• Please turn your phone to silent!
• Concentrate on lectures rather than texting, twitter,
gaming apps, mobile Facebook etc.
• I don’t carry spare lecture notes
Teaching format Format
Lectures:
11x lectures, 2 hours each with a break in the middle
Lectures should be interactive, so please ask questions throughout! Also, as this is the first
year of the course, please highlight any typos you may find in the notes
Tutorials:
Tutorials have been allocated to cover the primary aspects of the course. These will be in
exam format and answers will only be provided to those who attend!
Lab:
Labs will be Verilog based using Vivado tool.
Problem based learning (PBL):
There will be a project during the semester and each group should be 4 students.

4
Lab work
In the lab
You will use Vivado as a simulation tool for
Verilog/Verilog-A

In the lab
You will ZYBO board for testing and evaluation
of your code

5
Project evaluation
• Project evaluation will be based on:

• Presentation of the project (5%)

• Project report (5%)

• Project work (10%)

6
Marking
• Exam 2 hours (40%)

• Midterm exam 1 hour (20%)


• Project assessment (20%)
• Four quizzes ( 15% total)
• 30st /10/2024
• 27th /11/2024
• 18th /12/2024
• 8th /12/2024
• 5% attendance/assignment

7
Project evaluation
• Project evaluation will be based on:

• Presentation of the project (5%)

• Project report (5%)

• Project work (10%)

• Project idea has to be agreed by 30th of October 2024


• Report submission has to be on 18th December 2024
• Final discussion will be 25th of December 2024

8
Reading
Digital design and computer architecture
David Money Harris & Sarah L. Harris
ISBN: 978-0-12-394424-5

Chapters 4 & 5 & 6

9
Today’s Lecture Overview

1. What is Architecture ?
2. Technologies
3. History
4. Core Concepts

10
What is Architecture ?

11
Computer architecture is a set of rules and methods that describe the
functionality, organization, and implementation of computer systems.
Some definitions of architecture define it as describing the capabilities
and programming model of a computer but not a particular
implementation. In other definitions computer architecture
involves instruction set
architecture design, microarchitecture design, logic design,
and implementation

Write down a list of different devices/systems that


would processors/microcontrolers

12
Moore’s law

13
Die size growth

14
Finer Lithography

15
Fabrication facility costs

16
Performance growth

17
Microarchitecture

18
Pipeline

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Pipeline

20
Multilevel Memories

21
Multicores architectures

22
Multicores architectures

23
Interconnects

24
Introduction-HDL
• A block of hardware with inputs and outputs is called a
module

• The two general styles for describing module functionality are


behavioral and structural.
• Behavioral models describe what a module does.
• Structural models describe how a module is built from
simpler pieces
Simulation and Synthesis
• The two major purposes of HDLs are logic simulation and synthesis.
• During simulation, inputs are applied to a module, and the outputs are
checked to verify that the module operates correctly.

• Correcting errors after the system is built can be devastatingly expensive

• Bug in the Pentium processor forced the company to recall chips after
they had shipped, at a total cost of $475 million
Synthesis
• Logic synthesis transforms HDL code into a netlist describing the hardware
• The logic synthesizer might perform optimizations to reduce the amount of
hardware required.
• The netlist may be a text file, or it may be drawn as a schematic to help
visualize the circuit
• SystemVerilog and VHDL are rich languages with many commands. Not all
of these commands can be synthesized into hardware.

• Code is intended to represent hardware.


• you might write code that simulates correctly but cannot be implemented
in hardware
Combinational logic
• Bitwise Operators: Bitwise operators act on single-bit signals or on
multi-bit busses.
Combinational logic
Comments and White Space
Conditional Assignment
• Conditional assignments select the output from among alternatives based
on an input called the condition.
Conditional Assignment
Internal Variables
• HDL assignment statements (assign in SystemVerilog and <= in VHDL take
place concurrently.
Z’s and X’s
• HDLs use z to indicate a floating value, z is particularly useful for
describing a tristate buffer, whose output floats when the enable is 0

• Similarly, HDLs use x to indicate an invalid logic level. If a bus is


simultaneously driven to 0 and 1 by two enabled tristate buffers, the
result is x, indicating contention.
Delays

• Delays are helpful during simulation to predict how fast a circuit


will work and also for debugging purposes to understand cause
and effect

• These delays are ignored during synthesis; the delay of a gate


produced by the synthesizer
Structural modeling
Structural modeling
Structural modeling

• In general, complex systems are designed hierarchically.


• The overall system is described structurally by instantiating its major
components.
• Each of these components is described structurally from its building blocks,
and so forth recursively until the pieces are simple enough to describe
behaviorally.
• It is good style to avoid mixing structural and behavioral descriptions within
a single module
Lecture summary and learning objectives

What you need to know.


1. What computer architectures are.
2. Describe the different parts of module.
3. Your marking system.

39

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