What is RISC and CISC Architecture & Their

Differences

The architecture of the Central Processing Unit (CPU) operates the

capacity to function from “Instruction Set Architecture” to where it was
designed. The architectural design of the CPU is Reduced instruction set
computing (RISC) and Complex instruction set computing (CISC). CISC
has the capacity to perform multi-step operations or addressing modes
within one instruction set. It is the CPU design where one instruction works
several low-level acts. For instance, memory storage, loading from
memory, and an arithmetic operation.

Reduced instruction set computing is a Central Processing Unit design

strategy based on the vision that a basic instruction set gives great
performance when combined with a microprocessor architecture. This
architecture has the capacity to perform the instructions by using some
microprocessor cycles per instruction. This pdf discusses the RISC and
CISC architecture with appropriate diagrams. The hardware part of the
Intel is named as Complex Instruction Set Computer (CISC), and Apple
hardware is Reduced Instruction Set Computer (RISC).

What is RISC and CISC Architectures?

A complex instruction set computer is a computer where single instructions
can perform numerous low-level operations like a load from memory, an
arithmetic operation, and a memory store or are accomplished by multi-
step processes or addressing modes in single instructions, as its name
proposes “Complex Instruction Set ”.

A reduced instruction set computer is a computer that only uses simple

commands that can be divided into several instructions which achieve low-
level operation within a single CLK cycle, as its name proposes “Reduced
Instruction Set ”

RISC Architecture

The term RISC stands for ‘’Reduced Instruction Set Computer’’. It is a

CPU design plan based on simple orders and acts fast.

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This is a small or reduced set of instructions. Here, every instruction is
expected to attain very small jobs. In this machine, the instruction sets are
modest and simple, which help in comprising more complex commands.
Each instruction is about a similar length; these are wound together to get
compound tasks done in a single operation. Most commands are
completed in one machine cycle. This pipelining is a crucial technique
used to speed up RISC machines.

Reduced Instruction Set Computer is a

microprocessor that is designed to carry out
few instructions at a similar time. Based on
small commands, these chips need fewer
transistors, which makes the transistors
inexpensive to design and produce. The
features of RISC include the following.

The demand for decoding is less

Few data types in hardware RISC Architecture
General-purpose register Identical
Uniform instruction set
Simple addressing nodes

Also, while writing a program, RISC makes it easier by letting the computer
programmer eliminate needless codes and stops wasting cycles.

Characteristics

The characteristics of RISC architecture include the following.

Simple Instructions are used in RISC architecture.

RISC helps and supports few simple data types and synthesizes
complex data types.
RISC utilizes simple addressing modes and fixed-length instructions
for pipelining.
RISC permits any register to use in any context.
One Cycle Execution Time
The amount of work that a computer can perform is reduced by
separating “LOAD” and “STORE” instructions.
RISC contains a Large Number of Registers to prevent various
interactions with memory.

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 In RISC, Pipelining is easy as the execution of all instructions will be
done in a uniform interval of time i.e. one click.
In RISC, more RAM is required to store assembly-level instructions.
Reduced instructions need a less number of transistors in RISC.
RISC uses the Harvard memory model means it is Harvard
Architecture.
A compiler is used to perform the conversion operation means
converting a high-level language statement into the code of its form.

CISC Architecture

The term CISC stands for ‘’Complex Instruction Set Computer’’. It is a

CPU design plan based on single commands, which are skilled in
executing multi-step operations.

CISC computers have small programs. It has a huge number of compound

instructions, which take a long time to perform. Here, a single set of
instructions is protected in several steps; each instruction set has an
additional than 300 separate instructions. Maximum instructions are
finished in two to ten machine cycles. In CISC, instruction pipelining is not
easily implemented.

The CISC machines have good acts, based

on the overview of program compilers; as the
range of innovative instructions are simply
obtainable in one instruction set. They
design compound instructions in a single,
simple set of instructions.

They achieve low-level processes, which

makes it easier to have huge addressing
nodes and additional data types in the
hardware of a machine. But, CISC is CISC Architecture
considered less efficient than RISC, because
of its incompetence to eliminate codes which leads to wasting of cycles.
Also, microprocessor chips are difficult to understand and program for,
because of the complexity of the hardware.

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 Instruction Set Architecture is a medium to permit communication
between the programmer and the hardware. Data execution part,
copying of data, deleting, or editing is the user commands used in the
microprocessor, and with this microprocessor, the Instruction set
architecture is operated.
The main keywords used in the above Instruction Set Architecture are
as below

Instruction Set: Group of instructions given to execute the program and

they direct the computer by manipulating the data. Instructions are in the
form – Opcode (operational code) and Operand. Where, the opcode is the
instruction applied to load and store data, etc. The operand is a memory
register where instruction is applied.

Addressing Modes: Addressing modes are how the data is accessed.

Depending upon the type of instruction applied, addressing modes are of
various types such as a direct mode where straight data is accessed or
indirect mode where the location of the data is accessed. Processors
having identical ISA may be very different in the organization. Processors
with identical ISA and nearly identical organization is still not nearly
identical.

CPU performance is given by the fundamental law

Thus, CPU performance is dependent upon Instruction Count, CPI (Cycles

per instruction), and Clock cycle time. And all three are affected by the
instruction set architecture.

Instruction Count of the CPU

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This underlines the importance of the instruction set architecture. There
are two prevalent instruction set architectures

Examples of CISC Processors

IBM 370/168 – It was introduced in the year 1970. CISC design is a 32-bit
processor and four 64-bit floating point registers.
VAX 11/780 – CISC design is a 32-bit processor and it supports many
numbers of addressing modes and machine instructions which is from
Digital Equipment Corporation.
Intel 80486 – It was launched in the year 1989 and it is a CISC processor,
which has instructions varying lengths from 1 to 11 and it will have 235
instructions.

Characteristics

The characteristics of CISC architecture include the following.

Instruction-decoding logic will be Complex.

One instruction is required to support multiple addressing modes.
Less chip space is enough for general purpose registers for the
instructions that are 0operated directly on memory.
Various CISC designs are set up with two special registers for the
stack pointer, handling interrupts, etc.
MUL is referred to as a “complex instruction

Comparison Between RISC and CISC

RISC stands for ‘Reduced Instruction Set Computer Whereas, CISC

stands for Complex Instruction Set Computer. The RISC processors have
a smaller set of instructions with few addressing nodes. The CISC
processors have a larger set of instructions with many addressing nodes.

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 RISC vs CISC

Memory Unit

RISC has no memory unit and uses separate hardware to implement

instructions. CISC has a memory unit to implement complex instructions

Program

RISC has a hard-wired unit of programming. CISC has a

microprogramming unit

Design

RISC is a complex compiler design. CISC is an easy compiler design

Calculations

RISC calculations are faster and more precise. CISC calculations are slow
and precise

Decoding

RISC decoding of instructions is simple. CISC decoding of instructions is

complex

Time

Execution time is very less in RISC. Execution time is very high in CISC.

External memory

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RISC does not require external memory for calculations. CISC requires
external memory for calculations.

Pipelining

RISC Pipelining does function correctly. CISC Pipelining does not function
correctly.

Stalling

RISC stalling is mostly reduced in processors. CISC processors often stall.

Code Expansion

Code expansion can be a problem in RISC whereas, in CISC, Code

expansion is not a problem.

Disc space

Space is saved in RISC whereas in CISC space is wasted. The best

examples of CISC instruction set architecture include VAX, PDP-11,
Motorola 68k, And your desktop PCs on Intel’s x86 architecture, whereas
the best examples of RISC architecture include DEC Alpha, ARC, AMD
29k, Atmel AVR, Intel i860, Blackfin, i960, Motorola 88000, MIPS, PA-
RISC, Power, SPARC, SuperH, and ARM too.

SEMANTIC GAP

Both RISC and CISC architectures have been developed as an attempt to

cover the semantic gap.

Semantic Gap

To improve the efficiency of software development, several powerful

programming languages have come up, viz., Ada, C, C++, Java, etc. They
provide a high level of abstraction, conciseness, and power. By this

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evolution, the semantic gap grows. To enable efficient compilation of high-
level language programs, CISC and RISC designs are the two options.

CISC designs involve very complex architectures, including a large

number of instructions and addressing modes, whereas RISC designs
involve a simplified instruction set and adapt it to the real requirements of
user programs.

CISC and RISC Design

Multiplication of two Numbers in Memory

If the main memory is divided into areas that are numbered from
row1:column 1 to row 5: column 4. The data is loaded into one of four
registers (A, B, C, or D). To find multiplication of two numbers- One stored
in location 1:3 and other stored in location 4:2 and store back result in 1:3.

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 Multiplication of Two Numbers

Applications of RISC and CISC

RISC is used in high-end applications like video processing,

telecommunications, and image processing. CISC is used in low-end
applications such as security systems, home automation, etc.

Advantages and Disadvantages

The advantages of RISC architecture include the following.

RISC(Reduced instruction set computing)architecture has a set of

instructions, so high-level language compilers can produce more
efficient code
It allows freedom of using the space on microprocessors because of
its simplicity.
Many RISC processors use the registers for passing arguments and
holding the local variables.
RISC functions use only a few parameters, and the RISC processors
cannot use the call instructions, and therefore, use a fixed-length
instruction that is easy to pipeline.
The speed of the operation can be maximized and the execution time
can be minimized.
A very less number of instructional formats, a few numbers of
instructions, and a few addressing modes are needed.

The disadvantages of RISC architecture include the following.

Mostly, the performance of the RISC processors depends on the

programmer or compiler as the knowledge of the compiler plays a
vital role while changing the CISC code to a RISC code
While rearranging the CISC code to a RISC code, termed as a code
expansion, will increase the size. And, the quality of this code
expansion will again depend on the compiler, and also on the
machine’s instruction set.
The first level cache of the RISC processors is also a disadvantage of
the RISC, in which these processors have large memory caches on
the chip itself. For feeding the instructions, they require very fast
memory systems.

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The advantages of CISC architecture include the following.

Microprogramming is an easy assembly language to implement, and

less expensive than hard-wiring a control unit.
The ease of microcoding new instructions allowed designers to make
CISC machines upwardly compatible:
As each instruction became more accomplished, fewer instructions
could be used to implement a given task.

The disadvantages of CISC architecture include the following.

The performance of the machine slows down due to the amount of

clock time taken by different instructions will be dissimilar
Only 20% of the existing instructions are used in a typical
programming event, even though there are various specialized
instructions in reality that are not even used frequently.
The conditional codes are set by the CISC instructions as a side
effect of each instruction which takes time for this setting – and, as
the subsequent instruction changes the condition code bits – so, the
compiler has to examine the condition code bits before this happens.

From the above comparison of RISC and CISC, finally, we can conclude
that we cannot distinguish between RISC and CISC technology because
both are apt at their precise application. Today, both RISC and CISC
designers are doing all to get an edge on the competition.

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RISC Vs CISC Architecture : In-Depth Comparative
Analysis

In computer architecture, two significant instruction set designs have dominated

microprocessor engineering: RISC (Reduced Instruction Set Computing) and CISC
(Complex Instruction Set Computing). These architectures elaborate on the design
and implementation of a processor’s instruction set, which impacts efficiency,
performance, and overall system configuration.

CISC architecture has prevailed for decades, especially in personal computer

systems and servers. However, in recent years, there has been a shift from RISC
architecture to CISC architecture because they use more complex sets of
instructions capable of executing multiple operations with a single instruction. In
this we explore the comparison between RISC vs CISC architectures. Also, navigate
how RISC architecture differs from the CISC processors, along with the advantages
of migrating from RISC to CISC processors.

Before diving deep, here is a summary of RISC vs CISC processor.

Basis for
Comparison RISC Architecture CISC Architecture

Emphasis Software Hardware

Instruction Size Small Large

Registers More Registers Used Less Registers Required

Pipelining Easy Difficult

Addressing Mode Limited addressing mode More addressing mode required

required

Understanding the Fundamentals of Computer Architecture

Nearly all the latest CPUs have different architecture designs to work from
“Instruction Set Architecture.” Primarily, there are two types of architectural designs:

RISC (Reduced Instruction Set Computing) Processors

 CISC (Complex Instruction Set Computing) Processors

These two designs differ in multiple ways. RISC architecture mainly focuses on
executing commands while aiding some microprocessor cycles per command for
optimum performance, while CISC architecture can perform multiple operations
with a single set of instructions.

Also, it has diverse ways of addressing modes to access memory, which depends on
the CPU framework, which requires a single set of instructions to carry out many
low-level actions.

Understanding RISC Architecture

Reduced Instruction Set Computing, or RISC, is the CPU architecture designed to

follow simple instructions. In simple terms, every command will perform small and
simple tasks at a fast speed. Here, most instructions are of similar length as they
divide all the complex instructions into a simple set of instructions through a
process known as Pipelining.

Simple instructions => One instruction is One CW PM larger

 RISC

larger

What is Pipelining in RISC Microprocessor?

Pipelining is a multi-stage procedure that carries out single instructions in one

machine cycle to increase the speed of RISC microprocessors. RISC uses a small set
of instructions, so the number of chips used for transistors is small.

In RISC architecture, minimum decoding is required as the data types available in

the hardware are fewer. The register needed for general purposes is common to all,
while the addressing nodes are simple, and the

instruction set is uniform. As a result, when a task is executed, RISC preserves the
number of cycles it is carried out by eliminating the code’s unnecessary parts.

What are the Characteristics of RISC Architecture?

Here are some characteristics of RISC architecture:

Simple set of commands that can be easily decoded and implemented.

The size of the instruction set is very small, sometimes as small as a
single word.
It is a fast procedure as a single instruction is executed with just a single
instruction.
The general-purpose register quantity is larger.
The variable data type is less in number.
The addressing modes are quite simple.
Achieving pipeline is the primary goal.

What are the Advantages of RISC Microprocessors?

Here are some of the advantages of using RISC microprocessors in the CPU design:

Usage of Simple Instruction Sets: The simple set of instructions is used in

RISC processors, which makes it easy to decode and execute, resulting in
 faster processing.
Reduced Power Consumption: The RISC microprocessors consume less
power, making them ideal for portable devices.
Faster Output: The RISC microprocessor produces quicker results due to
more uncomplicated instructions.

What are the Disadvantages of RISC Processors?

Here are some of the disadvantages of RISC processors:

Increased Instructions-Sets Requirements: Many sets are required for

instructions to perform complex tasks.
Memory Usage: To store additional instructions for executing complex
tasks, ample memory storage is needed.

Expensive: The RISC processors are costly to design and manufacture.

Understanding CISC Architecture

Complex Instruction Set Computing, or CISC architecture, is used to execute

complex tasks with just a single command. It contains instructions for multiple steps
required in an operation for execution in a program.
Therefore, CISC processors have comparatively smaller programs, while the size of
their instruction set is large and requires quite some time to produce output.
In CISC architecture, various measures are taken to secure every instruction set,
which means an extra set of commands for each instruction, which prolongs the
output result. Depending on the instruction size, the instruction may take two or
more machine cycles. Moreover, it doesn’t use the pipelining process as RISC
architectures.

Key Features of CISC Architecture

Here are some noteworthy features of CISC architecture in CPU frameworks:

CISC processor can quickly execute compound command output with a single
complex set of instructions
It can be used for compilers.
It has a wide range of addressing nodes.
CISC uses multiple data types for its machine hardware and can carry out
 processes for a low-level command.
It is complex in nature.

What are the Characteristics of CISC Architecture?

Here are some characteristics of CISC architecture:

It has a complex set of instructions; therefore, it is also known as decoding.

The size of the instruction set is significant due to its complexity, which is
often more than one word.
The time taken to execute compound instruction is more than a single clock
cycle.
The number of general-purpose registers used is smaller as most operations
are carried out in memory.
Multiple data types are used in CISC microprocessors.
The addressing mode framework is generally complex.

What are the Advantages of CISC Microprocessors?

Here are some of the advantages of using CISC microprocessors in the CPU design:

Popularity: CISC microprocessors are widely used in software and have a

more extensive user base.

Code Size: It is a reduced code size as it uses complex instructions to

execute multiple operations for a program.
Memory-Effective Code: The instruction set of CISC architecture is more
complex, requiring fewer commands for a program, making it more memory-
efficient code.

What are the Disadvantages of CISC Processors?

Here are some of the disadvantages of CISC processors:

Slow Execution Process: Due to the complexity of CISC architectures’

instruction sets, it takes longer to decode and execute the commands.
Higher Power Consumption: Due to the complexity of their instruction
 sets, CISC processors require more power than other CPU frameworks like RISC
architectures.
Design Complexity: The design and manufacturing of CISC processors are
complex, making production difficult.

RISC vs CISC Processor: Analyzing & Assessing the CPU

Performance

Here is a brief analysis how the RISC vs CISC processor approaches enhance CPU
performance.

In RISC architecture, the number of clock cycles for each instruction is reduced
at the cost of the total instruction per program.
In contrast, in CISC architecture, the number of instructions sets used per
program is reduced, but this increases the overall number of cycles per
instruction.

RISC microprocessor is more popular for high-level language dependency as it uses

simpler and faster instructions. However, when a task or programming is
performed in assembly language, instructions are needed to carry out many tasks,
as executing a program in assembly can be very tedious and prone to error. Due to
this, the CISC architecture framework was developed to aid assembly programs.

For Example:

A task for the addition of two 8-bit numbers

1. RISC Architecture Approach:

The programmer must create a load command to load the information in

 registers.
For the next step, a suitable operator is required
Finally, the output will be stored in the designated location.

Here, in the task of performing addition, the program is divided into three parts,
i.e., load, operate, and store, which makes RISC programs long and requires more
memory to store instructions while needing fewer transistors as the commands are
simple and less complex.

2. CISC Architecture Approach:

The task will be carried out with a single instruction or a command, ADD.

RISC vs CISC Architecture: A Comparative Analysis

Here is an in-depth comparison of RISC vs CISC architectures:

RISC Architecture CISC Architecture

RISC architecture is known as Reduced CISC architecture is known as Complex

Instruction Set Computing. Instruction Set Computing.

Emphasizes software. Emphasizes hardware.

Functions only on the Hardwired Control Unit. Functions both on Microprogrammed and
Hardwired Control Unit.

For the usage of more registers, transistors For the storage of complex instructions,
are used. transistors are being used.

Many registers are used. Registers are used in less quantity.

Instructions or commands given are fixed in The size of commands or instructions may vary.
size.

Can easily execute Register to Register Can perform operations like REG to REG, REG
Arithmetic Operations. to MEM, and MEM to MEM.

The size of the code used is large. The size of the code used is small.

Instruction can be executed in a single clock More than one clock cycle is required to
cycle. complete a single instruction.
 The number of instructions given to execute Many instructions are given to perform the
the task are less compared to CISC and is also task, also known as Complex Instruction Cycle.
known as Reduced Instruction Cycle.

The addressing modes are simple and limited. The addressing modes are complex and large.

It consumes less power. It consumes more power as compared to RISC.

Requires heavy usage of RAM storage. Less or efficient usage for RAM storage.

Highly dependent on pipelining procedure. Less dependency on pipelining

procedure.

RISC does not support array. CISC supports array.

In RISC, for return addresses and procedure For return addresses and procedure
arguments, registers are often used. Also, for arguments, stack is used.
certain processes, memory references can be
avoided.
Machine-level operations are more The implementation programs are well
transparent in RISC designs. Also, certain hidden from the machine-level programs in
instruction sequences are restricted some RISC CISC processors. The clean abstraction
processors restrict for efficiency. between program and its execution is
provided by ISA.
RISC architecture uses split instruction cache The unified cache is used by CISC architecture
and data cache. for data and instructions.

Examples of RISC processors are ARM, DEC The examples for CISC processors are:
Alpha, AMD 29K, ARC, Atmel AVR, Personal computers, Motorola 68K, x86,
PA-RISC, SPARC, Intel i860, Blackfin, PDP-11, and VAX.
SuperH, i960, Power, Motorola 88000,
MIPS, and Power.

Aging legacy systems are mostly developed using RISC architecture, which lacks
flexibility, scalability, and the ability to carry out complex instructions.

solutions to migrate from outdated legacy applications to a modern platform like

x86 systems or the cloud.

The x86 servers have a CISC-based architecture, which ensures they can easily
interact with other solutions and perform complex tasks.
Final Thoughts

Which microprocessor is more efficient, CISC vs. RISC architecture? It is debatable

as each approach has its own strengths and weaknesses, while the evolution of
technology is diminishing the lines between them.
Businesses relying heavily on legacy systems are migrating to modern platforms to
meet the ever-growing demands. While RISC architecture has been offering great
assistance with its simple and fast instruction, with the evolving technologies,
complex instruction is required, which makes CISC architecture a better candidate
for performing a task. The future of processor design lies in finding the right
balance between simplicity and complexity, power efficiency and performance, and
cost-effectiveness.

Frequently Answered Questions (FAQs)

1. What are the CISC and RISC architectures called?

RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set
Computing).

2. What are the examples of RISC architecture-based legacy

systems?

Here are some examples of legacy systems that are based on RISC architectures:

DEC Alpha

PA-RISC
SPARC

3. Is the x86 server based on CISC architecture?

Yes, the design of the x86 server is based on CISC architecture.

4. Explain in brief about RISC processors.

RISC processors provide fast execution with simple individual instruction and
effective pipelining.
5. What are the format ranges for RISC and CISC processors?

RISC processors use 32-bit fixed format, which is mostly register-based

instructions, while CISC processors use variable format, ranging from 16 to 64 bits
per instruction.

6. In terms of hardware complexity, how do RISC vs CISC

architectures compare?

When we compare RISC vs CISC architectures, RISC hardware tends to be simpler

due to its reduced instruction set, while CISC hardware is often more complex to
support its wider range of instruction types and addressing modes.

7. In terms of power efficiency, how do RISC vs CISC processors

compare?

RISC processors are often more power-efficient due to their simpler design and
instruction execution, making them popular in mobile and embedded devices.

8. Code size comparison between RISC vs CISC microprocessors?

Due to complex instructions, CISC microprocessors have a smaller code size, while
RISC may require more instructions and thus result in a larger code size for the same
functionality.