Scribd
Upload
11 views5 pages

Computer Organization and Architecture - Weekly Test 01 - Test Paper

The document is a weekly test for Computer Organization and Architecture, covering various topics through multiple-choice questions and numerical answer type questions. It includes questions on microprocessor architecture, instruction formats, and memory organization, with a total of 15 marks available. An answer key and hints for solving the questions are also provided.

Uploaded by

Believer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
11 views5 pages

Computer Organization and Architecture - Weekly Test 01 - Test Paper

The document is a weekly test for Computer Organization and Architecture, covering various topics through multiple-choice questions and numerical answer type questions. It includes questions on microprocessor architecture, instruction formats, and memory organization, with a total of 15 marks available. An answer key and hints for solving the questions are also provided.

Uploaded by

Believer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

1

Branch : CSE & IT Batch : Hinglish


WEEKLY TEST – 01
Subject : Computer Organization and Architecture
Topic : Introduction to COA
Maximum Marks 15

Q.1 to 5 Carry ONE Mark Each

[MCQ] [MCQ]
1. A microprocessor has a data bus with 64 lines and an 4. Consider 32 bits stack CPU supports 1W opcode and
address bus with 32 lines. The maximum number of 4GB RAM.
bits that can be stored in memory is . Following statement is executed in the system:
12 64
(a) 32 ×2 (b) 32 × 2 X = (A*B) (C+D)
32
(c) 64 × 2 (d) 64 × 264 How many machine instructions required for the
given statement.
[MCQ]
(a) 6 (b) 7
2. Various storage device used by an operating system
(c) 8 (d) None
can be arranged as follows in increasing order of
accessing speed. [NAT]
(a) Secondary memory → main memory → cache 5. Consider 32 bits hypothetical CPU which supports 1-
memory → Register
word long instruction with 7 bits opcode, register
(b) Main memory →Secondary memory→cache
operand field value 5 bits and a memory operand field.
memory→Register Then calculate the total memory size in MB.
(c) Secondary memory →cache memory → main
memory →Register
(d) Main memory → secondary memory→ Register
→ cache memory

[MCQ]
3. In the Big-Endian system, the computer stores.
(a) MSB of data in the lowest memory address of data
unit.
(b) LSB of data in the lowest memory address of data
unit.
(c) MSB of data in highest memory address of data
unit.
(d) LSB of data in the highest memory address of data
unit.
2

Q.6 to 10 Carry TWO Mark Each

[NAT] [MCQ]
6. Consider a hypothetical CPU which supports 9. Consider a hypothetical CPU which supports 84
instruction with 2 register operands and 1 memory instructions. Instruction format contain two registers
operands. CPU supports 120 instructions, 24 register operand, one memory operand and 13 bits immediate
and 512 KB memory space. How many bits are constant field. CPU supports 34 registers 256KB
required to encode the instructions. memory space. A process contains 100 instructions.
How much storage space is required in bytes to store
[NAT] the process.
7. Consider 32 bits CPU which supports 1 words (a) 625 bytes (b) 700 bytes
instruction with 3 Register operands and immediate (c) 600 bytes (d) 725 bytes
operands fields. Processer supports 7 bits opcode and
24 Register with register size of 32 bits. Instruction is [NAT]
placed in a 256KW memory. What is the largest 10. Consider 64 bits hypothetical CPU which supports one
unsigned constant possible in the instruction?
word instruction program is stored in the memory with
a starting address of 1000 in decimal. Consider a
[NAT] processes P and 4 instructions. What will be the
8. Consider 20 bits hypothetical CPU which supports 1 program counter (PC) value of during the execution of
word instruction placed in a 8KW memory space. If 3rd instruction?
there exits 126 one address instruction and ab zero
address instruction then calculate the value of a + b.
3

Answer Key
1. (c) 7. (1023 to 1023)
2. (a) 8. (16 to 16)
3. (a,d) 9. (b)
4. (c) 10. (1024 to 1024)
5. (4 to 4)
6. (36 to 36)
4

Hints and Solutions


1. (c) 5. (Range 4 to 4)
Data lines = 64 bits
Address lines = 32 bits
Number of memory location = 232
MR field = 32 – 12
Block size = 64 bits.
= 20
Maximum number of bits stored in memory
Number of cells in memory = 220
= 232 × 64 bit
Cell size = 7 + 5 + 20
2. (a)
= 4 bytes
Memory size = 220 × 4 bytes
= 4 MB

6. (Range 36 to 36)

Number of registers = 24

Number of bits required to locate register = log2 24


3. (a,d)
In Big Endian, lower address contains higher byte and =5
higher address contain lower bytes. Number of Instruction = 120

Opcode = log2 120 = 7


4. (c)
X = (A*B) (C+D) Memory space = 512 KB

I1: PUSH A Bits required to address memory cells = log2 512 K


I2: PUSH B = log2 219
I3: ADD = 19
I4: PUSH C Instruction size = 7 + 5 + 5 + 19
I5: PUSH D = 36
I6: ADD
7. (Rang 1023 to 1023)
I7: MUL Instruction size = 32 bits
I8: POP X
Total number of instructions required in stack CPU is
8.
Number of registers = 24
5

Bits required to represent a register = log2 24 = 5 Memory space = 256 KB


Opcode = 7 bits Address space = log2 218
Immediate field value = 32 – (7 + 5 + 5 + 5) = 18 bits
x = 32 – 22
x = 10
The maximum unsigned constant value possible
= 210– 1 One instruction size = 7 +6 + 6 + 18 + 13
= 1023 = 50 bits
 7 bytes
8. (16) Note:- 50 bits  6 bytes + 2 bits
By default, memory is byte addressable so 7 cell will
Instruction be used for one instructions.
Process size =100 instruction
Memory space = 8 KW = 100× 7 cells
Memory address space = log2 8K = 100 × 7 bytes
= log2 213 = 700 bytes
= 13 10. (Range 1024 to 1024)
Total number of instructions = 27 Word size = 64 bits
= 128 = 8 bytes
Number of one address instruction = 126 Initial PC value = 1000
Then number of zero address instruction I1 – 1000 – 1007
= (128 – 126) × 213 I2 – 1008 – 1015
= 2 ×213 I3 – 1016 – 1023
= 214 I4 – 1024 – 1031
Answer = 2 + 14 = 16 During the execution of I3 instruction PC will store
the address of next instruction.
9. (b) PC →1024
Number of instructions = 84
Opcode = log 2 ( 84 )  = 7 bits
Number of registers = 34
Number of bits required to locate a register = log2 34
=6

For more questions, kindly visit the library section: Link for web: https://smart.link/sdfez8ejd80if

PW Mobile APP: https://smart.link/7wwosivoicgd4

You might also like