Computer Organization and Architecture - Weekly Test 01 - Test Paper
Computer Organization and Architecture - Weekly Test 01 - Test Paper
[MCQ] [MCQ]
1. A microprocessor has a data bus with 64 lines and an 4. Consider 32 bits stack CPU supports 1W opcode and
address bus with 32 lines. The maximum number of 4GB RAM.
bits that can be stored in memory is . Following statement is executed in the system:
12 64
(a) 32 ×2 (b) 32 × 2 X = (A*B) (C+D)
32
(c) 64 × 2 (d) 64 × 264 How many machine instructions required for the
given statement.
[MCQ]
(a) 6 (b) 7
2. Various storage device used by an operating system
(c) 8 (d) None
can be arranged as follows in increasing order of
accessing speed. [NAT]
(a) Secondary memory → main memory → cache 5. Consider 32 bits hypothetical CPU which supports 1-
memory → Register
word long instruction with 7 bits opcode, register
(b) Main memory →Secondary memory→cache
operand field value 5 bits and a memory operand field.
memory→Register Then calculate the total memory size in MB.
(c) Secondary memory →cache memory → main
memory →Register
(d) Main memory → secondary memory→ Register
→ cache memory
[MCQ]
3. In the Big-Endian system, the computer stores.
(a) MSB of data in the lowest memory address of data
unit.
(b) LSB of data in the lowest memory address of data
unit.
(c) MSB of data in highest memory address of data
unit.
(d) LSB of data in the highest memory address of data
unit.
2
[NAT] [MCQ]
6. Consider a hypothetical CPU which supports 9. Consider a hypothetical CPU which supports 84
instruction with 2 register operands and 1 memory instructions. Instruction format contain two registers
operands. CPU supports 120 instructions, 24 register operand, one memory operand and 13 bits immediate
and 512 KB memory space. How many bits are constant field. CPU supports 34 registers 256KB
required to encode the instructions. memory space. A process contains 100 instructions.
How much storage space is required in bytes to store
[NAT] the process.
7. Consider 32 bits CPU which supports 1 words (a) 625 bytes (b) 700 bytes
instruction with 3 Register operands and immediate (c) 600 bytes (d) 725 bytes
operands fields. Processer supports 7 bits opcode and
24 Register with register size of 32 bits. Instruction is [NAT]
placed in a 256KW memory. What is the largest 10. Consider 64 bits hypothetical CPU which supports one
unsigned constant possible in the instruction?
word instruction program is stored in the memory with
a starting address of 1000 in decimal. Consider a
[NAT] processes P and 4 instructions. What will be the
8. Consider 20 bits hypothetical CPU which supports 1 program counter (PC) value of during the execution of
word instruction placed in a 8KW memory space. If 3rd instruction?
there exits 126 one address instruction and ab zero
address instruction then calculate the value of a + b.
3
Answer Key
1. (c) 7. (1023 to 1023)
2. (a) 8. (16 to 16)
3. (a,d) 9. (b)
4. (c) 10. (1024 to 1024)
5. (4 to 4)
6. (36 to 36)
4
6. (Range 36 to 36)
Number of registers = 24
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