Computer Organization

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UNIT – 5
Memory Organization: Memory Hierarchy, Main Memory –RAM And ROM Chips, Memory Address
map, Auxiliary memory-magnetic Disks, Magnetic tapes, Associate Memory,-Hardware
Organization, Match Logic, Cache Memory –Associative Mapping , Direct Mapping, Set associative
mapping ,Writing in to cache and cache Initialization , Cache Coherence ,Virtual memory-Address
Space and memory Space ,Address mapping using pages, Associative memory page table ,page
Replacement .

Memory Hierarchy

The total memory capacity of a computer can be visualized by hierarchy of components. The
memory hierarchy system consists of all storage devices contained in a computer system from the
slow Auxiliary Memory to fast Main Memory and to smaller Cache memory.
Auxillary memory access time is generally 1000 times that of the main memory, hence it is at the
bottom of the hierarchy.
The main memory occupies the central position because it is equipped to communicate directly with the
CPU and with auxiliary memory devices through Input/output processor (I/O).
When the program not residing in main memory is needed by the CPU, they are brought in from
auxiliary memory. Programs not currently needed in main memory are transferred into auxiliary
memory to provide space in main memory for other programs that are currently in use.
The cache memory is used to store program data which is currently being executed in the CPU.
Approximate access time ratio between cache memory and main memory is about 1 to 7~10

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Memory Access Methods

Each memory type, is a collection of numerous memory locations. To access data from any memory,
first it must be located and then the data is read from the memory location. Following are the methods
to access information from memory locations:

1. Random Access: Main memories are random access memories, in which each memory
location has a unique address. Using this unique address any memory location can be reached
in the same amount of time in any order.
2. Sequential Access: This methods allows memory access in a sequence or in order.
3. Direct Access: In this mode, information is stored in tracks, with each track having a
separate read/write head.

Main Memory
The memory unit that communicates directly within the CPU, Auxillary memory and Cache
memory, is called main memory. It is the central storage unit of the computer system. It is a large and
fast memory used to store data during computer operations. Main memory is made up
of RAM and ROM, with RAM integrated circuit chips holing the major share.

 RAM: Random Access Memory

o DRAM: Dynamic RAM, is made of capacitors and transistors, and must be
refreshed every 10~100 ms. It is slower and cheaper than SRAM.
o SRAM: Static RAM, has a six transistor circuit in each cell and retains data, until
powered off.

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o NVRAM: Non-Volatile RAM, retains its data, even when turned off. Example: Flash
memory.
 ROM: Read Only Memory, is non-volatile and is more like a permanent storage for
information. It also stores the bootstrap loader program, to load and start the operating system
when computer is turned on. PROM(Programmable ROM), EPROM(Erasable PROM)
and EEPROM(Electrically Erasable PROM) are some commonly used ROMs.

Memory Address map:

 The addressing of memory can establish by means of a table that specifies the memory
address assigned to each chip.
 The table, called a memory address map, is a pictorial representation of assigned address
space for each chip in the system, shown in the table.
 To demonstrate with a particular example, assume that a computer system needs 512 bytes of
RAM and 512 bytes of ROM.
 The RAM and ROM chips to be used specified in figures.

 The component column specifies whether a RAM or a ROM chip used.

 Moreover, The hexadecimal address column assigns a range of hexadecimal equivalent
addresses for each chip.
 The address bus lines listed in the third column.
 Although there 16 lines in the address bus, the table shows only 10 lines because the other 6
not used in this example and assumed to be zero.
 The small x‟s under the address bus lines designate those lines that must connect to the
address inputs in each chip.
 Moreover, The RAM chips have 128 bytes and need seven address lines. The ROM chip has
512 bytes and needs 9 address lines.
 The x‟s always assigned to the low-order bus lines: lines 1 through 7 for the RAM. And lines
1 through 9 for the ROM.
 It is now necessary to distinguish between four RAM chips by assigning to each a different
address. For this particular example, we choose bus lines 8 and 9 to represent four distinct
binary combinations.
 Also, The table clearly shows that the nine low-order bus lines constitute a memory space for
RAM equal to 29 = 512 bytes.
 The distinction between a RAM and ROM address done with another bus line. Here we
choose line 10 for this purpose.
 When line 10 0, the CPU selects a RAM, and when this line equal to 1, it selects the ROM.

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Auxiliary Memory
Devices that provide backup storage are called auxiliary memory. For example: Magnetic
disks and tapes are commonly used auxiliary devices. Other devices used as auxiliary memory are
magnetic drums, magnetic bubble memory and optical disks.
It is not directly accessible to the CPU, and is accessed using the Input/Output channels.

Cache Memory
The data or contents of the main memory that are used again and again by CPU, are stored in
the cache memory so that we can easily access that data in shorter time.
Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not found in
cache memory then the CPU moves onto the main memory. It also transfers block of recent data into
the cache and keeps on deleting the old data in cache to accomodate the new one.

Hit Ratio
The performance of cache memory is measured in terms of a quantity called hit ratio. When
the CPU refers to memory and finds the word in cache it is said to produce a hit. If the word is not
found in cache, it is in main memory then it counts as a miss.
The ratio of the number of hits to the total CPU references to memory is called hit ratio.
Hit Ratio = Hit/(Hit + Miss)

Associative Memory
It is also known as content addressable memory (CAM). It is a memory chip in which each
bit position can be compared. In this the content is compared in each bit cell which allows very fast
table lookup. Since the entire chip can be compared, contents are randomly stored without
considering addressing scheme. These chips have less storage capacity than regular memory chips.

Memory Mapping and Concept of Virtual Memory

The transformation of data from main memory to cache memory is called mapping. There are 3
main types of mapping:

 Associative Mapping
 Direct Mapping
 Set Associative Mapping

Associative Mapping
The associative memory stores both address and data. The address value of 15 bits is 5 digit
octal numbers and data is of 12 bits word in 4 digit octal number. A CPU address of 15 bits is placed
in argument register and the associative memory is searched for matching address.

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Direct Mapping
The CPU address of 15 bits is divided into 2 fields. In this the 9 least significant bits constitute
the index field and the remaining 6 bits constitute the tag field. The number of bits in index field is
equal to the number of address bits required to access cache memory.

Set Associative Mapping

The disadvantage of direct mapping is that two words with same index address can't reside in cache
memory at the same time. This problem can be overcome by set associative mapping.
In this we can store two or more words of memory under the same index address. Each data word is
stored together with its tag and this forms a set.

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Replacement Algorithms
Data is continuously replaced with new data in the cache memory using replacement algorithms.
Following are the 2 replacement algorithms used:

 FIFO - First in First out. Oldest item is replaced with the latest item.
 LRU - Least Recently Used. Item which is least recently used by CPU is removed.

Writing in to cache and cache Initialization:

The benefit of write-through to main memory is that it simplifies the design of the computer
system. With write-through, the main memory always has an up-to-date copy of the line. So when a
read is done, main memory can always reply with the requested data.

If write-back is used, sometimes the up-to-date data is in a processor cache, and sometimes it is in
main memory. If the data is in a processor cache, then that processor must stop main memory from
replying to the read request, because the main memory might have a stale copy of the data. This is
more complicated than write-through.

Also, write-through can simplify the cache coherency protocol because it doesn't need
the Modifystate. The Modify state records that the cache must write back the cache line before it
invalidates or evicts the line. In write-through a cache line can always be invalidated without writing
back since memory already has an up-to-date copy of the line.

Cache Coherence:
In a shared memory multiprocessor with a separate cache memory for each processor , it is possible
to have many copies of any one instruction operand : one copy in the main memory and one in
each cache memory. When one copy of an operand is changed, the other copies of the operand must
be changed also. Cache coherence is the discipline that ensures that changes in the values of shared
operands are propagated throughout the system in a timely fashion.

Virtual Memory
Virtual memory is the separation of logical memory from physical memory. This separation provides
large virtual memory for programmers when only small physical memory is available.

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Virtual memory is used to give programmers the illusion that they have a very large memory even
though the computer has a small main memory. It makes the task of programming easier because the
programmer no longer needs to worry about the amount of physical memory available.

Address mapping using pages:

 The table implementation of the address mapping is simplified if the information in the
address space. And the memory space is each divided into groups of fixed size.
 Moreover, The physical memory is broken down into groups of equal size called blocks,
which may range from 64 to 4096 words each.
 The term page refers to groups of address space of the same size.
 Also, Consider a computer with an address space of 8K and a memory space of 4K.
 If we split each into groups of 1K words we obtain eight pages and four blocks as shown in
the figure.
 At any given time, up to four pages of address space may reside in main memory in any one
of the four blocks.

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Associative memory page table:

The implementation of the page table is vital to the efficiency of the virtual memory
technique, for each memory reference must also include a reference to the page table. The fastest
solution is a set of dedicated registers to hold the page table but this method is impractical for large
page tables because of the expense. But keeping the page table in main memory could cause
intolerable delays because even only one memory access for the page table involves a slowdown of
100 percent and large page tables can require more than one memory access. The solution is to
augment the page table with special high-speed memory made up of associative registers or
translation look aside buffers (TLBs) which are called ASSOCIATIVE MEMORY.
Page replacement
The advantage of virtual memory is that processes can be using more memory than exists in
the machine; when memory is accessed that is not present (a page fault), it must be paged in
(sometimes referred to as being "swapped in", although some people reserve "swapped in to refer to
bringing in an entire address space).

Swapping in pages is very expensive (it requires using the disk), so we'd like to avoid page faults as
much as possible. The algorithm that we use to choose which pages to evict to make space for the
new page can have a large impact on the number of page faults that occur.

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