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Experiment 6

The report details the design and FPGA implementation of a traffic light controller using Verilog, conducted by Tisa Nayak as part of the EC-3095 course. It includes the necessary equipment, theoretical background, design and testbench code, and results from simulation and synthesis. The experiment concludes with successful design and verification of the traffic light controller's functionality.

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14 views13 pages

Experiment 6

The report details the design and FPGA implementation of a traffic light controller using Verilog, conducted by Tisa Nayak as part of the EC-3095 course. It includes the necessary equipment, theoretical background, design and testbench code, and results from simulation and synthesis. The experiment concludes with successful design and verification of the traffic light controller's functionality.

Uploaded by

ritzaria1911
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SCHOOL OF ELECTRONICS ENGINEERING

VLSI DESIGN LABORATORY REPORT


(EC-3095)

Submitted By:

Name: Tisa Nayak

Roll No: 1730202

Section: ECS-2

Semester: 7th (Autumn)

Year: 2020-2021
Experiment No.: 06

Tasks to be completed in the Experiment:

Design of traffic light controller, using Verilog, and it’s FPGA

implementation.
Aim of the Experiment:
Design of traffic light controller, using Verilog, and it’s FPGA
implementation.

Equipment and Software Required:


The Equipment and Software required are as follows:
 EDA Playground (online Verilog Simulator) using Aldec Riviera Pro
2019.0 for simulation and Yosys 0.9.0 for synthesis.

Theory:

Traffic Light Controller:

Traffic light which is one of the vital


public facilities that plays an
important role to the road users.
Traffic lights were first installed in
1868 in London, United Kingdom,
outside the British Houses of
Parliament in London, by the railway
engineer J. P. Knight and constructed
by the railway signal engineers of
Saxby & Farmer. Traffic lights, also known as traffic signals, traffic lamps,
signal lights, stop lights and also known technically as traffic control
signals are signaling devices positioned at road intersections, pedestrian
crossings and other locations to control competing flows of traffic. Traffic
lights alternate the right of way accorded to road users by displaying lights
of a standard color (red, yellow, and green) following a universal color
code. The typical sequence of color phases are as follows: GREEN- Allows

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traffic to proceed in the direction denoted. YELLOW- Provides warning
that the signal will be changing from green to red. RED- Prohibits any
traffic from proceeding.

A sensor on the farm is to detect if there are any vehicles and change the
traffic light to allow the vehicles to cross the highway. Otherwise, highway
light is always green since it has higher priority than the farm.

Fig: State diagram of traffic light controller

Code:
TASK:

%Program to design traffic light controller, using Verilog, and it’s


FPGA implementation

TESTBENCH CODE:

module traffic_light_tb();

reg rst,clk;

wire h_red,h_yellow,h_green,s_red,s_yellow,s_green;

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traffic_light L0(rst,clk,h_red,h_yellow,h_green,s_red,s_yellow,s_green);

initial begin

$dumpfile("dump.vcd");

$dumpvars;

clk=0;

rst=1;#10;

rst=0;#1000

$finish;

end

always #10 clk=!clk;

endmodule

DESIGN CODE:

module traffic_light (rst, clk, h_red, h_yellow, h_green, s_red, s_yellow,


s_green);

input rst,clk;

output reg h_red, h_yellow, h_green, s_red, s_yellow, s_green;

reg [1:0] state;

reg [4:0] count;

parameter s0=0,s1=1,s2=2,s3=3;

initial state=0;

initial h_red=0;

initial h_yellow=0;

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initial h_green=0;

initial s_red=0;

initial s_yellow=0;

initial s_green=0;

initial count=0;

always @(posedge clk) begin

if(rst)

state=s0;

else

case(state)

s0: begin

if(count==20) begin

count=0;

state=s1;

end

else begin

state=s0;

count=count+1;

end

end

s1: begin

if(count==10) begin

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count=0;

state=s2;

end

else begin

state=s1;

count=count+1;

end

end

s2: begin

if(count==10) begin

count=0;

state=s3;

end

else begin

state=s2;

count=count+1;

end

end

s3: begin

if(count==5) begin

count=0;

state=s0;

5
end

else begin

state=s3;

count=count+1;

end

end

endcase

end

always @(state) begin

case(state)

s0: begin

h_green=1;

s_red=1;

h_red=0;

h_yellow=0;

s_yellow=0;

s_green=0;

end

s1: begin

h_green=0;

s_red=1;

h_red=0;

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h_yellow=1;

s_yellow=0;

s_green=0;

end

s2: begin

h_green=0;

s_red=0;

h_red=1;

h_yellow=0;

s_yellow=0;

s_green=1;

end

s3: begin

h_green=1;

s_red=0;

h_red=0;

h_yellow=0;

s_yellow=1;

s_green=0;

end

endcase

end

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endmodule

Output/Graph:
Synthesis Result:

Simulation Result:

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Discussion/Inference of the experiment:
Designing of traffic light controller, using Verilog, and it’s FPGA
implementation, and obtaining their circuit design using Yosys 0.9.0 (for
synthesis) and their EPwaveform using Aldec Riviera Pro 2019.10 (for
simulation).

Conclusion:
This experiment enabled us to design the Verilog code for traffic light
controller, using Verilog, and it’s FPGA implementation. Also the test
bench for verification is written, in the alternative online Verilog
simulator, EDA Playground. The EPwaveform is observed and the code is
synthesized with the technological library and verified.

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____________________
_
Signature of Faculty

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