Decimal Adders (2/3)

4 4
A8 A4 A2 A1 A S
+ B8 B4 B2 B1 Decimal adder
- -

4
B C
2-4
-

Zoo Zz Z I

÷÷÷÷÷÷i÷÷÷
÷÷÷
.

> g

29
Decimal Adders (3/3)
B 8 B 4 B 2 B 1 A8 A4 A2 A1

-74
Zoo

Zoo .

Za

O I I 0
zoo Zq 2-2 ZI

30
 2h
o Multiplication / division by

⇒ shift left / right w

digits

binary
100 =
bc 3 :O ] o o
X
BCI :O ]

3:03 ÷ too = b
] bz.be bo
b C

Binary Multiplier

31
 Multiply/Divide by 2

• Multiplication/division by 2n
– Shift left/right

32
 M-Bit x N-Bit Multiplication

0000
0000

1-

33
 2-Bit x 2-Bit Binary Multiplier
B1 B0
x A1 A0
B
,
to Botto

Betti Both A0B1 A0B0

f-
#

C C Cl
,
2 Co

A1B1 A1B0

34
BC 3:03 A @
2:03

4-Bit x 3-Bit Binary Multiplier

or
a
v
O
①
O

O
35
 Array Multiplier

a3

a2

a1

a0
b0

b1

-
FA FA FA FA 0

b2

FA FA FA FA 0

b3

FA FA FA FA 0
p7

p6

p5

p4

p3

p2

p1

p0
36
Decoders

37
 ÷
One-Hot Representation

• Represent a set of N elements with N bits. Code

• Exactly one bit is set. Binary One-hot
Az At Ao 177136 -
Do
000 00000001
. -

001 00000010
010 00000100
011 00001000
100 00010000
101 00100000
110 01000000
111 10000000 38
 EN

x-DF
-

-
x Enabling Function

• Enabling permits an input signal to pass through to

an output.
• When EN = 0, buffer is disabled, F = 0.
I

EN X F • When EN = 1, buffer is enabled, F = X.

0 0 0 disabled• In general, when a block is disabled,

( ) the output can be a fixed value or
0 1 0 high impedance.
1 0 0 enabled

1 1 1
) F
-

-
X
X
-

D- F

F
-

- Enix
FYI) -

D- f

39
 Decoding
hot code
code one
binary
→ -

• n-to-m line decoder: the conversion of an n-bit input code to

-

an m-bit output code with n £ m £ 2n such that each valid

-

code word produces a unique output code.

– Output variables are mutually exclusive. Only one output can be 1 at a
time.
– Binary to one-hot decoder.
• Circuits that perform decoding are called decoders.
• A binary one-hot decoder converts a symbol from binary code
to one-hot code.

I
Binary input a to one-hot output b

Decoder
I b[i] = 1 if a = i
n
a b
m
b = 1<<a
n
m ≤ 240
 Decoder Examples
At
Do

OF
A D ,
Do =

• 1-to-2-Line Decoder D
, = A

i i o
A

• 2-to-4-Line Decoder
A0
– Two 1-to-2 line decoders +

A1 A0 D0 D1 D2 D3 4 AN Ds
A1
0 0 1 0 0 0 D0 = A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 = A 1 A 0

(a)
D2 = A 1 A 0

D3 = A 1 A 0
41
(b)
 Decoder Expansion

• 3-to-8-line decoder
– Number of output ANDs = 8
– Number of inputs to decoders driving output ANDs = 3
– Closest possible split to equal
• 2-to-4-line decoder
• 1-to-2-line decoder
– 2-to-4-line decoder
• Number of output ANDs = 4
• Number of inputs to decoders driving output ANDs = 2
• Closest possible split to equal
– Two 1-to-2-line decoders

42
 table
Truth

page
33 .

3-to-8 Line Decoder (1/2)

ID
I
Da =AzAiAo
AI
°
- -

Do
-

Aa Ao

=D
-
-

Asai AT

AID
=
-

Db
AT m -

Do Eo

TIED
At
=AzAiAo
-

Ds
-

AT
-

Ao -
Do -

)
-

Dq =
AIAAT ,

- D ,
= AT AI Ao

- D2 -
- AIA ,
AT

-
Dl = AIAT Ao

Do -
-
AIATAI

43
 Decoder Expansion

• 8
3-to-8-line decoder r
– Number of output ANDs = 8
– Number of inputs to decoders driving output ANDs = 3
-

– Closest possible split to equal

y
• 2-to-4-line decoder
•✓ 1-to-2-line decoder
– 2-to-4-line decoder
• Number of output ANDs = 4

I • Number of inputs to decoders driving output ANDs = 2

-

• Closest possible split to equal

– Two 1-to-2-line decoders

42
 table
Truth

page
33 .

3-to-8 Line Decoder (1/2)

ID
I
Da =AzAiAo
AI
°
- -

Do
-

Aa Ao

=D
-
-

Asai AT

AID
=
-

Db
AT m -

Do Eo

TIED
At
=AzAiAo
-

Ds
-

AT
-

Ao -
Do -

)
-

Dq =
AIAAT ,

- D ,
= AT AI Ao

- D2 -
- AIA ,
AT

-
Dl = AIAT Ao

Do -
-
AIATAI

43
 ouI
Ao

too
Al

3-to-8 Line Decoder (2/2)

Athol
0
0100
I

AIIOO O

I
A-,

AIA
O
✓

u
AT
I ] D
-

-
AIATAI

A
A
= ALAI AT
a

44
 7-to-128 Line Decoder (1/2)

0
• 7-to-128-line decoder
– Number of output ANDs = 128
– Number of inputs to decoders driving output ANDs = 7
– Closest possible split to equal
• 4-to-16-line decoder
• 3-to-8-line decoder
– 4-to-16-line decoder
• Number of output ANDs = 16
• Number of inputs to decoders driving output ANDs = 2
• Closest possible split to equal
– 2 2-to-4-line decoders

45
 7-to-128 Line Decoder (2/2)

'tt-
415

Ab -

Drb
Ty
! 's
-

A4

a.io#-xiaFIED-Dn7A5--dec/
-
-

Xo
- l
A 3
I

Ya
At I

':tc
-

.
,
At D
Yo Yo
-
-
-
,
Ao -
,

÷D-
Do

Practice :

gate input ?

46
 Advantages of Dividing Large Decoder
D6z=A5A4AsA2AIAo
A
THE
If Dando
AT
• 6-to-64 decoder requires 1762 = A5AqA3AzAI
( – 64 6-input AND gates (384 inputs) :

• 6-to-64 decoder using 2-to-4 decoders requires

( – 12 2-input AND gates (24 inputs)
– 64 3-input AND gates (192 inputs)
• Faster, smaller, lower power;
-17063 ID
-
As 33
Xz

¥91
-

"

- Too ?? -

Dba
y ,

ftp.TEYi-a
93 = ASA 2 32
A
n.ae/2-aIi4t-
3 '
to
X3=A5A4
4
12
-

ya
- -

As -
dec :
- -
To

' "
At -

I D- Do
21 47
Ao
-
-

-
to
to
 Combinational Logic
Implementation with Decoders (1/2)
• Any combinational circuit with n inputs and m outputs can be
implemented with an n-to-2n decoder and m OR gates.
• Example: F(x,y,z)=Σ(1,2,4,7)
-

I aE÷ .
-
r
.

48
 Combinational Logic
Practice Implementation with Decoders (2/2)

• Example: 3-bit prime detector

F(x,y,z)=Σ(1,2,3,5,7)

49
Encoders

50
 Encoding

• Encoding: the opposite of decoding - the conversion of an m-

bit input code to a n-bit output code with n £ m £ 2n such
that each valid code word produces a unique output code.
• Circuits that perform encoding are called encoders.
• An encoder has 2n (or fewer) input lines and n output lines
which generate the binary code corresponding to the input
values.
• Typically, an encoder converts a code containing exactly one
bit that is 1 to a binary code corresponding to the position in
-

which the 1 appears.

=

51
 A 4-to-2 Encoder
B Bo B -_
Azt a 2
Az Az At Ao , ,

-
°

o o o I
°
Bo= Azt At
O I
° O I O

I O
O
I O O
A 3

=D B
-
I I ,
I o o
0
Az

X X
Az
AID
o o o
o
-
Bo

52
 Design a Larger Encoder

• Additional summary
output (High bits) is
true if any input of the High bits
encoder is true. Low bits

4:2
a[15:12]
4 2
• First rank encodes low
bits, second rank

4:2
a[11:8] b[3:2]

4:2
encodes high bits. 4 2 2

a[7:4]

4:2
4 2

b[1:0]
4:2

a[3:0]
2
4 2
53
 ✓
8-to-3 Line Encoder
bit
h
high

ooh
bcz :o) :

input act :O ]
,
output
bz b ,
bo
a do
Az Az

9000
Ay
,

At AG As O
O

O
O I O

O O
O O O
O I O 0 o I
O O
O O

2/-4101
°

000010000100¥
O O I O
O O I O
O O
O
O O O I I
O O I O
O

O O O L O I
o
O I O
O
O O O I I O
O

to
O
o

O
O O O O I I I
I O

hzb

I10ha
-Oo
00
do
10-12
Y!
Aa -
hi hi '
b
,
-

- -

-
to

Ien€
4 -
-

I ,
af -

, o

as I O
Yo
D
o
bo
-14-4-27
-

act
-

ha - bae
to

f-
.
-

to I
Xi
-
-

as
-
-

O I
ol
-
etc h -
ere
Xo ,

54
-

%
 Design a Larger Encoder
(6 to -
-

• Additional summary

4h30
output (High bits) is
true if any input of the High bits
encoder is true. Low bits

4:2
a[15:12]
4 2
• First rank encodes low
bits, second rank ha

4:2
a[11:8] b[3:2]

4:2
encodes high bits. 4 2 2

h hah ho b ba hi
,

①
, ,

I a[7:4]

4:2
I
O o o I
4 2
O I O O I O
no

:O
: :
b[1:0]
4:2

a[3:0]
2
4 2
53
 O
- - n
- b bzb bo
454443424 Yoda aooayabas-auasaza.no
,
,
,

O O O O O O O
I
O O - -
-

O O I O O O 0 I

0001€
O O - .
-

O L O O O O I O
O
- -

O
-

O
I O O
O O I I

0001001€
O O
I O O I O I
O I O O
O
I L O
O O O
(

I 00 O

O O I O 00 I
I
I O O I O
O L O

O I O I
L O O l

- I I 00
O O
I O
O
.
-
.

I I O I
O I O O
. -

O
-

I I I O
U I O O .
-
-

I I l I
I O O
- .
 ✓
8-to-3 Line Encoder
bit
h
high

ooh
bcz :o) :

input act :O ]
,
output
bz b ,
bo
a do
Ay Az Az

+000
,

At AG As O
O

O
O I O

O O
O O O
O I O 0 O I
O O
O O
°

000010000100¥
O O I O
O O I O
O O
O
O O O I I
O O I O
O

O O O L O I
o
O I O
°
O O O I I O
O

to
O
o

O
O O O O I I I
I o

hzb IT

ohh
00
ol
do
10
'
at hi hi -
b hi

21
-
- -
Ya -

Toi
4 -
to as
y ,
-

af -
,

04

-enC↳
as yo , o

=D
o
bo
9×1
-14-4-27
-

act
ha
?I
-

ha bz

-42
-

tten
.
-

on
I
" '
? !
-

ao
at ene
-
he -

54
to
thy I

Multiplexers

55
 Multiplexers
select information from inputs
• Multiplexer: binary
u
one
.

– n k-bit inputs
– n-bit one hot select signal s
• Multiplexers are used as data selectors.
input
a0 output
k b
Max

an-1 k
k
D s
n
Control
input
56
 One Hot vs. Binary Select

• One hot: n k-bit input lines, one n-bit control line

I b
3- to s
-

-
MUY o o I do

O I O At

I O O Az
-

• Binary select: n k-bit input lines, one m-bit control line

I S b
3- to -

O O do
Max
O I
Al

10
as
I I
X
✓

binary 57
 ( binary
select )

2-to-1 Multiplexer (1/2)

• The multiplexer circuit shown:

– 1:2-line decoder
– 2 enabling circuits
– 2-input OR gate
• To obtain a basis for multiplexer expansion, we combine the
Enabling circuits and OR gate into a 2 ´x 2 AND-OR circuit:
r r
– 1:2-line decoder

##
– 2 x 2 AND-OR Two 2- input

'd
ads
,

Arps
• n
In general, for an 2 :1-line multiplexer: s

①
– N:2n-line decoder zu dgdadidohd

①
h -
to -
O O
O O O

a
– 2n x 2 AND-OR ol 0010

I O
0
I o O

I I I o o O %
-
do 58
 " " t "

?¥%t¥
If
was .am ,

#
.

b
It To
s a
,
Ao it to
ol

↳ (
O

l
::
O
I
O
I
:
l

0
b=5aot
,

a
5.

(
,
I O
b- at
- I O

I O I
I

l I I I
enabling
diagram
③ logic ao -

}D
- b
Dp
g.gg#yq!z,y.,npu+anp.on
2-to-1 Multiplexer (2/2)

59
 4:1 Multiplexer (1/2)
binary select

• 2:22-line decoder
• 22 x 2 AND-OR 2- to -4 dec

Decoder
S1

443 x22AND-OR
AND-OR
S0
do
= =
Decoder
S1

S[1:0]: binary select S0

I0

: I1
Y

I2
d ]

I3
60
 4:1 Multiplexer (2/2)
?
at -
b

S[3:0]: one hot

-

a0
a0
s0
s0
a1
a1
s1
b s1 b
a2
a2
s2
s2
a3
a3
s3
s3

AND-OR implementation 3-state buffer implementation

-

61
Quadruple 2:1 MUX (4-Bit 2:1 MUX)

00
?€
Ot
-

ya
(
.

-00
.
A Asis °

Boo
Bao
O

13,0
-

=
Bz O

a÷÷
Ask

-1310
=
Bz O

Bo '

B
( Bis

Djs
-
-
)
disabled
enabled

?I I
5=1

Bz .
5. -
-

B .s
,
-

62
I I
-

E -
-
O
,
-
 K-Bit n:1 MUX
symbol

select
binary
Il
.

E 7
= hot
one

63
 I b
-
to
-
I Large Binary Select MUX
at

• Larger binary select MUX can be

constructed from smaller binary 01

select MUXes.
G-

• 16:1 MUX can be constructed ol

from five 4:1 MUXes.

Sb ,
Sbz Sb
,
Sbo b Aq
-
O
O O O Ao

O O O I Al ol

O O I O Az

I
O O I Az
-

° A
I O O Cry
I)
O I O I ol
05
O I O ab

①
I
°
I I I 64
art
Boolean Function Implementation
with a MUX (1/2)
X select inputs
o ,
y :

°
3 : data input

÷¥÷÷
o
.

65
 Boolean Function Implementation
with a MUX (2/2)
• Assign an ordering sequence of the n-1 input variables (x,y) to
the selection input of MUX.
• The last variable (z) will be used for the input lines.
• Construct the truth table.
• Consider a pair of consecutive minterms starting from m0.
• Determine the input lines according to the last variable (z) and
output signals (F) in the truth table.

66
Arbiters and Priority Encoders

67
 Arbiters

• Arbiter handles requests from multiple devices to

use a single resource.
– Also called find-first-one (FF1) unit.
-

– Accepts an arbitrary input signal r and outputs one-hot

signal g to indicate the least significant 1 (or the most
=

significant 1) of the input.

• Example: input 01011100
– Output: 00000100 (least significant 1)
– Output: 01000000 (most significant 1)

68
 inputs
outputs
.

) wcitid
°
rci ] ncis gci
-
O O
O O

O I O I uci ] : no one
yet
O O
I O
whew wCiT=2 it
,
° " "
I I I
means there is no I

get
gcio
.

-
rci →

) → wait 'T
uCi3→ -

✓ ncis
gcit-rc.is
.

✓
wcitlT-rc.to ncis

69
 Arbiters Implementation
wci ]

µ
to Kratz 809,9293
High
No_one_yet[i]
-

, I x x X A O
o o
r0
g0 O I X X O I o O

:
r0 g0
r1
r[i] g1
g[i] g1
r1

g2
r2
r2
g2
No_one_yet[i+1]

g3
r3

r3 Using lookahead
wciti g3

✓ 85-flro.h.rz.rs )
1-bit cell of arbiter
g ,

Using bit-cell
92 70
93
 Priority Encoder (1/2)

• If more than one input value is 1, then the encoder just

designed does not work.
• One encoder that can accept all possible combinations of
input values and produce a meaningful result is a priority
encoder.
• Among the 1s that appear, it selects the most significant input
position (highest priority) containing a 1 and responds with
the corresponding binary code for that position.

71
 Priority Encoder (2/2)

Encoder
Arbiter
r g a b
n n m

m= log2n

Encoder
Priority
a b
n m

72
Comparators

73
 Equality Comparator
a
Comparator
n
eq

b
n

a3 0
eq3
b3
a2
eq2
b2
eq
a1
eq1
b1
a0
eq0
b0
74
 Magnitude Comparator (1/2) outputs
-
• Compare two numbers A and B A > B A- B ACB

– Three possible results (A > B, A = B, A < B) when I O O

ATB
• Design approach for n-bit numbers when
I O
– By truth table (need 22n
rows, not practical) AIB
o

– By algorithm to build a regular circuit when

° 0 I
• A = A3A2A1A0, B=B3B2B1B0 AaB

• A = B if A3 = B3, A2 = B2, A1 = B1, A0 = B0

– Equality xi = AiBi + Ai’Bi’, (A = B) = x3x2x1x0
• (A > B) = A3B3’ + x3A2B2’ + x3x2A1B1’ + x3x2x1A0B0’
• (A < B) = A3’B3+x3A2’B2 + x3x2A1’B1 + x3x2x1A0’B0

75
 13=13313213 Do
A=A3A2AiAo ,
,

A 2B
whew A) 7133 A 3=1 133=0
① ,
,

② when A 3=133
( Atto , =D A 2=1 ,
132=0
,

⑤ when
A, '
Bz A 2=1322 At =L
,
131=0
, ,

when A 3=133 At Bl A 0=1 13,0=0

④ As Bz
-

- -
-
,
,
,
,

76
Magnitude Comparator (2/2)

77
Shifters

78
 Shifters
• Shifter: shifts one bit to the left or right at a time.
I
• Logical shifter: shift the number to the left or right and fills empty
.

spots with 0’s. " "

– Example: 1101 O
→
/¥I→ -0110

LSR 1 = 0110
=
" 01
→ I
→
lol -0
z
.

• Arithmetic shifter: same as logical shifter but on right shift fills

empty MSBs with the sign bit (sign extension).
/rig
" O '
– Example: 1101 → → -1110

LSR 1 = 1110 " 01

→ I It
-3 1010
} • Barrel shifter: rotate numbers in a circle such that empty spots are
.

filled with the bits shifted off the other end.

– Example: 1101 101
/tf
1101
I → → 1110

LSR 1 = 1110
17¥ 101=1
→
79