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Lecture 3

The document discusses the concepts of presettable counters, focusing on synchronous and asynchronous presetting, and provides examples of various integrated circuit (IC) counters such as the 74ALS160-163 and 74HC160-163 series. It explains the operation of synchronous up/down counters, the importance of control inputs for counting direction, and the methods for extending the maximum counting range using decoding techniques. Additionally, it outlines the steps for analyzing and designing counters, including state transition diagrams and logic expressions.

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Karim Saleh
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4 views

Lecture 3

The document discusses the concepts of presettable counters, focusing on synchronous and asynchronous presetting, and provides examples of various integrated circuit (IC) counters such as the 74ALS160-163 and 74HC160-163 series. It explains the operation of synchronous up/down counters, the importance of control inputs for counting direction, and the methods for extending the maximum counting range using decoding techniques. Additionally, it outlines the steps for analyzing and designing counters, including state transition diagrams and logic expressions.

Uploaded by

Karim Saleh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LOGIC II

Counters & Register


Lecture 3

Dr. Marwa Gamal Abd El-Azeem


Review Questions
1. What is meant when we say that a
counter is presettable?

2. Describe the difference between


asynchronous and synchronous
presetting.
IC SYNCHRONOUS COUNTERS
Examples of IC counters that use synchronous
presetting :::::

TTL 74ALS160, 74ALS161, 74ALS162, and 74ALS163


and their CMOS equivalents, 74HC160, 74HC161,
74HC162, and 74HC163.

The 74ALS160-163/74HC160-163
Series
 clocked by a PGT applied to CLK.
 Two of the counters are MOD-10 counter
while the other two are MOD-16 counter
The 74ALS160-163/74HC160-163
Series
 ENT and ENP are essentially ANDed together
to control the count function.
If either or both of the count enable controls is
inactive (LOW), the counter will hold.
The count up with PGT on CLK, all four of the
control inputs must be HIGH.
 ENT controls
RCO.
The counter contains four FFs.
– The IC has an active-low asynchronous CLEAR input.
– For these counters to be synchronously cleared, the
CLR input must be LOW and a PGT must be applied to the
clock input.
– The counter can be preset to any value (applied to the A,
B, C, and D inputs) by applying an active-low LOAD input.
– The counter is controlled shown in Figure 7-13c.
Example 1
A 74HC163 has the input signals given in the timing
diagram applied. The parallel data inputs are permanently
connected as 1100. Assume the counter is initially in the
0000 state, and determine the counter output waveforms.
Example 2
A 74HC160 has the input signals given in the
timing diagram applied. The parallel data inputs
are permanently connected as 0111. Assume the
counter is initially in the 0000 state, and
determine the counter output waveforms.
74ALS190 -> 75ALS191 Series
Synchronous Up/Down Counters
 To count, the LOAD control input must be
inactive (HIGH) and the count enable control
CTEN must be LOW. The count direction is
controlled by the D/U control input.

 If D/U is LOW, the count is incremented with


each PGT on CLK, while a HIGH on D/U will
decrement the count.

 MAX/MIN detects only one state in the count


sequence—it just depends on whether it is
counting up or down.

 The active LOW RCO output is only enabled


when CTEN is LOW.
 EXAMPLE

A 74HC190 has the input signals given in


the timing diagram applied. The parallel
data inputs are permanently connected as
0111. Assume the counter is initially in the
0000 state, and determine the counter
output waveforms.
 EXAMPLE
 Compare the operation of two counters, one with
synchronous load and the other with asynchronous load.
Refer to Figure 7-18(a), in which a 74ALS163 and a
74ALS191 have been wired in a similar fashion to count
up in binary. Both chips are driven by the same clock
signal and have their QD and QC outputs NANDed
together to control the respective LOAD input control.
Assume that both counters are initially in the 0000 state
and Load input is 0001

(a) Determine the output waveform for each counter.


(b) What is the recycling count sequence and modulus for
each counter?
(c) Why do they have different count sequences?
Extending Maximum Counting Range
 Displaying the contents
 Connecting the output of each FF to a small
indicator LED
The indicator LED method becomes
inconvenient as the size (number of bits) of the
counter increases because it is much harder to
decode the displayed results mentally.
 Electronically decoding is preferable method
Active-HIGH Decoding
 A MOD-X counter has X different states
 A decoding network is a logic circuit that
generates X different outputs.

 Using AND Gates for decoding


To Decode a MOD-8 Counter
(produce pulse at specific count)

Active-LOW Decoding
 Using NAND Gates for decoding
Active-HIGH Decoding
 How many AND gates are required to decode
completely all of the states of a MOD-32 binary
counter?

• What are the inputs to the gate that decodes for


the count of 21 (that is,101012)?
by predicting the FF control inputs for
each state of the counter

Steps of Analysis process

1) write the logic expression for each FF control


input.
2) Assume a PRESENT state for the counter
3) Apply that combination of bits (PRESENT state
) to the control logic expressions.
4) The outputs from the control expressions will
allow us to predict NEXT state
5) Repeat the analysis process until the entire
count sequence is determined.
EXAMPLE:

1) Control expression

2) Assume a PRESENT state = 0000


3 & 4 ) Apply PRESENT state and find NEXT
state
Steps of design

1) Determine the desired


number of bits (FFs) and the
desired counting

2) Draw the state transition


diagram showing all possible
states, including those that
are not part of the desired
3) Use the state transition
diagram to set up a table
that lists all PRESENT
states and their NEXT
states.
4) Add a column for each JK input (or other
inputs). Indicate the level required at each J
and K in order to produce transition to the
NEXT state.
5) Implement the final expressions (obtained from the K
map).
6) Design the logic circuits needed to generate the levels
required at each J and K input..

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