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Sync

The document describes a Verilog module that generates three output signals (mcu_out, tx_out, rx_out) based on a clock input (clk_in). It utilizes counters to control the timing of the output signals, with specific high durations defined for each signal. The module includes logic for resetting the counters and adjusting the timing for the rx_out signal based on defined offsets.

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Vedant Borde
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3 views2 pages

Sync

The document describes a Verilog module that generates three output signals (mcu_out, tx_out, rx_out) based on a clock input (clk_in). It utilizes counters to control the timing of the output signals, with specific high durations defined for each signal. The module includes logic for resetting the counters and adjusting the timing for the rx_out signal based on defined offsets.

Uploaded by

Vedant Borde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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`timescale 1ns / 1ps

module m(
clk_in, rx_out,tx_out,mcu_out
);
input clk_in;

output reg mcu_out;


integer cnt_mcu=0;
integer div=5000; // 100KHz out
integer mcu_high=200; // 1 => 10ns, 2 => 20ns,...

////---TX------
output reg tx_out;
integer cnt_tx=0;
integer tx_high=30; // 1 => 10ns, 2 => 20ns,...

//---RX------
output reg rx_out;
integer cnt_rx=0;
//integer rx_high=6; // 1 => 10ns, 2 => 20ns,...

integer temp=80;//var*2ns=160ns --> starting offset


integer temp_2=180;//var*2ns=160ns + 200ns=360ns --> ending offset

//assign clk_in_reg=clk_in;
//---mcu_out---
always@(posedge clk_in) begin
cnt_mcu=cnt_mcu+1;

if(cnt_mcu<= mcu_high) begin


mcu_out=1;
end
else if(cnt_mcu>= (mcu_high+1) && cnt_mcu<=div) begin
mcu_out=0;
end

if(cnt_mcu==div) begin
cnt_mcu=0;
end
end

////---TX PULSE---
always@(posedge clk_in) begin
cnt_tx=cnt_tx+1;

if(cnt_tx<= tx_high) begin


tx_out=1;
end
else if(cnt_tx>= (tx_high+1) && cnt_tx<=div) begin
tx_out=0;
end

if(cnt_tx==div) begin
cnt_tx=0;
end
end

//--RX PULSE---
always@(posedge clk_in) begin
cnt_rx=cnt_rx+1;

if(cnt_rx<=temp || cnt_rx>temp_2) begin rx_out=0; end


if(cnt_rx>temp && cnt_rx<=temp_2) begin rx_out=1; end

if(cnt_rx==div) begin
cnt_rx=0; temp=temp+1;
if(temp==temp_2) temp=80;
end
end

endmodule

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