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Introduction 2019
General Digital System

So far we have seen Combinational Logic

The output(s) depends only on the current values of the input
variables
Here we will look at Sequential Logic circuits
Digital Systems The output(s) can depend on present and also past values of
the input and the output variables
FLIP-FLOPs Sequential circuits exist in one of a defined number of
states at any one time
They move "sequentially" through a defined sequence of
BK
TP.HCM
transitions from one state to the next
The output variables are used to describe the state of a
sequential circuit either directly or by deriving state variables
from them

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dce Synchronous and Asynchronous dce General flip-flop symbol and definition of its two dce
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Sequential Logic
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possible output states

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NAND Gate Latch

Synchronous The NAND gate latch or simply latch is a basic
The timing of all state transitions is controlled by a common FF.
clock
Changes in all variables occur simultaneously
The inputs are set and clear (reset)
Asynchronous The inputs are active low, that is, the output will
State transitions occur independently of any clock and normally change when the input is pulsed low.
dependent on the timing of transitions in the input variables
Changes in more than one output do not necessarily occur
When the latch is set
simultaneously
We now introduce the concept of memory. The flip-
Clock flop, abbreviated FF, is a key memory element.
When the latch is clear or reset
A clock signal is a square wave of fixed frequency The outputs of a flip flop are Q and
Often, transitions will occur on one of the edges of clock pulses Q is understood to be the normal output, is always
i.e. the rising edge or the falling edge
Q 0 and Q 1
the opposite.

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A NAND latch is an example of a bistable device 2019
Setting the NAND Flip-Flop 2019
Resetting the NAND Flip-Flop

NAND
001 NAND
011 001
101 011
110 101
110

NAND
001
011
101
110

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Function table of a NAND latch 2019

NAND Gate Latch 2019

Other Representations of a NAND latch

Summary of the NAND latch:

SET = RESET = 1. Normal resting state, outputs
remain in state prior to input.
SET = 0, RESET = 1. Q will go high and remain
high even if the SET input goes high.
SET = 1, RESET = 0. Q will go low and remain low
even if the RESET input goes high.
SET = RESET = 0. Output is unpredictable because
the latch is being set and reset at the same time.
Symbols indicate Q is set (high) when S is
low.

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Determine Q 2019 A example of NAND latch Application 2019

NOR Gate Latch

The NOR latch is similar to the NAND latch
except that the Q and outputs are reversed.
The SET and RESET inputs are active high, that
is, the output will change when the input is
NAND latch used to debounce a mechanical switch pulsed high.
In order to ensure that a FF begins operation at
a known level, a pulse may be applied to the
SET or RESET inputs when a device is powered
up.

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dce dce SR latch useful when temporary setting is used to dce

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NOR gate latch 2019 2019

Digital Pulses
activate switch
(a) NOR gate latch; (b) function table; (c) simplified block
symbol. The NAND FF is used to The transition from low to high on a positive
provide a bounce free switch pulse is called rise time (tr).
so that the 1 KHz pulse can
propagate to the output Rise time is measured between the 10% and 90%
without distortion. points on the leading edge of the voltage waveform.
The transition from high to low on a positive
pulse is called fall time (tf).
Determine Q for a NOR latch given the inputs below Fall time is measured between the 90% and 10%
points on the trailing edge of the voltage waveform.

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Rise and Fall times 2019
Rise and Fall times 2019

Clock Signals and Clocked Flip-Flops

Asynchronous system outputs can change
state at any time the input(s) change.
Synchronous system output can change state
only at a specific time in the clock cycle.
The clock signal is a rectangular pulse train or
square wave.
Positive going transition (PGT) when clock pulse
goes from 0 to 1.
Negative going transition (NGT) when clock pulse
Signal that activates an active-low output with: goes from 1 to 0.
tw = 50ns, tr =15ns, and tf = 10 ns.
Transitions are also called edges.
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Ideal Clock Signals 2019

Clock Signals and Clocked Flip-Flops

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Clocked Flip-Flops

Clocked FFs change state on one or the other

clock transitions. Some common characteristics:
Clock inputs are labeled CLK, CK, or CP.
A small triangle at the CLK input indicates that the
input is activated with a PGT.
A bubble and a triangle indicates that the CLK input is
activated with a NGT.
Control inputs have an effect on the output only at the
active clock transition (NGT or PGT). These are also
called synchronous control inputs.
The control inputs get the FF outputs ready to change,
but the change is not triggered until the CLK edge.

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Clock Signals and Clocked Flip-Flops

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Clocked S-R Flip-Flop 2019

Clocked SR Flip-Flop
The SET-RESET (or SET-CLEAR) FF will change states Clocked S-R flip-flop that triggers only on negative-going
Setup time (tS) is the minimum time interval before the
at the positive going or negative going clock edge. transitions.
active CLK transition that the control input must be
kept at the proper level.
Hold time (tH) is the time after the active CLK transition
during which the control input must kept at the proper
level.

Simplified version of
the internal circuitry
for an edge-
triggered S-R flip-
flop.

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2019 Clocked SR Flip-Flop 2019

Clocked J-K Flip-Flop 2019

Clocked JK Flip-Flop
Implementation of edge-detector circuits used in edge-
triggered flip-flops: (a) PGT; (b) NGT. The duration of the Operates like the S-R FF. J is set, K is clear.
CLK* pulses is typically 2 5 ns. When J and K are both high the output is
toggled from whatever state it is in to the
opposite state.
May be positive going or negative going clock
trigger.
Has the ability to do everything the S-C FF
does, plus operate in toggle mode.

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dce dce dce Edge-triggered D flip-flop

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Edge-triggered J-K flip-flop 2019

Clocked D Flip-Flop 2019

implementation from a J-K flip-flop

One data input.
The output changes to the value of the input at
either the positive going or negative going clock
trigger.

CLK* must be high for FF to change states. This condition only

occurs at the edge of a CLK transition.
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Parallel transfer of binary data using D flip-flops 2019

D Latch (Transparent Latch) 2019

D Latch
D latch: (a) structure; (b) function table; (c) logic symbol.
One data input.
The clock has been replaced by an
enable line.
The device is NOT edge triggered.
The output follows the input only when
EN is high.

EN must be high for D-Latch to change states.

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dce dce dce Clocked J-K flip-flop with asynchronous inputs
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D Latch 2019

Asynchronous Inputs 2019

Waveforms showing the two modes of operation of the

transparent D latch. Inputs that depend on the clock are synchronous.
Most clocked FFs have asynchronous inputs that
do not depend on the clock.
The labels PRE and CLR are used for
asynchronous inputs.
Active low asynchronous inputs will have a bar
over the labels and inversion bubbles.
If the asynchronous inputs are not used they will
be tied to their inactive state.

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dce Clocked J-K flip-flop with asynchronous inputs dce dce Flip Flop Propagation Delays
Flip-Flop Timing Considerations
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Important timing parameters:

Setup and hold times
Propagation delay: the time for a signal at the input to be
shown at the output.
Maximum clocking frequency: highest clock frequency that
will give a reliable output.
Clock pulse high and low times: minimum time that the clock
must be high before going low, and low before going high.
Asynchronous active pulse width: the minimum time
PRESET or CLEAR must be held for the FF to set or clear
reliably.
Clock transition times: maximum time for the clock
transitions, generally less than 50 ns for TTL, or 200 ns for
CMOS devices.
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Clock LOW and HIGH time Propagation Delay in Synchronous Circuits
Potential Timing Problems in FF Circuits
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When the output of one FF is connected to the

input of another FF and both devices are
triggered by the same clock, there is a potential
timing problem.
synchronous asynchronous The input (J2) to Q2 must
Propagation delay may cause unpredictable be held for tH after the
outputs. clock edge.
tw(L) is the minimum time that the CLK must remain low before it
The low hold time parameter of most FFs mean
goes high. This will occur only if tPHL
tw(H) is the minimum time that the CLK must remain high before it > tH.
goes low.
Usually, this is the case.
Similarly for asynchronous signals - but may have a different value
than the CLK signal.
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dce dce Asynchronous Signals may have Undesirable Side dce
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Flip-Flop Synchronization 2019 2019

Edge-triggered flip-flop can Synchronize
Effects
Circuit
Most systems are primarily synchronous The signal A has
in operation, in that changes depend on no effect until
the clock. negative edge of
clock.
Asynchronous and synchronous
operations are often combined.
The random nature of asynchronous
inputs can result in unpredictable results.
Asynchronous signal A can produce
partial pulses at X

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Asynchronous Data Transfer Operation Synchronous transfer of contents of register X into
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Data Storage and Transfer 2019 2019

register Y
Asynchronous transfers are controlled by PRE
and CLR inputs.
Transferring the bits of a register
simultaneously is a parallel transfer.
Transferring the bits of a register a bit at a time
is a serial transfer.

Uses PRE and CLR inputs to load data into FF

A = 1, EN =1, PRE = 0, sets B = 1

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A =0, EN =1, CLR = 0, sets B = 0 50 51

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Serial Data Transfer: Shift Registers

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Four-bit Shift Register
Serial Data Transfer: Shift Registers
When FFs are arranged as a shift register, bits Parallel transfers register contents are
will shift with each clock pulse. transferred simultaneously with a single clock
cycle.
FFs used as shift registers must have very low
Serial transfers register contents are
hold time parameters to perform predictably.
transferred one bit at a time, with a clock pulse
Modern FFs have tH values well within what is
for each bit.
required.
Serial transfers are slower, but the circuitry is
The direction of data shifts will depend on the
simpler. Parallel transfers are faster, but
circuit requirements and the design.
circuitry is more complex.
Serial and parallel are often combined to exploit
the benefits of each.

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Serial transfer from X register into Y register MOD-8 Asynchronous Counter
Frequency Division and Counting
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FFs are often used to divide a frequency as

illustrated in next slide. Here the output
frequency is 1/8th the input (clock) frequency.
The same circuit is also acting as a binary
counter. The outputs will count from 0002 to
1112
The number of states possible in a counter is
the modulus or MOD number. Next slide is a
MOD-8 (23) counter. If another FF is added it
would become a MOD-16 (24) counter.

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Example of Microprocessor Interfacing
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State Table & Diagram of MOD-8 Asynchronous Counter 2019

Microcomputer Application 2019

Microprocessor units (MPUs) which will be

studied later, perform many functions that
involve the use of registers for data transfer and
storage.
MPUs may send data to external registers for
many purposes, including:
Solenoid or relay control
Motor starting
Device positioning
Motor speed controls

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Schmitt-Trigger Response (two thresholds) Schmitt-Trigger Response (two thresholds)
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Schmitt-Trigger Devices 2019 2019

Not a FF but shows a memory characteristic

Accepts slow changing signals and produces a
signal that transitions quickly.
A Schmitt trigger device will not respond to an
input until it exceeds the positive or negative
going threshold.
There is a separation between the two
threshold levels. This means that the device

until the input goes to the opposite threshold.

Standard inverter response to slow noisy input, and
Standard inverter response to slow noisy input, and
(b) Schmitt-trigger response to slow noisy input.
Often used with noisy signals Often used with noisy signals
(b) Schmitt-trigger response to slow noisy input.
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One-shot (Monostable Multivibrator)

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One-shot 2019
Retriggerable and Nonretriggerable Operation

Changes from stable state to quasi-stable state

for a period of time determined by external
components (usually resistors and capacitors).
Nonretriggerable devices will trigger and return
to stable state.
Retriggerable devices can be triggered while in
the quasi-stable state to begin another pulse.
One shots are called monostable multivibrators
because they have only one stable state.
They are prone to triggering by noise so, tend to
be used in simple timing applications.

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dce Logic symbols for the 74121 nonretriggerable dce dce

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one-shot
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Clock Generator Circuits 2019

Clock Generator Circuit: Schmitt-trigger Oscillator

Schmitt-trigger oscillator using a 7414 INVERTER. A 7413

FFs have two stable states, so are considered
Schmitt-trigger NAND may also be used.
bistable multivibrators.
One shots have one stable state and are
considered monostable multivibrators.
Astable or free-running multivibrators switch back
and forth between two unstable states. This makes
it useful for generating clock signals for
synchronous circuits.
Crystal control may be used if a very stable clock is
needed. Crystal control is used in microprocessor
based systems and microcomputers where
Circuit will not oscillate if R is not kept within these limits.
accurate timing intervals are essential.

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2019 Clock Generator Circuit: 555 Timer
555 timer IC used astable multivibrator.

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