Fabecation Techniques and MOSFET Physical Design (Module 5) B59 Module 5 Fabrication Techniques and MOSFET Physical Design es; MATERIAL PREPARATION Ques 1) | What do you mean by material preparation? Also write the basic steps, which are involved in the material preparation proc Ans: Material Preparation Material preparation involves the basic steps involved in the fabrication of device. The integrated circuits are fabricated with silicon. To fabricate devices, silicon must be extremely pure and in crystalline form without any defects. An impurity of the order of a ppb (parts per billion) only is allowed. Silicon is the most important semiconductor material for electronic industry. It is found abundantly in nature in the fori of silica and silicate (sand), ‘Steps Involved in the Material Preparation Process The various steps involved in the material preparation process are as follows: 1). Purification of silicon, 2) Crystal growth, 3) Crystal slicing, 4), Wafer preparation, and 5) Wafer processing. Ques 2) Define purification of silicon. Also write the chemical reactions, which are carried out at the time of silicon purification. or How electronic grade silicon is prepared from raw RO? eae (2019 105) Ans: Purification of Silicon Silicon is the eighth most common element in the universe by mass, but very rarely occurs as the pure free element in tuture. It is most widely distributed in dusts, sands, Blanetoids, and planets as various forms of silicon dioxide (slica) or'silieates. Silicon is solid at room temperature, with relatively high melting and boiling points of 1414 and 3265 °C respectively Metaurgicsl Grade Silicon (MGS) i obtained by eduction of quartzite (a crystalline form of SiO; available the form of rock) in a carbon are furnace The main raw material for the growth of single silicon “Ystal is Electronic Grade Silicon (EGS), which 1s Polycrystalline material of high purity. ‘The major Impurities in EGS are boron, carbon and residual donors. To produce EGS, first Metallurgical Grade Silicon (MGS) 's produced in a submerged are furnace, which is charged with quartzite and carbon, The overall reaction for producing MGS is, SiC (solid) + SiO, (solid) ~> Si liquid) + SiO (gas) + CO (gas) ‘The drawn MGS is solidified ata purity of 98%. ‘The next step is to crush the silicon and then react it with anhydrous hydrogen chloride to form trichlorsilane (SiHC1). The reaction is, Si (solid) + 3HCI (gas) —> SiHCI, (gas) + Hz (gas) + heat ‘The reaction takes place in a fluidized bed at a temperature of 300°C to produce trichlorsilane in the presence of catalyst. Trichlorsilane is liquid at room temperature and it has many unwanted chlorides which can be removed by fractional distillation, ‘The EGS is prepared from purified SiHCls in a chemical vapour deposition (CVD) process. The chemical reaction for EGS production is, 2SiHCI, (gas) + 2H; (eas) —> 2Si (solid) + 6HCI (gas) This reaction is also called hydrogen reduction process. ‘An alternative method for producing EGS is pyrolysis of silane, which has lower production cost and less harmful reaction by-product. In this process, CVD reactor is operated at 900°C and supplied with silane instead of trichlorsil:ae. The pyrolysis reaction is, SiFL, (gas) + Heat ~ Si (solid) + 2H, (gas) Ques 3) List the advantages of SiO. Or Write advantages and uses of SiO, Ans; Advantages of SiO; The major advantage of Si is the existence of a native ‘oxide (Silicon dioxide, SiO), which is used as an insulator in electronic devices. Silicon dioxide can easily beB-60 incorporated onto silicon circuits, and such layers are adherent to the underlying silicon. SiO, is not only a good insulator (with a band gap of 8.9 eV), but the Si-SiO: Interface can be easily engineered to have excellent clectrical properties, most importantly low density of interface states, Tt possesses a higher hole mobility compared to GaAs (500 versus 400 em’V"'s''). This high mobility allows the fabrication of higher-speed P-channel field effect transistors, which are required for CMOS logic. Because they lack a fast CMOS structure, GaAs circuits must use logic styles which have much higher power consumption; this has made GaAs logic circuits unable to compete with silicon logic circuits. For manufacturing solar cells, silicon has relatively low absorptivity for the sunlight meaning about 100 micrometers of Si is needed to absorb most sunlight. Uses of Silicon Dioxide 1) In IC fabrication techniques like etching, diffusion, ion implantation, etc. 2) In Dielectrics for the electronic devices. 3) As an Ultrathin layer for MOS and CMOS devices This has infact increased the wide popularity of CMOS devices with high input impedance 4) In 3D devices in MEMs technology. Ques 4) Define crystal growth. Also list the various processes used for crystal growth. Ans: Crystal Growth The crystal growth process is done to convert polycrystalline silicon to single crystalline silicon. Crystallisation takes place if molten silicon is allowed to solidify to a seed crystal (seed crystal is highly pure single crystalline silicon which is used as the stating material for crystal growth). ‘The silicon crystal growth is a liquid-solid mono- component growth system. ‘The speed of the growth is determined by the number of sites on the face of the crystal and the specifics of the heat transfer at the interface. Some of the most important growth parameters fof the crystal are the growth rate or growth velocity of the crystal, and the instantaneous solidification rate. Interface Boundary | layer (liquid) Solid Melt (Liquid) (Crystal) ai: Growth Tw “Temperature BL Melt (Liquid) Impurity Atoms *siticon Atoms MON Distance Figure $.1: Silicon Crystal Growth p-tech, Sith Semester TP Solved Series (VLSI Circuit Despn xy ‘The temperature fluctuations cause a huge difference in the rates near the interface. The growth rate can be greg than or even less than the pull rate at a given time figure 5.1 shows the transport process and temperayy | gradients involved. rrocesses Used for Crystal Growth types of processes are used, which are a follows; 1). Czochralski growth (CZ process), and 2) Float zone process (FZ process). Ques 5) Explain Czochralski crystal growth (cz process) process used for silicon crystal growth, Al Write the advantages and disadvantages of CZ proces, or Illustrate with diagram the principle of crystal growth by Czochralzki method. on (2018 (05), With a neat sketch, explain Czochralski crystal growth mechanism. (2021 [08) ‘Ans: Czochralski Crystal Growth (CZ Process) Proces: Crystal growth typically involves a phase change from 3 solid, liquid, or gas phase to a crystalline solid phase. The Czochralski (CZ) process, which accounts for 80% to 90% of worldwide silicon consumption, consists of dipping « small single crystal seed into molten silicon and slowly withdrawing the seed while rotating it simultaneously, Following figure 5.2 is a schematic of a Czochralski crystal growing apparatus. The silicon crystal manufactured in a cylinder, which is known as ingot « boule. In modem technology, the boule can reach ¢ diameter of over 300mm and length of 1-2m long. APull Coated silica | enclosure BF power Gas Figure 5.2: CZ Crystal Growth ‘The crucible is usuall fused silica Ii process of Cam, ire following steps are used it Arrangement ly made of quartz or graphite With! ski (CZ) proc 1) A fused ssilica crucible is fy ica crucible is loaded with a charge undoped EGS together with a precise amoutt 4 diluted silicon alloy ne The gases. insi evacuated, "4 the growth chamber are 3) The growth cham Bas (0 inhib OEE iS then back-filed with an iFabrication Techniques and MOSFET Physical Design (Module 5) 4). The silicon charge inside the chamber is then melted (Si melting point = 1421 deg C), 5) A slim seed of crystal silicon (5 mm diameter and 100-300 mm long) with precise orientation tolerances, is introduced into the molten silicon, 6) The seed crystal is then withdrawn at a very controlled rate, The seed crystal and the crucible are rotated in opposite directions while this withdrawal process occurs, Advantages of CZ Process ‘The various advantages of CZ. process are as follows: 1) An appropriate thermal field is easy to establish for various crystals with a wider span of materials and ‘melting points than any other melt-growth method. 2) Where CZ is used, crystals grow from the free surface of the melt without contacting with crucible. 3) In CZ, a neck process can be easily employed to liminate dislocations originating from the seed and thermal shock. Disadvantages of CZ Process The various disadvantages of CZ process are as follows. 1) The CZ furnace is usually constructed of either Al,O, or stabilised ZrO; ceramics, which contact directly with the crucible, This configuration leads to a weakly oxidizing atmosphere in the furnace. Such conditions ‘may result in the oxidation of crucible and introduce pollutants into the met. 2) In CZ growth, appreciable temperature gradients are usually needed to control the diameter of the growing crystal. Ques 6) What do you mean by wafer preparation? Also write the various steps involved in the process of wafer preparation. ‘Ans: Wafer Preparation After electronic grade silicon (EGS) is obtained, it is still in the form of polycrystalline which is unsuitable to be made into an IC chip. ‘Therefore, in order to make it suitable, EGS must be converted into a single crystal material known as mono-crystalline. This is done by melting EGS in a furnace and recrystallizing. ‘Steps Used in Wafer Preparation The steps, which are used in the wafer preparation, are as follows: 1) Diameter Grinding: After the CZ process, the ingot undergoes diameter grinding to smoothen the surface and to obtain a uniform diameter. The figure below shows the ingot before and after diameter grinding process. Before Aer o's B61 2) Wafer Flat Grinding: Flat grinding is done as a visual frame of reference for wafers with diameters less than 6 inches. Larger wafers will have a notch cut into them instead to reduce wastage. It is used for alignment with the first mask. Flat grinding also helps to indicate the orientation and conductivity type (P or N) of the wafer. The figure below show the water flat grinding. ‘Ungrinded Wafer Grinded Wafer UU 3) Wafer Slicing: A diamond coated, inside-diameter saw is used to slice the ingot into wafers. The saw is also known as an Annular Saw. The saw is designed to be rigid so that it is less likely to wobble during the sawing action so as to reduce wastage. The saw is also extremely thin to reduce further wastage. 4) Wafer Lapping/Polishing: The waters are being lapped using a coarse abrasive (alumina) suspended in a solvent. Then, Chemical Mechanical Polishing will remove damage caused by lapping, making the wafer very shiny like a mirror. 5) Edge-Grinding: By edge-grinding, it helps to reduce edge-chippings which can result in breakage or dislocations in the cirouit. The figure below shows the edge grinding process. The one at the top is before the edge-grinding and the one at bottom is after the edge-grinding [eeeeseeceseeeees] aD) 6) Backside Processing: In most of the cases the back of the wafer is left unpolished This is because normally only the front part of the wafer will be used for making ICs. However, in some cases (uncommon). the backside of the wafer may be used as. well. Special processes known as Backside Guttering are used to induce crystalline damage on the backside of the wafer on purpose. These damages on. the backside of the wafer cause dislocations which act as traps for Mobile Ionic Contaminants (MIC). [t is highly important for these MICs to be tapped otherwise it can interfere and hinder device ‘operations THERMAL OXIDATION Ques 7) Explain the process of thermal oxidation in growth mechanism. Also explain types of oxidation Process. Or With schematic diagram and chemical reactions involved, illustrate wet and dry oxidation processes (2018 (05) iieneteniiiniieessB62 Or Mlustrate the dry and wet oxidation technique used in IC fabrication with schematic diagram. (2019 [10]) Or diagram and chemical reactions illustrate wet and dry oxidation processes. (2018 [05]) With schematic involved, Ans: Thermal Oxidation Thermal oxidation is the Process of growing a thin layer of Oxide on the surface of a wafer Or Thermal oxidation (oxidation for short) is the process by Which a layer of Silicon Dioxide (SiO,) is formed on the Surface of a silicon wafer with a specific thickness The figure 5.3 illustrates the oxidation process showing the before and after stages of oxidation process. During the course of the oxidation process, oxygen or Water molecules diffuse through the surface oxide into the silicon substrate, and the Si-SiO, interface migrates into the silicon (Figure 5.3). Thermal oxidation of silicon Tesults in a random three-dimensional network of silicon dioxide constructed from tetrahedral cells. Since the Volume expands, the external SiO, surface is not coplanar with the original silicon surface. For the growth of an oxide of thickness d, a layer of silicon equal to a thickness of 0.44d is consumed. Os flow tS | Silicon Figure 5.3: Mlustration of the Oxidation Process: (a) Before Oxidation (b) After Oxidation ‘Types of Oxidation Processes There are two types of oxidation processes are used: 1) Wet Oxidation: Wet oxidation is so called because the water vapour is used as the oxidising atmosphere during the oxidation process. In wet oxidation, the required temperature is usually less than that of dry oxidation and is between 900°C and 1000°C. Figure 5.4 shows the growth curve for wet oxidation, ‘The reaction equation is given as follows: Si + 2H;O SiO, + 2H; ey ‘Steam Oxidation 10 10 10 10 Oxidation Time (Min) Figure 5.4: Growth Curves for Pyrogenic Steam Oxidation B.Tech, Sixth Sem ester TP Soved Series (VLSI Cite Des ee dation is so named jg. | 2) Dry Oxidation: Dry oxidation | 2) Oy Gaising atmosphere COMAIDS PUTE Oxygeq | th couse f oxidation 1 ty ONO, he yg temperature is between 900°C and 1200%C nee ‘an acceptable growth rate, achieve Figure 5.5 shows the growth curve for dry oxiggy | The reaction equation is as follows Si + 0; > SiO> 0; Oxidation ‘Thickness (A) VO NOG. 10. 10 Oxidation Time Figure 5.5: Growth Curves for Dry Oxidation. ., no HC Present; -~-, 4.5% HCI Ques 8) Phosphorous is implanted in a p-type silica sample with a uniform doping concentration of Sxi0! atoms per cm’. If the beam current density is 254 per cm? and the implantation time is 8 minute, calculate the implantation dose and peak impuriy concentration, Assume ARp = 0.3m. (2019 05), ‘Ans: Given that, 10" 00 0. 3 1 ' 3 o Depth Gum) for pinblementation Proftte for Boron in Silicon °F Different Values of ton-Beam Energy Implantation dose Q, = Jt 5x 10" cm? Peak impurity Concentration Q Fabrication Techniques and MOSFET Pt Ques 9) A SiO; layer is grown 1000°C for 40 minutes followe oxidation at 1200°C. Determine | oxide layer formed. B = 0.29, § oxidation at 100°C, B = 0.045 = 0.027 for dry oxidation at 1200° Ans: Thickness of oxide grown by w: r 1 yea 40 minutes = 10/60 hr = 0.667 hr, 1 a 0.228]] 0.667 | _ 2 (0.228) 40.29 Time required to grow 0.340um | oxidation at 1200°C is: We tos ta +e BO B/A_ B=0.045, B/A=L12, 0 t (0.340)7 | 0.340 ———-0.027 =2.841 0.045 * 1.12 Thickness of oxide layer obtained in ( tog =VBOHD Co Alay << ta for k = ¥0.045(3.84 + 0.027) = 0.417 um Ques 10) A silicon crystal is t Czochralski process and is to con atoms/cm’, Given the segregation c in silicon is 0.8, Atomic weight 10.81g/mole, density of silicon 2.229 number is 6.023x10™ atoms/mole. initial concentration of Boron in th the required doping density. (b) If th silicon in the crucible is 20kg, ho Boron should be added to obtain the Ans: a) 5x 10!°atoms/em 5x10" _ 6.>5x10!ato k, 08 b) Weight of silicon = 50x a 8 weight Volume of silicon = 5 _ 50x10" 233 2.146x10%em' —————— —ind MOSFET Physical Design (Module 5) fatrication Techniques ai 9) A SiO; layer is grown by wet oxidation at for 40 minutes followed by 1 hour dry a at 1200°C. Determine the thickness of the ove layer formed. B = 0.29, B/A = 1.27 for wet oxgation at 1000°C, B = 0.045, B/A = 1.12 and 70.027 for dry oxidation at 1200 ns: Thickness of oxide grown by wet oxidation \ oe osidation {40 minutes = 10/60 hr = 0.667 hr, t =0 1 2 0.667 (0.228)? 4x0.29 0.228 -1}=0.340um Time required to grow 0.340um thick oxide by dry oxidation at 1200°C is: Wong tee tof yt g BB/A B=0085, B/A=1.12, ¢=0.027 2 OS" 2380 bag) oe te 0.045” 1.12 Thickness of oxide layer obtained in (2.84 +1) br is =YBQE+1) (+ Atos << tax for long oxidation times) = /0.045(3.84+0.027) = 0.4174m. Ques 10) A silicon crystal is to be grown by Czochralski process and is to contain 5x10" boron ‘atoms/cm’. Given the segregation constant kp for Boron i silicon is 0.8, Atomic weight of boron equals 1081g/mole, density of silicon 2.22g/em’ and Avogadro tumber is 6.023x10” atoms/mole. (a) Determine the itial concentration of Boron in the melt to produce the required doping density. (b) If the initial amount of ‘ilicon in the crucible is 20kg, how many grams of Soron should be added to obtain the same doping? (2018 (05) Ans; 7 Y ett Ge 5x10! atoms/cm’, k, = 0.8 N10" 0.8 = 6.2510! atoms/cm’ me of silicon = density 146%10*em* B63 Neglecting the change in volume on adding boron atoms Name of boron atoms = Number of boron atoms/cm? x Volume of Si = 6.25 x 10" 2.146 x 10° = 13.41 x 10" weight/mole atoms/mole Weight of boron added = * Total number of atoms 10.81 = Sonate Ala 10” = 2.40 x 107g = 2.40 mg Ques 11) A SiO, layer is grown by wet oxidation at 1000°C for 40 minutes followed by dry oxidation for 1 hour at 1200°C. Determine the thickness of the oxide layer formed. For wet oxidation at 100°C, B =0.29, BJ/A = 1.27 and for dry oxidation at 1200°C, B = 0.045, BIA = 1.120, 7 = 0.027. (2018 [05]) Ans: Thickness of oxide grown by wet oxidation, 1 tet ya A?/4B 27 2. A=0.228 }0/60hr = 0.667hr, t = 0 | “acs | -1}=0.340um Time required to grow 0.340 um thick oxide by dry oxidation at 1200°C is, ene ies foxy tox _ BBA B= 0.045, B/A = 112, t= 0.027 = O30 00 6.027 = 2.84hr 0.045 1.12 ‘Thickness of oxide layer obtained in (2.84 + 1) hris, t, = BOD GAL, <Y mechanism are Gold, Copper and Ni nee 7 Fabrication Techniques and MOS! Since these impurity ato cannot replace the host at with silicon. Each of t contain an impurity atom. diffusion of interstitial at diffusion of lattice atoms. to form a vacancy. The | substitutional diffusion mi Ampunty atom un? © fan interstitial site Figu Ques 15) Define ion implan advantages of the ion impla diffusion technique. Also giv Ans: Ion Implantation Tech: Ton implantation is the dom dopant impurities into er performed with an electric ionized atoms or molecul penetrate into the target mat because of interactions with d Ton implantation is able to cc and dose of the dopants ia sil depth depends on the kinetic proportional to the electric fi controlled by varying the ior ion implantation the crystal implies worse electrical props Another problem is. that electrically inactive, becat interstitial sites. Therefore af process step is necessary whi and activates the dopants. A typical ion-implantation 5) 5.10 below: ‘Acceleration Revolv' vertu Analyser ‘magnet on beam Source vacuum ton source jon source. power 0 a ‘Advantages of fon Imp Diffusion Technique The advantages of the oe diffusion technique are as f° 1) Short process _ times. reproducibility of the Pr ————fabrication Techniques and MOSFET Physical Design (Module 5) Since these impurity atoms are smaller, hence they cannot replace the host atom and form covalent bonds with silicon. Each of the voids is big enough to contain an impurity atom. The energy required for the diffusion of interstitial atoms is lower than those for diffusion of lattice atoms. Since no energy is required to form a vacancy. The figure 5.9 below shows the substitutional diffusion mechanism. 20 Sistom—so ° ogo 0 ere Noid o fo og Impurity? of Oo Impurity atom in? — 0 %% ‘an interstiuial site iO Geo (a) o Figure 5.9 Ques 15) Define ion implantation technique. Write the advantages of the ion implantation technique over the diffusion technique. Also give its disadvantages Ans: Ion Implantation Technique Jon implantation is the dominant technique to introduce dopant impurities into crystalline silicon. This is performed with an electric field which accelerates the ionized atoms or molecules so that these particles penetrate into the target material until they come to rest because of interactions with the silicon atoms. Jon implantation is able to control exactly the distribution and dose of the dopants in silicon, because the penetration depth depends on the kinetic energy of the ions which is proportional to the electric field. The dopant dose can be controlled by varying the ion source. Unfortunately, after jon implantation the crystal structure is damaged, which implies worse electrical properties. Another problem is that the implanted dopants are electrically inactive, because they are situated on interstitial sites. Therefore after ion implantation a thermal Process step is necessary which repairs the crystal damage and activates the dopants. A typical ion-implantation system is shown in the figure 5.10 below: Revolving Aecsention YAM Ware zh ube plates (target position) ‘_me zum porns Fasy toa ese Owen cane Wales icaiues Er saees feadat power only Figure 5.10 Advantages of fon Implantation Technique over Diffusion Technique ‘The advantages of the ion implantation technique over the diffusion technique are as follows: 1) "Short process. times, good homogeneity and reproducibility of the profiles. (6 ieee aia eS ae B-65 2) Exact control of the amount of implanted ions by ‘measuring the current. This is of particular importance for low concentrations, e.g., to adjust the threshold voltage of MOS transistors Relatively low temperatures during the process. 3) 4) Various materials can be used for masking, for example, oxide, nitride, metals, and resist. 5) Implantation through thin layers, for example, SiO, is possible, 6) Low penetration depth of the implanted ions. This allows modification of thin areas near the surface with high concentration gradients. 7) Sequences of implantation steps with different energies and doses allow optimization of the dopant profiles. Disadvantages of the fon Implantation Technique The disadvantages of the ion implantation technique are as follows: 1) The implanted ions cause damage in the substrate, 2) The change of material properties is restricted to the substrate domains close to the surface 3) Additional effects during or after implantation, e.g., channeling or diffusion, make it difficult to achieve very shallow profiles and to theoretically predict the exact profile shapes. Ques 16) Explain the range theory in ion implantation. Also explain ion stopping and range distribution phenomena in ion implantation. or With the help of mathematical equations, explain the distribution of impurities in a semiconductor in ion implantation process. (2019 [10) Ans: Range Theory Range theory covers the basic theory of ion implantation ~ the physics of ion collisions, its application to calculating range distributions, the effect of a crystal lattice, damage, and recoil distributions. The basic phenome! theory, are as follows 1) Ton Stopping: As each implanted ion impinges onto the target, it undergoes a series of collisions with the host atoms until it finally stops at some depth, as depicted in figure 5.11 which are measured in range ‘A second component of scattering comes from inelastic collisions with electrons in the target. The total stopping power S of the target, defined by the energy loss (B) per unit path length (x) of the ion, is the sum of these two terms, eeB.Tech, Sixth Semester TP Solved Series (VLSI Circuit Design) KTy B-66 Depth (Ay 1200 -800 400 0 400 800 1200 Lateral Position (A) Figure 5.11: Monte Carlo Calculation of 128 Ion Trajectories for 50keV Boron Figure 5.12 shows the relative distribution to S of each of the terms over a wide energy range. Energies typical for ion implantation, 10 to 200 keV, fall at the far left of the figure, a region dominated by nuclear stopping. Low Intermediate + High energies | energies | energies * Electronic! al g st ' boc! 8 epee + region) g : 2 E £ a Voz” Figure 5.12: Nuclear and electronic components of the ion stopping power as a function of ion velocity. The quantity Vs is the Bohr on Velocity velocity, and Z, is the ion atomic number. Amegh Nuclear stopping is caused by a collision between two atoms, and can be described by classical kinematics. If the atoms were bare nuclei, then at a separation r, the columbic potential between them would be: v.(r) = 442 aye(L) 4me.r Where, z; and z, are the atomic number of the implanted and target atoms, respectively, & is the permittivity, and q is the electronic charge. In reality, electrons screen the nuclear charge and a screening function, {,(r), must be included such that; ‘ Vin = VN) see) Given the interaction potential, the equations of motion of atoms can be integrated to yield the scattering angle for any incident ion trajectory ‘Working in the center-of-mass frame, the result is, 4M\M +, » B) 2 Where, 5 T = Energy lost by the incoming ion E = Energy of the ion, @ the scattering angle M, and M, = Atomic mass numbers of the ion ang target atom The rate of energy loss to nuclear collisions per unjt path length can be calculated by summing the energy loss multiplied by the probability of that collision occurring. If the maximum possible energy transfer jn a collision is Tmax and there are N target atoms per unit volume, then Tage s, -(2} =N [Téo wld) ‘nuclear dx. 0 Where, do is the differential cross section. Nuclear stopping is elastic, and so energy lost by the incoming jon is transferred to the target atom that is subsequently recoiled away from its lattice site, thus creating a damage or defect site. Range Distribution: Each implanted ion traverses a random path as it penetrates the target, losing energy Y by nuclear and electronic stopping. Since implantation oe tal p stopy doses are usually higher than 10’? ions/cm’, ion trajectories can be predicted employing statistical Ques 17) Pho sample with a atoms per cm per cm? and calculate the im means, The average total path length is called the range R, which is composed of both lateral and vertical motions. The average depth of the implanted ions is called the projected range R,, and the distribution of ) Also find the pea the implanted ions about that depth can be approximated as Gaussian with a standard deviation Ans: J = 2.5 wAser 6, (or AR,). = 8 minutes : = 10°F Boron | The lateral motion of the ions leads to a lateral BE Gaussian distribution with a standard deviationa,. These parameters are illustrated schematically in g figure 5.13. Far from the mask edge, the lateral § motion can be ignored and n(x), the ion concentration 5 at depth x, can be written as: 2” x-R)? E aca. 7 . “| eeton 210 Where : aug : oo 04 1 = Peak concentration R, = Projected ran bi the Xan y ge, and 0) is the standard deviation See Silicon for different Vs If the total implanted dose is 9, imegrating equation : Im (S) gives an expression for the peak concentration Ne: It n= Plantation Dose Q, = (6) q a 2.5 x10 °x8x 60 _ 45x eral, an arbitrary distribu can be 16x10" stribution = can 16x10 cued im terms of its moments. The normalized Peak impunty concentrauon moment of an ion distribution is the project impunity © i ; 75x10 Nea =—4, oaxlo tx ova Rp. The second moment is the standard Beet Se The third moment is the skewness % whereas the fourth moment, kurtosis, is designated B.ion Techniques and MOSFET Physical Design (Module 5) vualitatively. skewness is a measure of the oMninetry of the distribution. Positive skewness ants the peak of the distribution closer to the surface jan Rp. Kurtosis is an indication of how flat the top ‘ya distribution is. A true Gaussian distribution has a Stewness of O and a kurtosis of 3 Semiconductor} a beam Figure 5.13: Schematic Views ofthe lon Range. (a) The ‘otal pathlength R is longer than the projected Rp. (b) The stopped atom distribution are is dimensional Gaussian. (Ques 17) Phosphorus is implanted in a p-type silicon ‘ample with a uniform doping concentration of 5 x 10" atoms per cm’, If the beam current density is 2.5pA per cm? and the implantation time is 8 minutes, calculate the implantation dose. Assume ARy = 0.3m. Abo find the peak impurity concentration. 5x 10°A/em* x 60 seconds Boron in silicon Br gy Ey OR aOa OS ke, hee a0) Depth (um) Figure §.14: Limplantation Profile for Boron in Silican for different Values of fon-Beam Energy ation Dose Q. 25x10 60 ~ 7.5 x 10" em® lox1o” Peat impurity concentration rt, - 2. 75x10" _ 29. 9710%em™ 03x10 x Von aR, Vix B67 Ques 18) Define the term ‘Epitaxy’. Also explain the types of epitaxy. Ans: Epitaxy Epitaxy is a Greek word, which means, This leads to the meaning that it is an arrangement of atoms (arranging themselves in a crystal form) upon a crystal substrate, So thatthe resulting added layer structure is an exact extension of the substrate crystal structure Epitaxy is a process used to grow a thin crystalline layer on a crystalline substrate ‘Types of Epitaxy ‘There are basically two types of epitaxy: 1) Homo Epi In this, the same material that of substrate is grown. For example, growing Si on silicon substrate. 2) Hetero Epitaxy: In this, a different layer is grown over the substrate. For example, growing AIGaAs on GaAs. In this type, the material grown should be lattice match between the substrate and the grown material so that the crystal does not have strain. Thermal coefficient of expansion of both materials should match. Ques 19) Explain vapour-phase epitaxy process in detail. Also explain the various types of reactors used in vapour-phase epitaxy process. Ans: Vapour-Phase Epitaxy (VPE) ‘The Vapor Phase Epitaxy (VPE) is a technique widely used in the microelectronics industry for the growth of thin films on silicon substrate. Its main advantages are the ability to grow epitaxial layers with very good quality and with high growth rates (above the m/min) ‘The CVD (Chemical Vapour Deposition) of single crystal silicon is usually performed in a reactor consisting of a quartz reaction chamber into which a susceptor is placed The susceplor provides physical support for the substrate wafers and provides a more uniform thermal environment. Silicon is most common growth from silicon tetrachloride in hydrogen at approximately 1200°C SiClug) + 2Flag) © Si, + 4HCI, a This reaction is reversible, and the growth rate depends strongly upon the proportion of the two source gases Growth rates above 2 micrometres per minute produce polycrystalline silicon, and negative srowth rates (etching) may occur if too mueh hydrogen chloride by product is present. An additional etching reaction competes with the deposition reaction: SiClip) + Sig) SIClyy 2azion Techniques and MOSFET Physical Design (Module 5) pee Liquid = Nitrogen ‘cooled shrouds twin ctl et Main shutter Rotating substrate Fond Hock uorecent ‘Seren To variable speed nator sd watt tener surety Pagore 8.18 Safety Considerations Typical reactors weight 2000 kg and occupy 2m’ or more af floor space. Several safety considerations must be addressed in the eperation of the reactor. 1) The reactor itself is usually designed with sufficient interlocks (0 prevent accidents. However, the user must remove and treat reaction by-products safely and arrange for proper delivery of process gases 10 the reactor. 2), The explosion and fire potential of hydroge: 3) The corrosive nature of HCI 4) The highly toxic nature of the doping and deposition ‘eases. 5) Arsine is instantly lethal if a concentration of 250 ppm is inhaled, and prolonged exposure at lower levels (35 ppm) can also be lethal, depending on the length of exposure, 6) Environmental considerations usually require a Water-mist fume serubber to remove most of the unreacted and reaction products from the carrier- Bas stream, Advantages of MBE Process 0) MBE is low temperature process ‘advantageous for VLSI 2) While preparing thin layers using MBE process, auto loping and auto diffusion both are minimised 4 The MBE process can be used for complicated doping profiles as it regulates the a of dopant 4) As MBE process is based on the evaporaion of silicon and the dopants, hence no chemical reactions are involved in it. ) For MBE process safety precautions are not required extensively ax compared to those required in CVE process which is ratings un Sunple exchange B09 Disadvantages of MBE Process 1) For overall perfect and pure film, it is necessary to maintain a very low pressure of the order of 10 T,., which is slightly difficult This process is very expensive as compared to CVD. process, 3) The growth rate in MBE process is 0.01 — 0.3grvmin which is very small compared to the growth rate of Hm/min in CVD process OGRAPHY Ques 21) Discuss about the process of lithography Also explain the steps involved in the process of lithography. Ans: Lithography Lithography is a process that is used. for device fabrication, a system that transters specific patterns from photomask or reticle to the surface of a substrate, This lechnology has been helping the semiconductor industry as it plays an important role in the production of electronic device components such as integrated circuits Steps in lithography Lithography involves a number of steps and these are the following, 1) Imposition of Structure on a Beam: The lithographer imposes structure on a beam of light, by passing it through a ‘mask’ and this is followed by projecting the image onto a silicon wafer covered with a thin layer of material known ay resist 2) Chemical ‘Transformation; The resist covering the substrate undergoes a chemical transformation when exposed to light; a process that modifies the solubility of the material and this modification makes the latent pattern image into a patterned chemical stencil, after the application of an appropriate solvent 3) Deposition: This can be a process where the substrate is put inside a reactor, to which a number of gases i supplied, which create a chemical reaction, producing @ solid material with condenses on all the surfaces inside the reactor 4) Etching: A process that chemically removes layers from the surface of a substrate; this process is needed to patiern deposited layers — removing the unwanted, leaving behind only the specific traces oF patterns Ques 22) What is ph photolithographic sequi disadvantages, an lithography? Also explain the Also give the udvantages, applications of photolithography. Or Wiaat Is photolithography? With steps involved in pl houraphy proce dingram illustrate the 2018 (05) Ans: Photolithography It is @ process that uses a light-sensitive material called photoresist Wo create a specific pattern on the surface of aB-70 substrate Many steps inthe fabrication process of semiconductor devices should only affect specific sections or areas of a substrate and this is realised through the help of photolithography. Photolithography Sequence The photolithography sequence are as follows: 1) Photoresist Application (Spinning): A drop of light- sensitive liquid called photoresist is applied to the center of the oxidized silicon wafer that is held down by a vacuum chuck. The wafer is then accelerated rapidly to a rotational velocity in the range 3000 to 7000 RPM for some 30 to 60 seconds. This action spreads the solution in a thin, nearly uniform coat and spins off the excess liquid. 2) Prebake: The silicon wafers coated with photoresist are now put into an oven at about 80°C far about 30 te 60 minutes to drive off solvents in the photoresist and to harden it into a semisolid film. 3) Alignment and Exposure: The coated wafer, as above, is now placed in an apparatus called a mask aligner in very close proximity (about 25 to 125 micro meters) to a photomask. The relative positions of the wafer and the photomasks are adjusted such that the photomask is correctly lined up with reference marks Gr a pre-existing pattern on the wafer. | ‘The photomask is a glass plate, typically about 125 yumm square and about 2 mm thick. The photomask has 1 photographic emulsion or thin film metal (generally ae mium) pattern on one side. The pattern has clear and opaque areas. The alignment of the photomask to the wafer is often required to be accurate to within fess than 1 micro meter, and in some cases 1 within 0.5 micro meters. After proper alignment has been achieved, the ‘wafer is brought into: direct contact with the photomask. 4) Development: Two types of photoresist exist- negative photoresist and positive phowwrcsi Inthe present Fescription negative photoresist 1§ used in which the ‘areas of the photoresist ‘that are exposed the ultraviolet eration become polymerized. The polymerization HOP snereases the length of the orpant chain Prooules thet make up the photorees “This makes the resist tougher and makes it essentially insoluble tn the developer solution. The resisting photoresist pattern after se jevelopment process Will eslCT be a replication Uwe the photomask pattem, with the clear areas on the photomask ‘corresponding to the arcas where the Photoresist remains on the wafers. An opposite type of itive photoresist. Postbake: wand ninsing the wafers are usually ‘oven at a temperature of about pout 30 to 60 minutes (0 toughen further 10°C for al “ jst on the wafer the remaining Fes! ‘This is to make it adhere betisr 1 the wafer and to tnake it more resistant 10 the hydrofluoric acid (HP) imtion used for etching of the silicon dioxide, —_ ~~ = B Tech, Sixth Semester TP Solved Series (VLSI Circuit Design, y Ry, 5) Oxide Etching: The remaining resist ts hardeneg fects as a convenient mask through Which the ot layer can be etched away 10 expose ary - semiconductor underneath. These exposed awit ready for impurity diffusion “— Advantages of Photolithography ‘The advantages of photolithography are as follows: 1) Photolithography can etch a pattern into an integra circuit with a single beam of ultraviolet light and. m not require any additional materials. This allows photolithography to be highly effciy and cost-effective while producing extremely sm incisions in a substrate. 2) Photolithography controls the exact size and shape the entire substrate. Disadvantages of Photolithography The disadvantages of photolithography are as follows 1). Photolithography requires a completely Flat substax in onder to produce effective patterns. It is a efficient at producing objects that are not flat 2) Photolithography requires extremely clean conditions that are void of all contaminants, liquids, a environmental hazards. ‘Applications of Photolithograpby ‘The applications of photolithography are as follows 1). Photolithography produces integrated crculls a other internal computer parts 2) It has been used to produce manites as well # microscopic computer systems. 3). Photolithography also produces patterns on any sail surface and is simply a form of lithography Ques 23) What do you mean by electron eas lithography process? Also give the advan disadvantages, and applications of electron ba® lithography process. ‘Ans: Electron Beam Lithography Process The most common Nano patterning method out these 3 I electron Beam Lithography (EBL). This 1s « Gm! analogy with photolithography, where electron exposure alters the chemistry of the resist instead of gt exposure. The most common (positive tone) EBL resist polymethyl (methacrylate), abbreviated PMMA. EBL can routinely produce lines as narrow as 20 30am PMMA. Smaller features are possible 10 cert circumstances. Limiting factors include feature from secondary electron yields (proximity exposu! difficulties in developing such small features broaden y When electrons are accelerated through 4 P° nent wavelength is given by ‘Where, V is in keV and A is in nmFabrication Techniques and MOSFET Physical Design (Module 5) When, V = 10keV, 4 = 0.0123nm which is much smaller than the wavelength of UV light. The schematic diagram of electron beam lithography process is shown below: Electron Gun Blanking Plate Deflection Coils Lens > = Water Figure $.19: Schematic Diagram of Electron Beam Advantages of Electron Beam Lithography Process The advantages of electron beam lithography process are as follows: 1) Print complex patterns directly on wafers, 2) Eliminates the diffraction problem, 3) High resolution up to 20nm (photolithography ~ ‘S0nm), and 4). Flexible technique. Disadvantages of Electron Beam Lithography Process ‘The disadvantages of electron beam lithography process ae as follows: 1) Slower than optical lithography (approximately 5 wafers/hour at less than 0.11 resolution), 2) Expensive and complicated, and 3) Forward scattering. Applications of Electron Beam Lithography Process The applications of electron beam lithography process are a follows: 1) Application areas of e-beam lithography span a wide range from cryo-electric devices, opto-electronic devices, and quantum structures, transport mechanism, studies ‘of semiconductor/superconductor interfaces, microsystem techniques, and optical devices. 2) The use of electron-beam lithography on pentacene and poly(3-hexylthiophene) field-effect transistor to achieve device isolation and enable the realization of nanoscale organic circuits 3) It can be used in the fabrication process by soft lithography B-7I Ques 24) Explain the process of etching. Also explain the types of etching used in the removal of substrate from unmasked region. Ans: Etching Etching refers to the removal of material from the wafer surface. The process is usually combined with lithography in order to select specific areas on the wafer from which material is to be removed. Etching represents one way of Permanently wansferring the mask pattern from the Photoresist to the wafer surface. The complementary Drocess to etching is deposition (or growth), where new material is added. ‘Types of Etching ‘There are two main types of etching are used, which are as follows 1) Wet Etching: In wet etching, the wafers are immersed in a tank of the etchant (mix of chemicals), as shown in figure 5.20. There is a chemical reaction between the wafer surface and the etchants that helps in material removal. Either a photoresist layer or a hard mask like oxide or nitride layer is used to protect the rest of the wafer ‘The time for etching depends on the amount and type of material that needs to be removed. KOH (Potassium hydroxide) is a common etchant used to remove Si, Usually, 30% KOH solution is used, which has a etch rate of ~ 100 umvV/hr at 90°C. Thus, an entire 4” wafer, with thickness of 500 um, can be etched through in approximately 5 hours. (1) Reactants (1) Products (2) Reaction — Oxide Si Wafer Solution Figure 5.20: Schematic of the Wet Etching Process The etch rate of Si (100) by 30% KOH is shown in Mgure 5.21. After etching, the waters are rinsed, usually in DI water, for removal of etchant and then finally dried. KOH Bvching KOI 100 Si 30% olution n V7 130 Micranvhour 10 1 25 a 2» 30) SO ar ern) Temperate Figore 8.21: Etch Rate of Si in KOH as a Function of ‘Temperaturefine Suggest, is removal of east Ct solvent. Here, etchant gases Process, wan, elt” for the removal of material The i ts erced because wet etching has some Wet etch PPlicabilty, which ar listed below: ctching is used for large pattern sizes, ip Ta Jarger than 2um, hi 22 isotropic process — sloped sidewalls rather than straight walls, essential, ¥) Undercutting and resist eel off can hap. Ary etching processes are compared in a ry © Figure 5.22: (a) Starting Surface after Development of the Resist (b) Surface after Wet Etching (c) Surface after Dry Etching Ques 25) Discuss the process of metal deposition. Also explain various types of metal deposition techniques Ans: Metal Deposition Metallization refers to the wiring of the various fet a functioning circuit. Metal Gn (metallisation) is done for device contact and clectrical wiring. Ideally, the metal contact with gate, receecint, drain should have minimum’ possible ‘sistance and must follow Ohm’s law; whereas, the metal wiring should have minimum possible resistance and capacitance. Presently, all device contacts and metal (circuit) wirings are hot possible on a single layer (surface) because of ifsufficiency of space. Therefore, contacts and wirings are done in between the dielectric layers. This. scheme of electrical wiring is called multilevel wiring, In. present days, two-to three-level wiring is done. Metal Deposition Technique The Various types of metal deposition techniques are as follows: 1) Physical Vapour Deposition: Generally, the PVD Processes are performed under vacuum circumstances, and it involved four steps. Firstly, evaporation, over this stage the target is evaporated by high energy Source such as resistive heating or electrons beam. Secondly, transportation, the vapourised atoms move from target to the surface of substrate through this Phase. The third step is reaction, in some cases deposition, if there is a gas such as nitrogen or oxygen B.Tech, Sixth Semest 1p Solved Series (VLSI Circuit Design) xy tet ff materials reacts with er eer aes the coating does = only consist Of the tare, f gas, but it only as Spal “his phase does not be part ot Process, Finally, deposition, through this stage the surface of substrate will be built. ique is classified into two sorts: This techni evaporation: It is traditionally — Do aesatiea deposition, is used as a simples, Eaiaee for preparing thin film with a smay umber of micrometer (ja) thicknesses, The thermal evaporation process consists of evaporating and condensing processes in vacuum (=1x10° millibar) chamber. Firstly, source materials are evaporated by the heated source, which is maintaining a few cm distances from a substrate. Then, evaporated particles are condensed on the substrate. This process can use two types of sources that are resistive and electron beam source, which are shown in figure 5.23. Resistance heating evaporation Substrate in the system, the gas. If, however. in Electron beam evaporation Deposition of thin film ‘Vaporised material Vaporised material ‘Target material Evaporator + Heater To Vacuum Pump Figure 5.23: Types of Thermal Evaporation Process ') Sputtering: Sputter deposition is a physical Tle eno Position (PVD) method ef thin film deposition by sputtering. This involves cketing material from a target that is « source Onto a substrate such as a silicon wafer, ‘To Vacuum : swe? fom high-energy. ballistic impact to fow-energy thermalized motion is The gp M"8IME the background gas mn, uttering gas is often an inert gas meatentum transfer, the atomic he or aeTiPE Bas should be close tothe Of the target, so for sputtering light on Preferable, while for heavy On of The “PINEHNG a thown nthe Rene gt edae tYeical Design (Module 5) Vacuum, Chamber Substrate Plasma Target Sputter Gas — High Voltage Figure 5.24 2) Chemical Vapour Deposition: It may be defined as a system in which a combination of gases reacts with the substrate surface at a relatively great temperature, leading to decay of certain of the constituents of the gas combination and the fabrication of a solid film of depositing of a metal or composite on the substrate Types of Chemical Vapour Deposition A number of forms of CVD are in wide use and are frequently referenced in the literature. These Processes differ in the means by which chemical ‘actions are initiated (e.g., activation process) and process conditions. ') Atmospheric Pressure CVD (APCVD): CVD processes at atmospheric pressure. 4) Low Pressure CVD (LPCVD): CVD processes at sub-atmospheric pressures, Reduced pressures tend to reduce unwanted gas-phase reactions and improve film uniformity across the wafer. Most modem CVD process is either LPCVD or UHVCVp. ‘) Ultrahigh Vacuum CVD (UHVCVD): CVD Processes at a very low pressure, typically below 10“Pa (— 10torr). ') Plasma Enhanced CVD (PECVD): CVD Processes utilise plasma to enhance chemical Teaction rates of the precursors PECVD Processing allows deposition at__lower temperatures, which is often critical in the Manufacture of semiconductors. MOSFET FABRICATION ps ess ‘hes 26) Explain N-well CMOS IC. fabrication with the help of suitable diagram. Or h Lplain Newell CMOS IC fabrication sequence wit “help of neat diagrams. gsi ep B73 Explai Or the N-well CMOS IC Fabrication Sequence. (2021 [07)) Ans: N-well CMOS IC Fabrica The most popular approach fo CMOS starwith a lightly doy creates the n-type well for Hansistors. The process sequence of N-well CMOS IC fabrication sequence is shown in figure 5.2 ‘Create n-well regions and channel step regions Grow field oxide and gate oxide (thin oxide) Deposit and pattern polysilicon layer Implant source and drain regions, substrate contacts Create contact windows, deposit and pattern ‘metal layer tion Sequence r the fabrication of n-well ped p-type substrate and the fabrication of p-MOS Figure 5.25 Major steps for n-well CMOS process are illustrated follows: 1) The basic idea behind the n-well process is the formation of an n-well or tub in the p-type substrate and fabrication of P-tansistors within this well. The formation of an n-well by ion implantation is followed by a drive-in step (1.8 x 10” p cm, 8OkV with 1150°C for 15h of drive-in). This step requires a mask, which defines the deep n-well diffusions. ‘The ‘-transistor is formed outside the well. The basic steps are mentioned below: i) Start with a blank wafer, commonly known as a substrate, which is lightly doped as shown in figure below. P substrate fi) Cover the wafer with a protective layer of Si. (shown in figure below) using the oxidation Process at 900-1200°C with HO (wet ox idati or O; (dry oxidation) in the oxidation jturnace iti) Spin on photoresist, which is a light-sensitive organic polymer. It softens where exposed to light Protons SiO. psubstrate ide 2 ae TlB74 iv) Expose photoresist through the n-well mask and strip off the exposed photoresist using organic solvents. The n-well mask used to define the - ‘well in this step is shown in the figure below. Photoresist SiO: p substrate ¥) Etch oxide with HF, which only attacks oxide where the resist has been exposed. Photoresist SiO: : Pesubstrate vi) Remove the photoresist, which exposes the wafer as illustrated in the figure below. a S10; substrate vii) Implant or diffuse n dopants into the exposed wafer using diffusion or ion implantation as shown in the figure below. The ion implantation process allows shallower wells suitable for the fabrication of devices of smaller dimensions. The diffusion process occurs in all directions and dipper the diffusion more it spreads laterally. This affects how closely two separate structures can be fabricated. Fisio. pTech, Sixth Semester TP Solved Series (VLSI Circuit Design) xp Ques 27) Explain CMOS fabrication. Also is different types of CMOS Fabrication technique, or Define CMOS fabrication with suitable diagram, the different types of CMOS Fabrication technique aq explain any one of them with suitable diagram, Or Describe the twin tub fabrication technique yig suitable diagram. Also write the fabrication proc, flow steps of the twin-TUB fabrication. te ‘Ans: CMOS fabrication CMOS or Complementary Metal Oxide Semiconductor combination of NMOS and PMOS transistors. NMOS js @ N-type Metal Oxide Semiconductor, and PMOS is a Payy ‘Metal Oxide Semiconductor. N-type is a type of pentavaly impurities, and P-type is a type of trivalent impurities dope ‘on the semiconductor. The three terminals of the transisigy are Gate (G), Source (S), and Drain (D). The doping of » typeln-type is applied on the D and S terminals. ‘Types of CMOS Fabrication ‘The types of CMOS fabrication are as follows: 1) N-Well Fabrication 2) P- Well Fabrication 3) Twin-TUB Fabrication ‘The p-Well CMOS fabrication Process In this process of CMOS, the structure consists of an r type substrate in which p-type devices may be formed ty suitable masking and diffusion. In order to accommodae n-type devices, a deep p-well is diffused into the nye substrate as shown in the figure 5.26. SiO well viii) Strip off SiO; leaving behind the p-substrate alongwith the n-well as illustrated in the figure below. aa pots (4.5 um) 8 Polysilicon 2) ‘The formation of thin oxide regions for the formation of p- and n-transistors requires MASK 2(as shown in figure) which is also known as active mask because it defines the thin oxide regions where gates are formed. Polyslicon Thin pate oxide Potysiticon Thin gate oxide (Thin Oxitt and Polysilica) See ce cee oO P-diffusion pr Mas Post. Fabrication Techniques and MOSFET Physic gs a Positive) in ign (Module 5) Figure 5.26: CMOS p-Well Process Steps The diffusion must be carried out with special care since the p-well doping concentration and depth with affecting the threshold voltages the breakdown volt of the n-transistors, To achieve low threshold voltages (0 t0 1.0 V), we need either deep well diffusion or high well resistivity However, deep wells require larger spacing between the n- type and p-type transistors and wires because of lateral Uiffusion and hence a large chip area The p* wells act as substrate parent n-substrate and the isolated ne n-devices within the two areas are electrically Fabrication Process Flow In summary, typical processing steps are 1) Defines the areas in which the deep p-well diffusions are to take place. Defines the thin oxide regions, namely those ateas where the thick oxide is to be stripped and thin oxide is grown to accommodate p and n-transistors and wires. Used to pattem the polysilicon layer deposited after the thin oxide A pt mask is now used (to be in effect “Anded” with step 2) to define all areas where p-diffusion i 10 take place: 5) This is usually performed using the negative form of the p+ mask and defines these areas where n-type diffusion is to take place. ) Contact cuts are now defines! The metal layer pattern is defined by this mask. 8) An overall passivation (over glass) layer is now applied and this mask 1s needed to define the openings for access to bonding pads Twin-TUB Fabrication As the name implies, (win-TUB is 4 ‘and n-well processes formed on the also known as dual well process. The high ype substrate with both n-well and p-well re ‘reated, as shown below which is ame substrate sistivity Zw pitas Layer Figure $27 It is an inverting arrangement of twin-tub. The separate transistors and their arrangement help to optimize the n- type devices, p-type devices, and other parameters, such as body effect and threshold voltage. The wafer has two layers. The top layer is the epitaxial layer and the main substrate layer is of n-type. Fabrication Process Flow ‘The steps of the twin-TUB fabrication are as follows: 1) Deposition of thin oxide layer of silicon dioxide SiO»). 2) The deposition of silicon nitride layer using the CVD process. It has various advantages, such as high temperature stability and light weight The third step includes creating trenches and filling them with SiO2, which is an insulating material. The trenches are created to prevent the current leakage The oxide and nitride is removes to deposit the n-well and p-well regions with the help of diffusion, The p-well and the n-well mask are used to dispose of, the specific areas on both sides. The implant and annealing are required to adjust. the doping concentration of the two wells. The annealing process reduces the hardness for efficient doping. A thin layer of SiO. and polysilicon is applied on the surface of the silicon wafer. 4 5) The source, gate, and drain regions are created using the diffusion process 8) 9 ‘The oxide and nitride layer is again deposited. The metal layer of aluminum is deposited on the surface of wafer including the contact holes. It also fills the cut holes, A protective glass layer is deposited on the transistor in the last step, 10) LAYOUT DESIGN AND DESIGN RULES Ques 28) Discuss about the basic layout design rules. Or ‘What is layout design rule? What are the differences between } rule and micron rule?