Design and Implementation of Operational

Amplifiers with Programmable Characteristics

in a 90nm CMOS Process
Sherlyn C. dela Cruz, Mark Gerard T. delos Reyes, Terence C. Gaffud,
Tanya Vanessa F. Abaya, Maria Theresa A. Gusad and Marc D. Rosales

Abstract—Operational amplifiers (op-amps) serve as the basic like power management, circuit integrity, rule-based physical
building blocks in almost every analog and mixed-signal verification, and parasitic extraction may not just be enough.
electronic circuit. However, one of the most common problems in A designer’s strategy must shift from basic and fundamental
op-amp design is the variation in the op-amp's performance design techniques to new and optimal design methods which
caused by process variations during fabrication. As such, it is of may require changing the design itself.
utmost importance that provisions be made on the op-amp to
compensate for possible deviations in performance after chip During chip fabrication, there are unavoidable permanent
fabrication. In this paper, a procedure on integrating variations in the parameters of the design. Because of this,
programmable bias networks into an operational amplifier is solutions are being developed on how to minimize the effects
developed. The programmable network driven by digital input of the variations. One possible solution is to incorporate
words makes the output bias currents and voltages variable, thus programmable blocks into the chip. This makes certain
making the op-amp tunable for proper operation even after chip
parameters variable even after chip fabrication. In this paper,
fabrication. Furthermore, the programmability of other op-amp
digital input words (i.e. logic high or logic low) control the
parameters such as gain, slew rate, and compensation are
explored to increase the capability and flexibility of the op-amp. switches of the programmable blocks, making these parameter
The programmability schemes are employed on two base op-amp variations in discrete levels only.
topologies namely, the Two-stage Miller and the Folded Cascode.
The project is implemented in a standard 90nm CMOS process. II.BASE OP-AMPS
Part of this project is the development of two op-amps
I.INTRODUCTION which are used as base amplifiers for the programmable

A nalog CMOS design becomes more difficult especially

in the present age of nanometer technology. This is
mainly because CMOS technology has been greatly
optimized for digital circuits while analog circuit design
blocks. The two base op-amps are the Two-stage Miller and
the Folded Cascode op-amps. These op-amps are necessary to
measure the performance of the programmable blocks during
integration.
cannot fully utilize the technology. Digital circuit design only
Figure 1 shows the schematic diagram used for the
depends on the tradeoff between speed and power dissipation
implementation of the Two-stage Miller op-amp.
while analog circuit design has other factors to consider such
as noise rejection and interference. This, in itself, poses major
problems in design and with the emergence of the nanometer PMOSVdd Differential Push-pull
Vdd
technology, more problems arise. These problems make current amplifier stage inverter stage
mirror M8
design process and implementation more difficult than it is in
Vdd
M1

previous CMOS technologies.

Vin1 Vin2 M6
Smaller transistor area means more transistors can be M2 M3
Rc Cc Vout

packed in a single chip. This makes a single chip smaller in M9 M4 M5

physical size but more powerful in performance in terms of M7

speed and bandwidth. But this also makes a single chip more
intricate because of the increased complexity in the layout and
Fig. 1. Two-stage Miller op-amp schematic diagram
fabrication rules, making chip manufacturability a great
challenge. Minor process variations and parameter drifts
become major problems due to the chip’s high sensitivity to Figure 2 shows the schematic diagram used for the
implementation of the Folded Cascode op-amp.
physical defects. As a result, old design techniques are no
longer applicable to the present technology. Fundamentals

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PMOS Folded Cascode Push-pull programmable bias networks driven by digital inputs to the
current mirror Vdd amplifier stage inverter stage op-amp design and implementation. This makes the bias
M1 M2
currents and voltages tunable to the desired value for correct
M11 M12
M14 M17 op-amp operation even with process variations after chip
M3 M4 fabrication.
Vin+ Vin- C R
M5 M6 Vout
Three programmable bias network topologies are
implemented in this project namely: Programmable Current
M7
M8

Attenuator (PCA), Programmable Current Reference Circuit

M13 M15
M18

M9
M10 M16
(PCRC), and Programmable Current Source (PCS).
Programmable Current Attenuator (PCA)[1]
Fig. 2. Folded Cascode op-amp schematic diagram Figure 4 shows a 4-bit digitally-programmed current
attenuator circuit. It is based from the conceptual scheme of
Snapshots of the layout of the two base op-amps are shown an R-2R ladder network. The value of the current passing
in Figure 3. through the legs of the circuit is determined by two major
factors: the division factor, D, introduced by the scheme itself,
5.88 μm 5.84 μm and the input digital word at the gates of the transistor pairs.
Two complementary outputs, I1 and I2 are produced at the
output node which is mainly dependent on the reference
current, Iref.
I1

I2

B1 B1 B2 B2 B3 B3 B4 B4
M1 M2 M8 M7 M12 M11 M14 M15

18.75 μm 24.41 μm
Iref/2 Iref/4 Iref/8 Iref/8
M3 M6 M10 M13
Iref/2 Iref/4 Iref/8
Iref
M4 M5 M9

Fig. 4. PCA schematic diagram[1]

Programmable Current Reference Circuit (PCRC)[3]

Figure 5 shows a 4-bit digitally-programmed current
(a) (b) reference circuit taken from a patent[3]. The architecture of the
Fig. 3. Layout of (a) Two-stage Miller and (b) Folded Cascode op-amps circuit shown in this figure is composed of transistor pairs
Table 1 summarizes the obtained specifications for the Two- with each pair connected in parallel with resistors of different
stage Miller and Folded Cascode op-amp. values. The circuit works by varying the total resistance seen
at the output node using the transistor pairs as switches, thus
TABLE 1 changing the P- and N- bias voltages or VP and VN,
SUMMARY OF OBTAINED SPECIFICATIONS FOR THE BASE OP-AMPS respectively.
Parameter Two-stage Miller Folded Cascode +V
Adm 52.37 dB 65.66 dB
M27 M26
CMRR 88.64 dB 103.23 dB
GBWP 1.014 GHz 539.4 MHz
M21
Out
M20

PM 47.4o 7.721° R0

SR 697.53 V/µs 556.42 V/µs M25 M19

R1

M24 M18
R2

III.Programmable Bias Networks M23 M17

R3

It is very critical for every op-amp to function properly and M22 M0

R4

correctly. During simulation, an ideal op-amp’s accuracy is

mainly dependent on how accurate its biasing is. However,
during chip fabrication, the technology parameters of the Fig. 5. PCRC schematic diagram[3]
transistors such as threshold voltage VT, length L, and width
W vary from the values used during schematic and layout Programmable Current Source (PCS)[2]
simulations. These deviations usually result in a change in the
bias voltages and bias currents; thus affecting other op-amp Figure 6 shows a 4-bit digitally-programmed current source
characteristics. One way of solving this problem is to include circuit. Equally sized NMOS transistors are connected either

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in series or in parallel to achieve the needed current, Iout. This Programmable Gain Amplifier (PGA)[5]
type of transistor connection effectively increases or decreases
the total W/L ratio of each leg: increasing the number of Figure 9 shows a 4-bit digitally-programmed gain amplifier.
transistors in serial connection decreases the current flowing The PGA consists of a negative feedback gm-boosted source
through it while parallel connection increases the leg current. degenerated differential pair with resistive loads, RLOAD =
The architecture delivers pre-programmed binary weighted 50kΩ. The main concept of this approach is to change the
current levels at every current leg which are all summed up at value of the resistance R so that the gain of the amplifier will
the Iout node. The number of bits on logic high contributes to also change. The PGA has a fixed dominant pole at
the additive nature of the current Iout. thus having a constant GBWP at all sweeps of
toM9
the degenerated resistance. It is a stand-alone amplifier;
B0 B1 B2 B3
therefore no integration with the base op-amps was done.
M1 M2 M6 M14 M30

M3 M7 M15 M31
Vdd

M4 M16 M32
M1 M2 M3
M5 M33

M12

M13 M27 50k 50k

Vin1 M4 Vin2 M5
M28 M58 Vout1 Vout2 Iref
R
M29 M59

M60 M7
M8 M6 M9
M61

Fig. 9. PGA schematic diagram[5]

Fig. 6. PCS schematic diagram[2]
Figure 10 shows a graph of the obtained results for the
Figure 7 summarizes the obtained specifications for the PGA.
integration with Two-stage Miller op-amp and Figure 8 for the
integration with the Folded Cascode op-amp.

Fig. 10. Obtained results for PGA

Programmable Slew Rate (PSR)[4]

Fig. 7. Obtained results for the integration of PCA, PCRC, and PCS with the
Two-stage Miller op-amp Figure 11 shows a 4-bit digitally-programmed slew rate.
This topology uses programmable current source in order to
make the currents within the op-amp variable. Every variation
to the bias current affects the output slew rate of the base op-
amp.
out

M3 M2 M1 M0 To op-amp

Fig. 11. PGA schematic diagram[4]

Fig. 8. Obtained results for the integration of PCA, PCRC, and PCS with the
Figure 12 shows a graph of the obtained results for the
Folded Cascode op-amp integration with the Two-stage Miller op-amp and Figure 13
for the integration with the Folded Cascode op-amp.
IV.OTHER PROGRAMMABLE TOPOLOGIES
To further increase the programmability and capability of
our op-amps, other programmable topologies are implemented
such as Programmable Gain Amplifier, Programmable Slew
Rate, and Programmable Compensation.

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Fig. 12. Obtained results for the integration of PSR with the Two-stage Miller Fig. 16. Obtained results for the integration of PC with the Folded Cascode
op-amp op-amp

V.CONCLUSIONS AND RECOMMENDATIONS

Using the presented methodologies, it is possible to design
and implement op-amps with programmable characteristics.
The three programmable bias network topologies were all able
to vary the input current driving the base op-amps with a range
of 8µA to 12µA (IBASE +/-20%). However, PCRC and PCA
suffer from poor linearity. Only PCS was able to produce a
linear output current which closely follows a linear step
increase.
The PGA attained a range of 0-17 dB. A constant GBWP of
Fig. 13. Obtained results for the integration of PSR with the Folded Cascode
op-amp 11.5 GHz is maintained at all sweeps of gain. The PSR also
was able to vary the slew rate for the integration with both op-
Programmable Compensation (PC) [6] amps. The integration with the Two-stage Miller and Folded
Cascode op-amp attained a slew rate range of 504 V/µs to 895
Figure 14 shows a 4-bit digitally-programmed V/µs and 434 V/µs to 1,354 V/µs respectively. Finally, the PC
compensation. The PC is implemented using MOS capacitors was able to increase the phase margin from 35.8o to 61.2o and
which are ideally connected in between the input and output from 0o to 75.31o for the integration with the Two-stage op-
stages of an uncompensated op-amp. Varying values of amp and Folded Cascode op-amp respectively.
capacitances effectively varies the compensation of the circuit.
ToInput ToOutput REFERENCES
[1] Sanz, Calvo, Celma and Moran. A Digitally Programmable VGA. 44th
R1
IEEE Midwest Symposium on Circuits and Systems. Vol. 2, pp 602 –
605. 2001.
[2] Ghorbel, Ben Hamida and Samet. Programmable Current Source
M3 M4 M5 M6
Dedicated to a Cochlear Implant. First International Symposium on
Control, Communications and Signal Processing. Pp 251 – 254. 2004.
CP1 CP2 CP3 CP4 [3] Chang and Starr. Programmable Current Reference Circuit. 2004.
[4] Shin, J.M. and Yoon, K.S. Design of a Programmable Slew Rate Op-Amp.
Fig. 14. PC schematic diagram [6]
37th Midwest Symposium on Circuits and Systems. Vol 1, pp 142 – 146.
1994.
Figure 15 shows a graph of the obtained results of the PC [5] Calvo, Sanz, and Celma. Low-voltage Low-power CMOS Programmable
integrated with the Two-stage Miller op-amp and Figure 16 Gain Amplifier. 6th International Caribbean Conference on Devices,
Circuit and Systems. Pp 101 -105, 2006.
for the integration with the Folded Cascode op-amp. [6] Lee, H.F. and Huang, Y.H.. A Rail-to-Rail CMOS Amplifier with
Programmable Compensation Schemes. 2003 IEEE Conference on
Electron Devices and Solid-State Circuits. Pp 105 – 108. 2003.
[7] Villena, P. W. Characterization of Operational Amplifiers Implemented in
a 90nm CMOS Process. University of the Philippines, Diliman, Quezon
City. October 2007

Fig. 15. Obtained results for the integration of PC with the Two-stage Miller
op-amp

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