LABORATORY MANUAL

Electrical
&
Electronics Engineering

(UES013)
 Digital Electronics Experiment No.1

Aim Implementation of following logic expression using AOI logic and then
Experiment:
implement using minimum numbers of NAND Gates:
̅
𝒁(𝑨, 𝑩, 𝑪) = 𝑨𝑩 + 𝑪

Apparatus: Digital training kit, Power supply, Connecting Wires, IC 7400 (NAND Gate
IC).

Before Implementing the above experiment, we need to understand basic and universal
logic gates.

Theory: Logic Gates are electronic circuits to perform logical operations. Each Gate can
have one (for NOT Gate) or multiple input variables (for all other Gates) and generate one
output. AND, OR and NOT Gates are basic logic Gates; NAND and NOR are called
Universal logic Gates; Apart from that there are two more special Gates XOR and XNOR.
The input combinations of a logic Gate and corresponding output can be written in a
Tabular form, which is called Truth Table. Various Gates, their Symbols, and Truth Tables
are illustrated in Table1.

IC configurations: In this experiment, we will use IC 7400 (NAND Gate IC). The IC
configuration is illustrated in the figures below -

Figure 1: 7400 IC Configurations.

Table1
 Being universal Gates, NAND and NOR can be used to implement any logic Gate; In
below examples, we show the Implementation of different Logic Gates (AND, OR, NOT,
NOR) using NAND Gates.

Experiment: Implementation of following logic expression using AOI logic and then
implement using minimum numbers of NAND Gates:
̅
𝒁(𝑨, 𝑩, 𝑪) = 𝑨𝑩 + 𝑪

Truth Table:

𝐴 𝐵 𝐶 𝐴𝐵 𝐶̅ 𝑍 = 𝐴𝐵 + 𝐶̅
0 0 0 0 1 1
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 0 1 1
1 0 1 0 0 0
1 1 0 1 1 1
1 1 1 1 0 1
 ̅
Simplification: 𝒁 = 𝑨𝑩 + 𝑪
 Digital Electronics Experiment No: 2
To verify the working principle of 8:1 Multiplexer

Objective:
Aim Design the following Boolean function using 8:1 multiplexer:

(𝑋, 𝑌, 𝑍) = Σ 𝑚(0, 2, 4, 6, 7)

Components and Equipment required: Digital IC trainer kit, IC’s (74151) &
connecting wires.
Theory:

A multiplexer is a combinational circuit that has 2n input lines and a single output
line. Simply, the multiplexer is a multi-input and single-output combinational
circuit. The binary information is received from the input lines and directed to the
output line. On the basis of the values of the selection lines, one of these data inputs
will be connected to the output. So, there are n selection lines and 2n input lines.

IC PINOUT:
  D0- D7 (PIN 1-4, 12-15) are the Input.

 S2, S1, S0 (PIN 9-11) are the select lines.

 VCC (PIN 16) is the bias voltage.

 GND (PIN 8) is the ground.

 Y (PIN 5) is the output PIN

Truth Table:

Select lines Output

S2 S1 S0 F
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

Truth table to be implemented:

Inputs Output
X Y Z F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
If we map S2, S1, S0 to X, Y, Z respectively, then

Inputs Output
S2X S1Y S0Z F
0 0 0 D01
0 0 1 D10
0 1 0 D21
0 1 1 D30
1 0 0 D41
1 0 1 D50
1 1 0 D61
1 1 1 D71
 Experiment 3

Aim: Design a 2-bit asynchronous counter using JK Flip-Flop (IC 7473).

Apparatus: Digital trainer kit, Power supply, Connecting wires, IC 7473.

Theory: The flip-flop is a basic bi-stable memory element widely used in sequential
logic circuits. Usually there are two outputs, Q and its complementary value. They
are called state variables. State variables which change only between logic 1 and
logic 0 are called binary state variables. There are two types of triggering are
considered in the JK flip flop; Positive and Negative edge triggering.
For a positive-edge triggered JK flip-flop:
 If the J and K inputs change while the clock transitions from low to high, the
flip-flop will respond to those changes.
 If the J and K inputs change while the clock is in a high state, the changes will
not affect the flip-flop's state until the next rising edge of the clock.
For a negative-edge triggered JK flip-flop:
If the J and K inputs change while the clock transitions from high to low, the
flip-flop will respond to those changes.
If the J and K inputs change while the clock is in a low state, the changes will not
affect the flip-flop's state until the next falling edge of the clock.
In JK flip-flop is a type of flip-flop circuit that has two inputs, J (set) and K (reset).
When the clear input is activated, it overrides the behavior of the flip-flop and forces
its outputs to a ‘LOW’ state and is the set input is particularly useful when you want
toinitialize or force a ‘HIGH ‘in a sequential circuit.

JK Flip Flop

1. Assemble the circuit for testing the behavior of JK flip flop. Pin
connections are shown above.
2. Set J=0, K=1, provide Clock pulse. Note logic level of Q and Q’
3. Set J=0, K=0, provide Clock pulse. Note logic level of Q and Q’
4. Set J=1, K=0, provide Clock pulse. Note logic level of Q and Q’
5. Set J=0, K=0, provide Clock pulse. Note logic level of Q and Q’
6. Set J=1, K=1, provide Clock pulse. Note logic level of Q and Q’
7. Again provide Clock pulse without changing the J & K inputs i.e.
keep J=1, K=1.Note logic level of Q and Q’. Repeat this step 2-3
times.
8. Check the output with CLR pin.
9. Prepare the truth table of the JK flip flop for all the possible input combinations.
10. Write your observations indicating for which J & K inputs, the flip
flop Q output is set to ‘1’and reset to ‘0’
 2 bit Asynchronous Counter

1. Wire up the two flip flops of IC 7473 as shown.

2. Connect the Q outputs of the flip flops to LED indicators on the kit. In the
above diagram, Flip flop Q1 provides the MSB and Q0 provides the LSB of
the counter.
3. Connect the common CLR line of the two flips through a switch on the trainer Kit.
4. At the beginning reset the Q outputs of the two flips by switching the CLR
line to “LOW “level and then to “HIGH”. Keep it HIGH thereafter for rest
ofthe performance.
5. Now Pulse the CLK_IN line on the trainer kit and note down the Q1 & Q0.
6. Keep on pulsing the CLK_IN line and note the direction of count.
7. In the above diagram Q output of first flop is connected as CLK input to second
flip flop. Now change the CLK input of second flip flop to 𝑄̅ output of first flop.
Now pulse the CLK_IN line of the counter again and note the direction of count
noting the Q1 & Q0 outputs of the two flip flops.
Procedure

1. Make the connections as shown in the figure.

2. Connect the primary side of the transformer to AC mains & Secondary side to the circuit input.
Get the connections check from Teacher.
3. Now, the the Oscilloscope at the input & output of the circuit and display these input & Output
signal on Oscilloscope.
4. Observe the Input and Output using DSO/CRO.
5. Put these respective Waveforms.

Observation
Ripple Factor of Half wave Rectifier

Efficiency of Half Wave Rectifier

UEC001 Lab manual

Experiment No. 65
Aim: To study the switching characteristics of bipolar transistors (BJT) and calculate the
delay time, rise time, ON time, storage time, fall time, OFF time.
Apparatus required:
Items Quantity
Transistor (BC107) 1
Resistors (68K, 2.2K, 1K) 1each
Capacitor (0.1uF) 1
DC variable power supply 1
CRO/DSO 1
Breadboard 1
Jumper wires as per requirement

Theory
One of the most fundamental applications of a transistor is using it to control the
flow of power to another part of the circuit – using it as an electric switch. Driving it in either
cut-off or saturation mode, the transistor can create the binary on/off effect of a switch.

Cut-off Region
Here the operating conditions of the transistor are zero input base current ( IB ), zero
output collector current ( IC ) and maximum collector voltage ( VCE ) which results in a large
depletion layer and no current flowing through the device. Therefore the transistor is
switched “Fully-OFF”.
•The input and Base are grounded (0v)
•Base-Emitter voltage VBE < 0.7v
•Base-Emitter junction is reverse biased
•Base-Collector junction is reverse biased
•Transistor is “fully-OFF” (Cut-off region)
•No Collector current flows ( IC = 0 )
•VOUT = VCE = VCC = ”1″
•Transistor operates as an “open switch”

Figure 6.1 Transistor in Cut-off Region

Then we can define the “cut-off region” or “OFF mode” when using a bipolar
transistor as a switch as being, both junctions reverse biased, VB < 0.7v and IC = 0. For a PNP
transistor, the Emitter potential must be negative with respect to the Base.

Saturation Region

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UEC001 Lab manual

Here the transistor will be biased so that the maximum amount of base current is
applied, resulting in maximum collector current resulting in the minimum collector emitter
voltage drop which results in the depletion layer being as small as possible and maximum
current flowing through the transistor. Therefore the transistor is switched “Fully-ON”.

•The input and Base are connected to VCC

•Base-Emitter voltage VBE > 0.7v
•Base-Emitter junction is forward biased
•Base-Collector junction is forward biased
•Transistor is “fully-ON” (saturation region)
•Max Collector current flows ( IC = Vcc/RL )
•VCE = 0 (ideal saturation)
•VOUT = VCE =”0″
•Transistor operates as a “closed switch”

Figure 6.2 Transistor in saturation Region

Then we can define the “saturation region” or “ON mode” when using a bipolar
transistor as a switch as being, both junctions forward biased, VB > 0.7v and IC = Maximum.
For a PNP transistor, the Emitter potential must be positive with respect to the Base.
A transistor cannot be turned on instantaneously because of presence of internal
capacitances. The figure shows the switching waveforms of an NPN transistor with resistive
load between collector and emitter.
When base-emitter voltage is VBE is applied, the base current rises to IBS . The collector
current however remains zero or equal to collector-emitter leakage current ICE0 as shown in
figure.

Figure 6.3 Circuit diagram of transistor as a switch with input/output waveforms

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UEC001 Lab manual

After some time delay td called delay time, the collector current begins to rise. This
delay is due to the time required to charge base emitter capacitance to V BES=0.7V.After this
delay td, Collector current rises to steady state value ICS in time tr, which is known as “Rise
Time” . This means that turn on time for BJT is
ton = td + tr .

Rise time depends upon the input capacitance. During rise time t r, Collector-emitter voltage
falls from VCC to VCES. When the base-emitter voltage VBE is removed at time t1, the collector
current doesn’t change for a time ts , called “Storage time”.
During ts, saturating charge is removed from the base. After ts, collector current
begins to fall and at the same time collector voltage starts building up. After time t f , called
“Fall Time”. IC decreases to ICE0 (Almost zero) and collector-emitter voltage rises to VCC . Sum
of “Storage time” and “fall time” gives “Turn off” time.

toff = ts + tf

Procedure
1. Connect the circuit as shown in figure 6.3
2. Set input (say Square wave, 5V, 100KHZ) using a function generator.
3. Observe the output at collector of transistor using CRO/DSO.
4. Note down the parameters listed above and plot it on a graph paper.

Result:

The Switching characteristics of the transistor have been studied and the required
parameters are observed.

Precautions:

1. All the Connections should be tight

2. While doing the experiment do not exceed the ratings of the transistor. This may lead to
damage of the transistor.
3. Transistor terminals must be identified and connected carefully.
4. Switch “ON “the power supply after completing the circuit.

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