www.DataSheet4U.

com

UC1861-1868
UC2861-2868
UC3861-3868
Resonant-Mode Power Supply Controllers
FEATURES DESCRIPTION
• Controls Zero Current Switched (ZCS) The UC1861-1868 family of ICs is optimized for the control of Zero Cur-
or Zero Voltage Switched (ZVS) rent Switched and Zero Voltage Switched quasi-resonant converters. Dif-
Quasi-Resonant Converters ferences between members of this device family result from the various
• Zero-Crossing Terminated One-Shot combinations of UVLO thresholds and output options. Additionally, the
Timer one-shot pulse steering logic is configured to program either on-time for
ZCS systems (UC1865-1868), or off-time for ZVS applications (UC1861-
• Precision 1%, Soft-Started 5V 1864).
Reference
The primary control blocks implemented include an error amplifier to com-
• Programmable Restart Delay pensate the overall system loop and to drive a voltage controlled oscillator
Following Fault (VCO), featuring programmable minimum and maximum frequencies. Trig-
• Voltage-Controlled Oscillator (VCO) gered by the VCO, the one-shot generates pulses of a programmed maxi-
with Programmable Minimum and mum width, which can be modulated by the Zero Detection comparator.
Maximum Frequencies from 10kHz to This circuit facilitates “true” zero current or voltage switching over various
1MHz line, load, and temperature changes, and is also able to accommodate the
resonant components' initial tolerances.
• Low Start-Up Current (150µA typical)
Under-Voltage Lockout is incorporated to facilitate safe starts upon
• Dual 1 Amp Peak FET Drivers power-up. The supply current during the under-voltage lockout period is
• UVLO Option for Off-Line or DC/DC typically less than 150µA, and the outputs are actively forced to the low
Applications state. (continued)

Device 1861 1862 1863 1864 1865 1866 1867 1868

UVLO 16.5/10.5 16.5/10.5 36014 36014 16.5/10.5 16.5/10.5 36014 36014
Outputs Alternating Parallel Alternating Parallel Alternating Parallel Alternating Parallel
“Fixed” Off Time Off Time Off Time Off Time On Time On Time On Time On Time

BLOCK DIAGRAM

UDG-92018
Pin numbers refer to the J and N packages.
10/98
 UC1861-1868
UC2861-2868
UC3861-3868
DESCRIPTION (cont.)
UVLO thresholds for the UC1861/62/65/66 are 16.5V start delay, and the internal system reference.
(ON) and 10.5V (OFF), whereas the UC1863/64/67/68 Each device features dual 1 Amp peak totem pole output
thresholds are 8V (ON) and 7V (OFF). After VCC ex- drivers for direct interface to power MOSFETS. The out-
ceeds the UVLO threshold, a 5V generator is enabled puts are programmed to alternate in the
which provides bias for the internal circuits and up to UC1861/63/65/67 devices. The UC1862/64/66/68 out-
10mA for external usage. puts operate in unison alllowing a 2 Amp peak current.
A Fault comparator serves to detect fault conditions and
set a latch while forcing the output drivers low. The Soft-
Ref pin serves three functions: providing soft start, re-

CONNNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
PLCC-20 & LCC-20 (Top View)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Q & L Package
Output Current
PACKAGE PIN FUNCTION
Source or Sink (Pins 11 & 14) . . . . . . . . . . . . . . . . . . . . . 0.5A
FUNCTION PIN
DC Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5A
Soft Ref 1
Power Ground Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V 5V 2
Inputs (Pins 2, 3, 10, & 15) . . . . . . . . . . . . . . . . . . . . –0.4 to 7V NI 3
Error Amp Output Current . . . . . . . . . . . . . . . . . . . . . . . . ±2mA INV 4
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W E/A Out 5
Junction Temperature (Operating). . . . . . . . . . . . . . . . . . 150°C Sig Gnd 6
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C Range 7
All voltages are with respect to signal ground and all currents RMIN 8
are positive into the specified terminal. Pin numbers refer to CVCO 9
the J and N packages. Consult Unitrode Integrated Circuits da- RC 10
Zero 11
tabook for information regarding thermal specifications and
NC 12
limitations of packages. NC 13
A Out 14
Pwr Gnd 15
DIL-16, SOIC-16 (Top View) Pwr Gnd 16
J or N, DW Packages VCC 17
B Out 18

2
 UC1861-1868
UC2861-2868
UC3861-3868
ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°C≤TA≤125°C for the
UC186x, –25°C≤TA≤85°C for the UC286x, and 0°C≤TA≤70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,
C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
5V Generator
Output Voltage 12V ≤ Vcc ≤ 20V, –10mA ≤ IO ≤ 0mA 4.8 5.0 5.2 V
Short Circuit Current VO = 0V –150 –15 mA
Soft-Reference
Restart Delay Current V = 2V 10 20 35 µA
Soft Start Current V = 2V –650 –500 –350 µA
Reference Voltage TJ = 25°C, IO = 0A 4.95 5.00 5.05 V
12V ≤ VCC ≤ 20V, –200µA ≤ IO ≤ 200µA 4.85 5.15 V
Line Regulation 12V ≤ VCC ≤ 20V 2 20 mV
Load Regulation –200µA ≤ IO ≤ 200µA 10 30 mV
Error Amplifier (Note 3)
Input Offset Voltage VCM = 5V, Vo = 2V, IO = 0A –10 10 mV
Input Bias Current VCM = 0V –2.0 –0.3 µA
Voltage Gain Vcm = 5V, 0.5V ≤ VO ≤ 3.7V, IO = 0A 70 100 dB
Power Supply Rejection Ratio Vcm = 5V, VO = 2V, 12V ≤ VCC ≤ 20V 70 100 dB
Error Amplifier (Note 3) (cont.)
Common Mode Rejection Ratio 0V ≤ Vcm ≤ 6V, VO = 2V 65 100 dB
VOUT Low VID = –100mV, IO = 200µA 0.17 0.25 V
VOUT High VID = 100mV, IO = –200µA 3.9 4.2 V
Unity Gain Bandwidth (Note 4) 0.5 0.8 MHz
Voltage Controlled Oscillator
Maximum Frequency VID (Error Amp) = 100mV, TJ = 25°C 450 500 550 kHz
VID (Error Amp) = 100mV 425 575 kHz
Minimum Frequency VID (Error Amp) = –100mV, TJ = 25°C 45 50 55 kHz
VID (Error Amp) = –100mV 42 58 kHz
One Shot
Zero Comparator Vth 0.45 0.50 0.55 V
Propagation Delay (Note 4) 120 200 ns
Maximum Pulse Width VZERO = 1V 850 1000 1150 ns
Maximum to Minimum Pulse VZERO = 0V UCx861 – UCx864 2.5 4 5.5
Width Ratio VZERO = 0V UCx865 – UCx868. –55°C to +85°C 4 5.5 7
VZERO = 0V UCx865 – UCx868, +125°C 3.8 5.5 7
Output Stage
Rise and Fall Time CLOAD = 1nF (Note 4) 25 45 ns
Output Low Saturation IO = 20mA 0.2 0.5 V
IO = 200mA 0.5 2.2 V
Output High Saturation IO = –200mA, down from Vcc 1.7 2.5 V
UVLO Low Saturation IO = 20mA 0.8 1.5 V
Fault Comparator
Fault Comparator Vth 2.85 3.00 3.15 V
Delay to Output (Note 4) (Note 5) 100 200 ns

3
 UC1861-1868
UC2861-2868
UC3861-3868

ELECTRICAL CHARACTERISTICS Unless otherwise stated, all specifications apply for –55°C≤TA≤125°C for the
UC186x, –25°C≤TA≤85°C for the UC286x, and 0°C≤TA≤70°C for the UC386x, VCC=12V, CVCO=1nF, Range=7.15k, RMIN=86.6k,
C=200pF, R=4.02k, and Csr=0.1µF. TA=TJ .
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
UVLO
Vcc Turn-on Threshold UCx861, UCx862, UCx865, UCx866 15 16.5 18 V
UCx863, UCx864, UCx867, UCx868 7 8.0 9 V
Vcc Turn-off Threshold UCx861, UCx862, UCx865, UCx866 9.5 10.5 11.5 V
UCx863, UCx864, UCx867, UCx868 6 7.0 8 V
Icc Start VCC = VCC(on) – 0.3V 150 300 µA
Icc Run VID = 100mV 25 32 mA

Note 1: Currents are defined as positive into the pin.

Note 2: Pulse measurement techniques are used to insure that TJ = TA.
Note 3: VID = V(NI) – V(INV).
Note 4: This parameter is not 100% tested in production but guaranteed by design.
Note 5: Vi = 0 to 4V tr(Vi) 10ns tpd = t(Vo = 6V) – t(Vi = 3V)

APPLICATION INFORMATION
UVLO & 5V GENERATOR (See Figure 1): When power The fault pin is input to a high speed comparator with a
is applied to the chip and Vcc is less than the upper threshold of 3V. In the event of a detected fault, the fault
UVLO threshold, Icc will be less than 300µA, the 5V gen- latch is set and the outputs are driven low. If Soft-Ref is
erator will be off, and the outputs will be actively held low. above 4V, the delay latch is set. Restart delay is timed as
When Vcc exceeds the upper UVLO threshold, the 5V Soft-Ref is discharged by 20µA. When Soft-Ref is fully
generator turns on. Until the 5V pin exceeds 4.9V, the discharged, the fault latch is reset if the fault input signal
outputs will still remain low. is low. The Fault pin can be used as a system shutdown
pin.
The 5V pin should be bypassed to signal ground with a
If a fault is detected during soft-start, the fault latch is set
0.1µF capacitor. The capacitor should have low equiva-
and the outputs are driven low. The delay latch will re-
lent series resistance and inductance.
main reset until Soft-Ref charges to 4V. This sets the de-
FAULT AND SOFT-REFERENCE (See Figure 1): The lay latch, and restart delay is timed. Note that restart
Soft-Ref pin serves three functions: system reference, re- delay for a single fault event is longer than for recurring
start delay, and soft-start. Designed to source or sink faults since Soft-Ref must be discharged from 5V instead
200µA, this pin should be used as the input reference for of 4V.
the error amplifier circuit. This pin requires a bypass ca-
The restart delay to soft-start time ratio is 24:1 for a fault
pacitor of at least 0.1µF. This yields a minimum soft-start
occurring during normal operation and 19:1 for faults oc-
time of 1ms.
curring during soft-start. Shorter ratios can be pro-
Under-Voltage Lockout sets both the fault and restart de- grammed down to a limit of approximately 3:1 by the
lay latches. This holds the outputs low and discharges addition of a 20kΩ or larger resistor from Soft-Ref to
the Soft-Ref pin. After UVLO, the fault latch is reset by ground.
the low voltage on the Soft-Ref pin. The reset fault latch
A 100kΩ resistor from Soft-Ref to 5V will have the effect
resets the delay latch and Soft-Ref charges via the 0.5mA
of permanent shut down after a fault since the internal
current source.
20µA current source can't pull Soft-Ref low. This feature
can be used to require recycling Vcc after a fault. Care
must be taken to insure Soft-Ref is indeed low at start up,
or the fault latch will never be reset.
4
 UC1861-1868
UC2861-2868
UC3861-3868
APPLICATION INFORMATION

UDG-92020

UDG-92021-1

Figure 1. UVLO, 5V, fault and soft-ref.

5
 UDG-92022-1

UDG-92023-1

Figure 2. Error Amp, Voltage Controlled Oscillator, and One Shot

6
 UC1861-1868
UC2861-2868
UC3861-3868
APPLICATION INFORMATION
Minimum oscillator frequency is set by Rmin and Cvco. The Error Amplifier directly controls the oscillator fre-
The minimum frequency is approximately given by the quency. E/A output low corresponds to minimum fre-
equation: quency and output high corresponds to maximum
43. frequency. At the end of each oscillator cycle, the RC pin
FMIN ≅ is discharged to one diode drop above ground. At the be-
RMIN • CVCO
ginning of the oscillator cycle, V(RC) is less than Vth1
Maximum oscillator frequency is set by Rmin, Range & and so the output of the zero detect comparator is ig-
Cvco. The maximum frequency is approximately given by nored. After V(RC) exceeds Vth1, the one shot pulse will
the equation: be terminated as soon as the zero pin falls below 0.5V or
3.3 V(RC) exceeds Vth2. The minimum one shot pulse width
FMAX ≅ is approximately given by the equation:
(RMIN / / Range ) • CVCO
Tpw(min) 0.3 R C.
The maximum pulse width is approximately given by:
Tpw(max) 1.2 R C.

STEERING LOGIC

UDG-92013 UDG-92014

The steering logic is configured on the UC1861,63 to result in The steering logic is configured on the UC1862,64 to result in
dual non-overlapping square waves at outputs A & B. This is inverted pulse trains occurring identically at both output pins.
suited to drive dual switch ZVS systems. This is suited to drive single switch ZVS systems. Both outputs
are available to drive the same MOSFET gate. It is advisable
to join the pins with 0.5 ohm resistors.

UDG-92015

The steering logic is configured on the UC1865,67 to result in

alternating pulse trains at outputs A & B. This is suited to drive UDG-92016

dual switch ZCS systems.

The steering logic is configured on the UC1866,68 to result in
non-inverted pulse trains occurring identically at both output
pins. This is suited to drive single switch ZCS systems. Both
outputs are available to drive the same MOSFET gate. It is ad-
visable to join the pins with 0.5 ohm resistors.

7
 UC1861-1868
UC2861-2868
UC3861-3868
APPLICATION INFORMATION (cont.)

UDG-92017

Figure 3. Current waveforms.

UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460

8
 IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated