Lecture No.

Course Name Electronic (3)

CMOS VLSI Design

Lecture 3-2: CMOS Transistor Theory

Instructor Dr. Samia Heshmat

Credits: David Harris
Harvey Mudd College

(Material taken/adapted from Harris’ lecture notes)

email [email protected] CMOS VLSI Design 14 October 2024

 Outline
❑ Introduction
❑ MOS Capacitor
❑ nMOS I-V Characteristics
❑ pMOS I-V Characteristics
❑ Gate and Diffusion Capacitance
❑ Pass Transistors
❑ RC Delay Models

CMOS VLSI Design Slide 2

 Introduction
❑ So far, we have treated transistors as ideal switches
❑ An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
❑ Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed
❑ Also explore what a “degraded level” really means

CMOS VLSI Design Slide 3

 Introduction
❑ The MOS transistor is a majority-carrier device in
which the current in a conducting channel between
the source and drain is controlled by a voltage
applied to the gate.

❑ nMOS transistor, the majority carriers are electrons;

in a pMOS transistor, the majority carriers are holes.

❑ The behavior of MOS transistors can be understood

by first examining an isolated MOS structure with a
gate and body but no source or drain.

CMOS VLSI Design Slide 4

 MOS Capacitor
❑ Gate and body form Vg < 0
polysilicon gate
silicon dioxide insulator
MOS capacitor +
- p-type body

(a)
❑ Operating modes
– Accumulation 0<V <V g t
depletion region
+
negative voltage is -

applied to the gate.

– Depletion (b)

small positive voltage V > V g t

is applied to the gate +

inversion region
depletion region
-
– Inversion
(c)

CMOS VLSI Design Slide 5

 Terminal Voltages
❑ Mode of operation depends on Vg, Vd, Vs Vg

– Vgs = Vg – Vs Vgs
+ +
Vgd
– Vgd = Vg – Vd - -

– Vds = Vd – Vs = Vgs - Vgd Vs

-
Vds +
Vd

❑ Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds  0
❑ nMOS body is grounded. First assume source is 0 too.
❑ Three regions of operation
– Cutoff
– Linear
– Saturation

CMOS VLSI Design Slide 6

 nMOS Cutoff
❑ No channel Vgs = 0 Vgd
+ g +
❑ Ids = 0 - -
s d

n+ n+

p-type body
b

⚫ The Vgs < Vt → Vds have free electrons.

⚫ The body has free holes but no free electrons.
⚫ Suppose the source is grounded. The junctions between the body
and the source or drain are zero-biased or reverse-biased, so little or
no current flows. We say the transistor is OFF, and this mode of
operation is called cutoff

CMOS VLSI Design Slide 7

 nMOS Linear
❑ Channel forms Vgs > Vt
Vgd = Vgs
❑ Current flows from d to s +
-
g +
-
– e- from s to d s d
n+ n+ Vds = 0
❑ Ids increases with Vds and Vgs
p-type body
❑ Similar to linear resistor b

⚫ Vgs > Vt. Now an inversion region of

Vgs > Vt
electrons called the channel connects g
Vgs > Vgd > Vt
+ +
the source and drain, creating a - - Ids
s d
conductive path and turning the
n+ n+
transistor ON. 0 < Vds < Vgs-Vt

⚫ The number of carriers and the p-type body

b
conductivity increases with the gate
voltage.
⚫ When a small positive Vds is applied to the drain current Ids flows through the
channel from drain to source. This mode of operation is termed linear
CMOS VLSI Design Slide 8
 nMOS Saturation
❑ Channel pinches off Vgs > Vt
+ g
+
Vgd < Vt

- -
❑ Ids independent of Vds s d Ids

❑ We say current saturates n+ n+

Vds > Vgs-Vt
p-type body
❑ Similar to current source b

• If Vds becomes sufficiently large that Vgd < Vt , the channel is no

• longer inverted near the drain and becomes pinched off - but
conduction is still brought about by the drift of electrons under the
influence of the positive drain voltage.
• Above this drain voltage the current Ids is controlled only by the
gate voltage and stop to be influenced by the drain. This mode is
called saturation.

CMOS VLSI Design Slide 9

 regions of operation
The nMOS transistor has three modes of operation.
❑If Vgs < Vt , the transistor is cutoff (OFF).
❑If Vgs > Vt , the transistor turns ON. If Vds is small, the transistor
acts as a linear resistor in which the current flow is proportional to
Vds.
❑If Vgs > Vt and Vds is large, the transistor acts as a current
source (saturation region) in which the current flow becomes
independent of Vds .
❑The majority carriers flow from their source to their drain.
Because electrons are negatively charged, the source of an nMOS
transistor is the more negative of the two terminals. Holes are
positively charged so the source of a pMOS transistor is the more
positive of the two terminals.

CMOS VLSI Design Slide 10

 I-V Characteristics
❑ In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

CMOS VLSI Design Slide 11

 Channel Charge
❑ MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
❑ Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 12

 Channel Charge
❑ MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
❑ Qchannel = CV
❑ C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 13

 Channel Charge
❑ MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
❑ Qchannel = CV
❑ C = Cg = oxWL/tox = CoxWL Cox = ox / tox
❑ V=
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 14

 Channel Charge
❑ MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
❑ Qchannel = CV
❑ C = Cg = oxWL/tox = CoxWL Cox = ox / tox
❑ V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design Slide 15

 Carrier velocity
❑ Charge is carried by e-
❑ Carrier velocity v proportional to lateral E-field
between source and drain
❑ v=

CMOS VLSI Design Slide 16

 Carrier velocity
❑ Charge is carried by e-
❑ Carrier velocity v proportional to lateral E-field
between source and drain
❑ v = E  called mobility
❑ E=

CMOS VLSI Design Slide 17

 Carrier velocity
❑ Charge is carried by e-
❑ Carrier velocity v proportional to lateral E-field
between source and drain
❑ v = E  called mobility
❑ E = Vds/L
❑ Time for carrier to cross channel:
– t=

CMOS VLSI Design Slide 18

 Carrier velocity
❑ Charge is carried by e-
❑ Carrier velocity v proportional to lateral E-field
between source and drain
❑ v = E  called mobility
❑ E = Vds/L
❑ Time for carrier to cross channel:
– t=L/v

CMOS VLSI Design Slide 19

 nMOS Linear I-V
❑ Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross

I ds =

CMOS VLSI Design Slide 20

 nMOS Linear I-V
❑ Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
=

CMOS VLSI Design Slide 21

 nMOS Linear I-V
❑ Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
= Cox
W V − V − Vds V
 gs t  ds
L 2 
W
=  Vgs − Vt − ds Vds
V  = Cox
 2 L

CMOS VLSI Design Slide 22

 nMOS Saturation I-V
❑ If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
❑ Now drain voltage no longer increases current

I ds =

CMOS VLSI Design Slide 23

 nMOS Saturation I-V
❑ If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
❑ Now drain voltage no longer increases current

I ds =  Vgs − Vt − dsat V
V
 dsat
 2 
❑ The geometry and technology-dependent
parameters are sometimes merged into a single
factor β.

CMOS VLSI Design Slide 24

 nMOS Saturation I-V
❑ If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
❑ Now drain voltage no longer increases current

I ds =  Vgs − Vt − dsat V
V
 dsat
 2 

( − Vt )
2
= Vgs
2

CMOS VLSI Design Slide 25

 nMOS I-V Summary
❑ Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds =   Vgs − Vt −  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2

CMOS VLSI Design Slide 26

 Example
❑ Consider a 0.6 m process
– From AMI Semiconductor
– tox = 100 Å 2.5
Vgs = 5
–  = 350 cm2/V*s 2
– Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)
❑ Plot Ids vs. Vds 1
– Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 3

– Use W/L = 4/2 

Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
W  3.9 • 8.85  10−14   W  W Vds
 = Cox = ( 350)  −8  L  = 120  A /V 2
L  100  10   L

CMOS VLSI Design Slide 27

 pMOS I-V
❑ All dopings and voltages are inverted for pMOS
❑ Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2/V*s in AMI 0.6 m process
❑ Thus pMOS must be wider to provide same current
– In this class, assume n / p = 2, if not stated.

CMOS VLSI Design Slide 28

 Summary of Shockley model

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9)
p-type body


 0 Vgs  Vt cutoff


I ds =   Vgs − Vt − ds V V  V
V
 ds linear
  
2 ds dsat

 
( gs t )
2
 V − V Vds  Vdsat saturation
2

for nMOS for pMOS

CMOS VLSI Design Slide 29