Lecture No.

Course Name Electronic (3)

CMOS VLSI Design

Lecture 4-2: CMOS Transistor Theory

Instructor Dr. Samia Heshmat
Credits: David Harris
Harvey Mudd College

(Material taken/adapted from Harris’ lecture notes)

email [email protected] CMOS VLSI Design 21 October 2024

 Nonideal Transistor Behavior

❑ Nonideal Transistor Behavior

– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
❑ Process and Environmental Variations

CMOS VLSI Design 2

 Alpha model
 0 Vgs  Vt cutoff

 V
I ds =  I dsat ds Vds  Vdsat linear
 Vdsat
 I dsat Vds  Vdsat saturation


( − Vt )

I dsat = Pc V gs
2
Vdsat = Pv (Vgs − Vt )
 /2

Pc, Pv and alpha are found by fitting the model to the empirical
modeling results

CMOS VLSI Design Slide 3

Channel Length Modulation
❑ Ideally, Ids is independent of Vds for a transistor in saturation,
making the transistor a perfect current source.
❑ Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
GND VDD VDD

❑ Shorter Leff gives more current Source Gate Drain

Depletion Region
Width: Ld
– Ids increases with Vds
– Even in saturation n L n
+ Leff +
p GND bulk Si

CMOS VLSI Design 4

Channel Length Modulation
❑ Ideally, Ids is independent of Vds for a transistor in saturation,
making the transistor a perfect current source.
❑ Reverse-biased p-n junctions form a depletion region
– Region between n and p with no carriers
– Width of depletion Ld region grows with reverse bias
– Leff = L – Ld
GND VDD VDD

❑ Shorter Leff gives more current Source Gate Drain

Depletion Region
Width: Ld
– Ids increases with Vds
– Even in saturation n L n
+ Leff +
p GND bulk Si

CMOS VLSI Design 5

 Chan Length Mod I-V


( − Vt ) (1 + Vds )
2
I ds = Vgs
2

❑  = channel length modulation coefficient

– not feature size
– Empirically fit to I-V characteristics

CMOS VLSI Design 6

 Threshold Voltage Effects
❑ Vt is Vgs for which the channel starts to invert
❑ Ideal models assumed Vt is constant
❑ Really depends (weakly) on almost everything else:
– Body voltage: Body Effect
– Drain voltage: Drain-Induced Barrier Lowering
– Channel length: Short Channel Effect

CMOS VLSI Design 7

 Body Effect
❑ Body is a fourth transistor terminal
❑ Vsb affects the charge required to invert the channel
– Increasing Vs or decreasing Vb increases Vt
Vt = Vt 0 +  ( s + Vsb − s )
❑ s = surface potential at threshold
NA
s = 2vT ln
ni
– Depends on doping level NA
– And intrinsic carrier concentration ni
❑  = body effect coefficient
tox 2q si N A
= 2q si N A =
 ox Cox

CMOS VLSI Design 8

 Body Effect Cont.
❑ For small source-to-body voltage, treat as linear

CMOS VLSI Design 9

 DIBL
❑ drain-induced barrier lowering (DIBL)
❑ Electric field from drain affects channel
❑ More pronounced in small transistors
where the drain is closer to the
VVV=−
ttds

channel
– Drain voltage also affect Vt

Vt = Vt − Vds
❑ High drain voltage causes current to
increase.

CMOS VLSI Design 10

 DIBL
❑ drain-induced barrier lowering (DIBL)
❑ Electric field from drain affects channel
❑ More pronounced in small transistors
where the drain is closer to the
VVV=−
ttds

channel
– Drain voltage also affect Vt

Vt = Vt − Vds
❑ High drain voltage causes current to
increase.

CMOS VLSI Design 11

 Short Channel Effect
❑ In small transistors, source/drain depletion regions
extend into the channel
– Impacts the amount of charge required to invert
the channel
– And thus makes Vt a function of channel length
❑ Short channel effect: Vt increases with L
– Some processes exhibit a reverse short channel
effect in which Vt decreases with L

CMOS VLSI Design 12

 Leakage
❑ What about current in cutoff?
❑ Simulated results
❑ What differs?
– Current doesn’t
go to 0 in cutoff

CMOS VLSI Design 13

 Leakage
❑ What about current in cutoff?
❑ Simulated results
❑ What differs?
– Current doesn’t
go to 0 in cutoff

CMOS VLSI Design 14

 Leakage Sources
❑ Subthreshold conduction
– Transistors can’t abruptly turn ON or OFF
– Dominant source in contemporary transistors
❑ Gate leakage
– Tunneling through ultrathin gate dielectric
❑ Junction leakage
– Reverse-biased PN junction diode current

CMOS VLSI Design 15

 Subthreshold Leakage
❑ Subthreshold leakage exponential with Vgs
Vgs −Vt 0 +Vds − k Vsb
 −Vds

I ds = I ds 0 e nvT
1 − e vT 
 
 
❑ n is process dependent
– typically 1.3-1.7
❑ Rewrite relative to Ioff on log scale

❑ S ≈ 100 mV/decade @ room temperature

CMOS VLSI Design 16

 Gate Leakage
❑ Carriers tunnel thorough very thin gate oxides
❑ Exponentially sensitive to tox and VDD

– A and B are tech constants

– Greater for electrons
• So nMOS gates leak more
❑ Negligible for older processes (tox > 20 Å)
From [Song01]

❑ Critically important at 65 nm and below (tox ≈ 10.5 Å)

CMOS VLSI Design 17

 Junction Leakage
❑ Reverse-biased p-n junctions have some leakage
– Ordinary diode leakage
– Band-to-band tunneling (BTBT)
– Gate-induced drain leakage (GIDL)

p+ n+ n+ p+ p+ n+

n well
p substrate

CMOS VLSI Design 18

 Diode Leakage
❑ Reverse-biased p-n junctions have some leakage
 VvD 
I D = I S  e − 1
T

 
 
❑ At any significant negative diode voltage, ID = -Is
❑ Is depends on doping levels
– And area and perimeter of diffusion regions
– Typically < 1 fA/m2 (negligible)

CMOS VLSI Design 19

 Band-to-Band Tunneling
❑ Tunneling across heavily doped p-n junctions
– Especially sidewall between drain & channel
when halo doping is used to increase Vt
❑ Increases junction leakage to significant levels

– Xj: sidewall junction depth

– Eg: bandgap voltage
– A, B: tech constants

CMOS VLSI Design 20

Gate-Induced Drain Leakage
❑ Occurs at overlap between gate and drain
– Most pronounced when drain is at VDD, gate is at
a negative voltage
– Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

CMOS VLSI Design 21

Temperature Sensitivity
❑ Increasing temperature
– Reduces mobility
– Reduces Vt
❑ ION decreases with temperature
❑ IOFF increases with temperature

I ds

increasing
temperature

Vgs

CMOS VLSI Design 22

Temperature Sensitivity
❑ Increasing temperature
– Reduces mobility
– Reduces Vt
❑ ION decreases with temperature
❑ IOFF increases with temperature

I ds

increasing
temperature

Vgs

CMOS VLSI Design 23

 So What?
❑ So what if transistors are not ideal?
– They still behave like switches.
❑ But these effects matter for…
– Supply voltage choice
– Logical effort
– Quiescent power consumption
– Pass transistors
– Temperature of operation

CMOS VLSI Design 24

 Parameter Variation
❑ Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
❑ Fast (F)

fast
FF
SF

– Leff: short

pMOS
TT

– Vt: low
– tox: thin
FS
SS

slow
❑ Slow (S): opposite slow fast
nMOS
❑ Not all parameters are independent
for nMOS and pMOS

CMOS VLSI Design 25

 Parameter Variation
❑ Transistors have uncertainty in parameters
– Process: Leff, Vt, tox of nMOS and pMOS
– Vary around typical (T) values
❑ Fast (F)

fast
FF
SF

– Leff: short

pMOS
TT

– Vt: low
– tox: thin
FS
SS

slow
❑ Slow (S): opposite slow fast
nMOS
❑ Not all parameters are independent
for nMOS and pMOS

CMOS VLSI Design 26

Environmental Variation
❑ VDD and T also vary in time and space
❑ Fast:
– VDD: high
– T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C

CMOS VLSI Design 27

Environmental Variation
❑ VDD and T also vary in time and space
❑ Fast:
– VDD: high
– T: low

Corner Voltage Temperature

F 1.98 0C
T 1.8 70 C
S 1.62 125 C

CMOS VLSI Design 28

 Process Corners
❑ Process corners describe worst case variations
– If a design works in all corners, it will probably
work for any variation.
❑ Describe corner with four letters (T, F, S)
– nMOS speed
– pMOS speed
– Voltage
– Temperature

CMOS VLSI Design 29

 Important Corners
❑ Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold F F F S
leakage

CMOS VLSI Design 30

 Important Corners
❑ Some critical simulation corners include

Purpose nMOS pMOS VDD Temp

Cycle time S S S S

Power F F F F

Subthreshold F F F S
leakage

CMOS VLSI Design 31

 Process variations
Both MOSFETs have 30nm channel with 130
dopant atoms in the channel depletion region

threshold voltage 0.97V threshold voltage 0.57V

Process variations impact gate length, threshold
voltage, and oxide thickness
CMOS VLSI Design Slide 32