Received February 8, 2022, accepted February 21, 2022, date of publication February 24, 2022, date of current version

March 11, 2022.

Digital Object Identifier 10.1109/ACCESS.2022.3154014

Modeling and Simulation of System Bus and

Memory Collisions in Heterogeneous SoCs
JOOHO WANG 1 , YUNGYU GIM2 , SUNGKYUNG PARK 3 , (Senior Member, IEEE),
AND CHESTER SUNGCHUNG PARK 1 , (Senior Member, IEEE)
1 Department of Electrical and Electronics Engineering, Konkuk University, Seoul 05029, South Korea
2 System LSI Business, Samsung Electronics, Inc., Hwaseong-si, Gyeonggi-do 18448, South Korea
3 Department of Electronics Engineering, Pusan National University, Busan 46241, South Korea

Corresponding author: Chester Sungchung Park ([email protected])

This work was supported by the Samsung Research Funding and Incubation Center, Samsung Electronics, under Project SRFC-IT1802-10.

ABSTRACT A system simulator is proposed and developed, which can help to optimize design parameters
and hence minimize the number of collisions. In order to search the optimal design parameter combi-
nation which meets the user requirement, the proposed simulator has some knobs: partitioning between
software and hardware, scheduling the operations in the system, and memory merging, all of which can be
adjusted to predict collisions and search the optimal architecture. Also, design parameters can be adjusted
sequentially to cover all design options and estimate the predicted performance for each option. The
proposed system simulator is evaluated with an example signal processing algorithm, orthogonal matching
pursuit (OMP) algorithm. Performances of four cases of the OMP algorithm are predicted by the proposed
simulator and in turn are compared with the actual performances on ZedBoard. The proposed simulator
can predict the performance of heterogeneous systems on chips with under 5% error for all the candidate
architectures for OMP while taking the system bus and memory conflicts into account. Moreover, the
optimized heterogeneous SoC architecture for the OMP algorithm improves performance by up to 32%
compared with the conventional CAG-based approach. The proposed simulator is verified that the proposed
performance estimation algorithm is generally applicable to estimate the performance of any heterogeneous
SoC architecture. For example, the estimation error is measured to be no more than 5.9% for the convolutional
layers of CNNs and no more than 5.6% for the LDPC-coded MIMO-OFDM. In addition, the optimized
heterogeneous SoC architecture improves performance by up to 48% for the third convolutional layer of
AlexNet and 56% for the LDPC-coded MIMO-OFDM. Lastly, compared with the conventional simulation-
based approaches, the proposed estimation algorithm provides a speedup of one to two orders of magnitudes.
The source code is available on the GitHub repository: https://github.com/SDL-KU/HetSoCopt.

INDEX TERMS Collision, conflict, design space exploration, hardware accelerator, heterogeneous SoC,
modeling, performance prediction and estimation, system simulator.

I. INTRODUCTION than sequential operations [1]. The field programmable gate

Demand for heterogeneous systems on chips (SoCs) is array (FPGA) [2], the application-specific integrated circuit
increasing these days owing to the impending end of Moore’s (ASIC) [3], and the graphics processing unit (GPU) [4] in
law and Dennard scaling. A heterogeneous SoC includes a broad sense are some examples to implement parallel-
more than one hardware accelerator which is dedicated to processing hardware accelerators. Owing to the superiority
intensive computation such as a large volume of convo- of the hardware accelerator in a specific domain over the
lution operations or matrix multiply operations. Hardware processor, the number of hardware accelerators is increasing
accelerators can supplement processors and enhance the these days [5].
overall system performance by adopting parallelism rather Meanwhile, hardware accelerators need more time for their
development and verification and have lower flexibility, com-
The associate editor coordinating the review of this manuscript and pared with software. Moreover, interface circuits are added to
approving it for publication was Fabrizio Messina . connect hardware accelerators to the on-chip interconnect or
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
For more information, see https://creativecommons.org/licenses/by-nc-nd/4.0/
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bus and the paths of data becomes more complex. In turn, algorithm can predict the communication performance of CSs
leveraging hardware accelerators to enhance the system per- more accurately than conventional performance estimation
formance may make the system bus more complicated and algorithms. In [11], a revised roofline model was proposed
increase data collisions in memory and the system bus. Con- to estimate the performance of a DMA-controlled accelerator,
sequently, the actual performance of the overall system can considering the impact of DRAM latency. The roofline model
be quite lower than the predicted performance if memory and proposed in [11] was verified using the Zynq platform.
system bus collisions are not properly taken into account. In this work, a system simulator which can predict the per-
Thus predicting the collisions in the system bus and memory formance of heterogeneous SoCs and model dynamic effects
and obtaining the system performance at early stages are such as collisions is proposed. Static analysis-based tech-
important. For these, a system simulator is needed, which niques typically provide sufficient efficiency in terms of time
can help to optimize design parameters and hence minimize cost but the accuracy is low. On the other hand, simulation-
the number of collisions. To reduce design turnaround time based techniques may generally provide satisfactory accu-
and also explore system level trade-offs of SoCs, design racy at the expense of lower efficiency than static analysis
space exploration and performance prediction by using sys- based techniques. The proposed simulator can help optimize
tem simulators early in the design flow are indispensable for design parameters and accordingly minimize the number of
successful SoC prototyping. conflicts or collisions while exploring a large design space.
The Zynq platform [6] is widely used to verify many Both speed and accuracy are valued by rapid design space
heterogeneous SoC simulators [7]-[11]. The Zynq platform exploration and consideration of dynamic effects such as col-
has a dual-core ARM processor tightly coupled with a field- lisions. To search the optimal design parameter combination
programmable gate array (FPGA). The FPGA can be used which meets the user requirement, the proposed simulator has
as a reconfigurable accelerator to efficiently implement some some knobs (based on the information extracted from the tar-
hardware functionality. The ARM side of the SoC is known as get system): partitioning between software and hardware (or
a processing system (PS), whereas the FPGA side is termed mapping operations into software or hardware), scheduling
programmable logic (PL). When an application is ported to the operations (or changing the order of operations) in the
the Zynq SoC, it can run as a pure software implementation system, and memory merging (separate memories or shared
on the PS. To gain performance, compute-bound parts of an memory), all of which can be adjusted to predict collisions.
application can be mapped as hardware accelerators on the Also, design parameters can be adjusted sequentially to cover
PL. For example, [7] predicted the performance of a het- all design options and estimate the predicted performance for
erogeneous SoC consisting of a DMA-controlled hardware each option. The simulator proposed in this study utilizes the
accelerator, a single processor core, a DRAM subsystem, and extracted time information (some knobs) for each component
on-chip buses using a SystemC TLM-based simulator. The such as a direct memory access (DMAC) controller, processor
results predicted using the SystemC TLM simulator were core, and on-chip bus through emulation based on the Zynq
compared with those obtained using the Zynq platform. [8] platform [6]. When the target application is implemented in
introduced gem5-aladdin, which integrates the gem5 system the Altera/Intel SoC platform [13], if the time information
simulator with the Aladdin accelerator simulator to enable of the Altera/Intel SoC platform is extracted in pre-measured
the simulation of SoCs with complex accelerator system and applied to the proposed simulator, the performance of the
interactions. The gem5-aladdin simulator showed that it val- target application implemented in Altera/Intel SoC Platform
idated against the Xilinx Zynq platform and achieved less can be easily predicted.
than 6% error. Specifically, the gem5-aladdin simulator mea- The proposed simulator in this study is used to seek the
sured and utilized the execution time information of the optimal condition which meets the system requirement, while
ZedBoard [12] for the CPU (i.e., Cortex-A9) to model the using minimal number of hardware accelerators. Pipelining is
cache line latency. In [9], the requirements for memory, assumed for the implementation of a given algorithm which
computation, and flexibility of the system were summarized is subdivided into multiple steps of operations. The SoC
for mapping a CNN on embedded FPGAs. Based on these performance is predicted while the allocation of operations
requirements, they proposed Angel-Eye, a programmable and to hardware accelerators and processors is changed and the
flexible CNN accelerator architecture simulator, along with a order of operations is adjusted, whereby the types of colli-
data quantization strategy and compilation tool. The design sions will vary. Namely, both partitioning and scheduling are
strategy obtained using the Angel-Eye simulator [9] was considered in the proposed simulator to recommend some
implemented on the Zynq platform, and the actual perfor- design parameter combinations to achieve the optimal sys-
mance gains were evaluated. Next, [10] proposed a perfor- tem performance. The execution time of each operation step
mance estimation algorithm to optimize the communication varies as the partitioning varies and the type of data collision
schemes (CSs), which are defined by the number of direct varies (and hence the execution time) as the scheduling varies.
memory access controllers (DMACs) and the bank alloca- The proposed system simulator is evaluated with an exam-
tion of DRAM. Using the communication bandwidths of ple compressive sensing algorithm, orthogonal matching pur-
CPs obtained from prior full-system simulations based on suit (OMP), which is subdivided into 5 steps. The OMP
the Zynq platform, the proposed performance estimation algorithm estimates the channel in the LTE wireless standard

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with a 5MHz channel bandwidth and multiple hardware II. RELATED WORK
accelerators are employed to implement the algorithm. The A multitude of studies have addressed design space explo-
data type, the size of data, the order of data, the access ration and performance estimation of heterogeneous SoC
type (read or write), and timing parameters are the inputs architectures [14]–[18]. Scheduling and timing analysis of
to the simulator. Performances of 4 cases of the OMP algo- on-chip communication, factoring in software parts such as
rithm are predicted by the simulator and those are compared interrupt service routines and device drivers were presented
with the measured performance in ZedBoard with the Xilinx in [14], [15], wherein the buffer resource, bus contentions,
Zynq 7020 SoC chip [12]. The execution time of the optimal and bus sharing were also taken into consideration to enhance
OMP architecture, obtained from the proposed simulator, is accuracy. In [16], a static performance estimation method
10295 cycles whereas the execution time from the actual was used to first reduce a large design space, and then
implementation on ZedBoard with the Zynq SoC chip is the reduced space was explored using a trace-driven mem-
10788 cycles, leading to a 4.8% error. The proposed system ory simulator to select the optimal on-chip communication
simulator can predict the performance of heterogeneous SoCs architecture. Because memory accesses are involved in bus
with under 5% error while taking the system bus and memory contention, memory allocation was also considered in [16].
collisions into account. Moreover, the proposed simulator is In today’s complex heterogeneous embedded SoC design, it is
verified that the proposed performance estimation algorithm imperative to model and simulate the system of interest at a
is generally applicable to estimate the performance of any high level. A methodology and framework to perform this
heterogeneous SoC architecture. For example, the estima- with analytical modeling and multi-objective optimization
tion error is measured to be no more than 5.9% for the were presented in [17], wherein candidate architectures were
convolutional layers of CNNs and no more than 5.6% for explored at different levels of abstraction. Dataflow graphs
the LDPC-coded MIMO-OFDM. Moreover, the optimized in [17] represented the transformation of coarse-grained
heterogeneous SoC architecture improves performance by up events in an application into fine-grained events in the archi-
to 48% for the third convolutional layer of AlexNet and 56% tecture. A system-level modeling and simulation environment
for the LDPC-coded MIMO-OFDM. was specified in [18], wherein pruning of the design space and
We summarize the novelty of this study as follows: calibration of timing parameters by coupling with low-level
• We propose a novel system simulator to optimize a simulators or prototype implementations were discussed.
heterogeneous SoC, which is defined by the number of In our work on heterogeneous SoC modeling and simu-
hardware accelerators and processors. The novel perfor- lation, we assumed a bus compliant with the AMBA AXI
mance estimation algorithm of the simulator proposed bus protocol [19]. In [10] and [20], a SystemC TLM-based
herein evaluates the performance of a heterogeneous simulator was used to evaluate and predict the performance
SoC architecture, based on the timing information of of a hardware accelerator implemented with an AXI bus-
accelerators and processors, measured on commercial based SoC architecture based on memory access modeling,
SoC platforms, such as the Zynq 7020 SoC chip on including the memory access type, burst type, and access
ZedBoard [12] and AccTLMSim [7]. latency. In [21], the design space for the AMBA hierarchical
• The performance estimation algorithm of the proposed shared bus was explored, and the execution time of each bus
simulator can search the design space by reflecting architecture was estimated by pipelining and accounting for
all combinations of memory merging, hardware- burst transactions. The execution order and amount of transfer
software partitioning, and scheduling to find the opti- data were also considered during design space exploration.
mal heterogeneous SoC architecture. In addition, the However, dynamic effects such as scheduling and hardware-
proposed performance estimation algorithm primarily software partitioning at the memory and system bus were not
considers the performance impact of both the mem- taken into account in [10], [20], [21].
ory latency and bus protocol overhead on a hardware A performance estimation method based on a tree model
accelerator. was presented in [22] to determine the relationship between
SoC parameters and performance, as well as to improve the
The paper is organized as follows. Section II reviews some
prediction accuracy during design space exploration, using
of the related works and summarize our contributions. System
parameter ranking to guide the design. A high-level ana-
modeling preliminaries are accounted for in Section III where
lytical tool to evaluate the communication and computation
the system, the bus, and data transfer types are addressed, fol-
overheads of heterogeneous systems was presented in [23],
lowed by transfer delay types which are extensively explained
wherein dataflow and loop pipelining within the high-level
in particular. Section IV deals with the performance estima-
synthesis framework were considered with the assumption of
tion process of the performance estimation method in terms of
an AXI4 stream protocol. In [23], dynamic data dependencies
modeling using an example of a signal processing algorithm.
were considered, and the communication and computation
Simulation methods, results, and analysis are elaborated on
times were estimated. A design space exploration method was
in Section V with case studies. Finally, the conclusion and
introduced in [24] with task scheduling, which is based on
future work are given in Section VI.
a traffic-aware priority-based earliest-finish-time algorithm,

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to achieve a high level of core utilization. Guidance on how modeled the communication bandwidth of a DMA-controlled
to offer a well-designed scratchpad on-chip memory system accelerator from/to the DRAM subsystem through an on-
in terms of memory capacity and number of memory banks chip bus on a transaction level. However, a simulation-based
was provided in [24]. There have been several reports on the approach may often be too time-consuming to explore a broad
optimization of the bank allocation of DRAM [25], [26] in design space for communication architectures.
a heterogeneous SoC architecture. Most proposed bank allo- We summarize the contributions of this study as follows:
cations focus on balancing interference mitigation and bank- • In order to improve the performance of the hetero-
level parallelism. For example, in [25], DRAM banks were geneous SoC architecture, compared with that of a
dynamically partitioned according to application profiling CAG-based optimization [14], which considers only
(e.g., memory-intensive vs. non-intensive). In [26], locality- memory merging, the proposed simulator considers
aware bank partitioning (LABP) was proposed to improve both hardware-software partitioning and scheduling.
dynamic bank partitioning by mitigating the inference caused The optimal combination of design options suggested
by non-intensive applications, for example, by separating by the proposed simulator can improve the perfor-
their banks from that of memory-intensive high-row buffer mance of a heterogeneous SoC architecture by up
locality applications. However, the proposed bank allocations to 32
are targeted at general-purpose processors (e.g., CPUs) run- • Compared with the conventional simulation-based [7]
ning different applications. Specifically, optimization of bank approach, the proposed performance-estimation algo-
allocation for application-specific hardware accelerators has rithm provides a speedup of two orders of magnitude.
not been considered. The simulation-based approach is sufficiently accu-
When it comes to the estimation of communication rate to capture the dynamic nature of the communica-
performance, there are two different approaches: static tion bandwidth, but it often takes a prohibitively long
analysis-based approach and simulation-based approach. The time to simulate. According to our experiments, the
static analysis-based approach tends to be faster than the conventional simulation-based approach takes at least
simulation-based approach, but the estimation accuracy may a few hours to evaluate a single heterogeneous SoC
not be sufficiently high to drive the design of communication architecture with hundreds of different combinations of
architectures. In particular, the static analysis-based approach hardware-software partitioning, memory merging, and
cannot accurately capture the dynamic nature of communica- scheduling. Using the conventional simulation-based
tion bandwidth. To improve accuracy, a static analysis-based approach, we run the full-system simulator proposed
approach is often combined with a set of traces extracted in [7], once for each design point, taking approxi-
from simulations. In [14], a hybrid trace-based performance mately 12.5 seconds per design point. By contrast,
estimation algorithm was proposed to estimate the perfor- to minimize the simulation time and maintain esti-
mance of bus-based communication architectures using a mation accuracy, the proposed performance estimation
communication analysis graph (CAG). In [27], a simulation- algorithm constrains the use of an evaluation board
based performance estimation was proposed based on the (e.g., ZedBoard [12]) to evaluate the time information
observation of actual traffic tracking of the application of of the heterogeneous SoC architecture. Because a few
each core (e.g., bus master). In [28], in order to estimate tens of time information are sufficient to express most of
the performance of bus-based communication architectures, the heterogeneous SoC architectures of interest, the extra
a static analysis based on a modified queueing model was simulation time required to obtain the time information
incorporated into the schedule-aware performance estima- of each hardware component becomes negligible, par-
tion. [29] proposes to estimate the memory latency based on ticularly in the case of broad design space (i.e., a space
the statistics of different access conditions. In [30], bus-based of hundreds of design points).
on-chip communication architectures were explored early in • Compared with static analysis-based bus performance
the design flow using a modeling abstraction, called the cycle estimation [28] and statistics-based estimation [29], the
count accurate at transaction boundaries. The abstraction proposed performance estimation algorithm can predict
used in [30] can speed up the simulation by a factor of 2 when the communication performance of heterogeneous SoC
compared with the bus cycle accurate abstractions. However, architectures more accurately because it considers both
in [27]–[30], neither the dynamic effects such as collisions or the bus protocol overhead (bus conflict) and memory
conflicts at the memory and the system bus, nor the operation latency (memory collision) using an evaluation board
scheduling was considered. (e.g., ZedBoard [12]) to evaluate the time information
However, the simulation-based approach is sufficiently of the hardware and software. The experimental results
accurate to capture the dynamic communication bandwidth. show that the proposed algorithm approaches the full-
Thus, most reports on bank allocation rely on performance system simulator [7] more closely than the conven-
evaluation using full-system simulators in conjunction with tional algorithms. For example, the proposed algorithm
DRAM simulators. For example, in [25], the proposed reduced the estimation error to 6%, whereas the conven-
bank allocations were evaluated using gem5 in conjunction tional algorithms in [28] and [29] experienced estima-
with open DRAM simulator. In [7], a full-system simulator tion errors of 18% and 16%, respectively.

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III. BASICS OF SYSTEM MODELING

In this section, modeling of systems consisting of masters,
buses, and slaves is described along with operating principles
and data transfer types. Based on these and performance
estimation methods which will be explained in Section IV,
the system simulator is developed and simulation results are
obtained to predict the system performance.

A. SYSTEM UNDER CONSIDERATION

A basic system is shown in Figure 1, where a master is a
processor or a direct memory access (DMA) controller and
a slave is a memory or a hardware accelerator which can run
operations. The number of masters and slaves is allowed to
vary and a single bus is assumed between masters and slaves. FIGURE 1. Basic system structure.
The slave is organized as first in first out (FIFO) and is
subdivided into a hardware (HW) block and an AXI slave
wrapper (assuming the bus complies with the AMBA AXI
protocol [19]), as shown in Figure 2. The hardware block
takes charge of operations or computation. The AXI slave
wrapper enables operations, synchronizes input and output,
and supports multiple outstanding transactions. The AXI
protocol uses valid and ready handshake signals to con-
firm the data transfer is completed. The enable signal is
generated by using valid and ready signals. A counter has
a pre-determined number of input data, which triggers the
operation, and a predetermined number of output data, which
is produced as an outcome of the operation. The counter
conducts sync between input and output such that the oper- FIGURE 2. Slave (hardware accelerator) structure.
ation gets started only after a preset number of input data is
received and the operation produces a preset number of output
data after a delay. The values set up in the counter can be data from leaving). In the read delay case when the master is
adjusted in. For example, when it comes to the target appli- not ready to send data at the right moment and thus RREADY
cation implemented in the heterogeneous SoC architecture is deasserted, WREADY is deasserted to immediately prevent
is LDPC-coded MIMO-OFDM, the amount of communica- data from entering the slave.
tion and computation required for each hardware accelerator According to the number of address channels and the num-
differs based on the number of spatial streams (NSS) and ber of data channels, the bus is categorized into shared address
the modulation coding scheme (MCS). In this case, during bus and shared data bus (SASD), shared address bus and
the initial design stage of each hardware accelerator, the multiple data buses (SAMD), and multiple address buses and
maximum value of the counter is set differently so that it can multiple data buses (MAMD) [31], [32]. The SASD mode has
respond to the change in the communication amount accord- one address channel and one data channel, where one master
ing to the determined NSS and MCS. The counter in Figure 2 is unable to occupy the bus while another occupies it. The
confirms the input by using WVALID and WREADY signals MAMD mode has multiple address channels and multiple
in AMBA AXI protocol [19]. If the counter reaches the state data channels, where even if one master occupies the bus,
that the slave is able to produce the output of the operation, another master is able to access a slave that is not under col-
the RVALID signal is asserted. The counter confirms the lision. However, it needs a large amount of resources and its
output data transfer by using the RREADY signal. If data are design gets readily complicated. Figure 4 and Figure 5 show
not generated in time and a read delay occurs, WREADY is the SAMD mode which combines the benefits of the SASD
deasserted to prevent new data from entering the slave. The and MAMD modes. In Figure 4, one address bus is shared by
read delay case and the write delay case are illustrated in all the masters while in Figure 5, each master has a separate
Figure 3, where the input data are assumed to be output in the data bus so that simultaneous data transfers are possible. For
next clock cycle. In the normal case when no delay occurs, the AXI protocol, one address is needed to send a burst and
the data come in through the write channel and the outcome hence the required bandwidth on the address channel is lower
of the operation goes out through the read channel. In the than that on the data channel. Thus the SAMD mode typically
write delay case in which an input delay occurs (by deasserted exhibits similar performances as the MAMD mode but in a
WVALID from the master), RVALID is deasserted after the particular case of one master occupying the address channel,
current output of the operation goes out (to prevent further another may not access the channel.

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FIGURE 3. Counter operations.

FIGURE 6. Data transfer associated with a processor core.

needs help from the DMA to transfer data. The DMA is

FIGURE 4. SAMD bus: address channel. unable to begin its activity of itself but entails control by
a processor. Thus in the beginning, the processor first con-
figures the DMA with the information needed to initially
setup the data transfer (DMA set in Figure 7). Subsequently,
DMA 0 which is in charge of the hardware accelerator input
begins its action while reading data from memory 0. After
some time passes by and the hardware accelerator begins
to output the result, DMA 1 reads out from the hardware
accelerator and writes in into memory 1. The data associated
with this are shown as the latter read (blue) and the latter
write (red) in Figure 7, where the two reads and the two
writes overlap with one another. By comparison with the
data transfer maneuvered by a processor, the number of data
movements is doubled (as shown in the lower part of Figure 7)
whereas the data transfer time is shorter owing to the higher
FIGURE 5. SAMD bus: data channels. efficiency with DMAs in general. However, the use of DMA
does not always guarantee a better performance because of
B. DATA TRANSFER MODELING IN BUS ARCHITECTURE the doubled number of reads and writes and the overhead of
Figure 6 shows the process in which a processor reads data the DMA set.
from memory, internally executes operations on them, and Two types of collisions, memory collision and SAMD
writes the outcome to another memory. Since the processor collision, will be addressed, which will incur delay. Figure 8
is able to read and write data of its own accord, it can directly shows the situation that multiple masters try to access mem-
access memory. The data transfer through the bus or on-chip ory through a bus with an arbiter. This leads to a collision
interconnect is seen in the lower part of Figure 6 where after at memory if only one physical port exists in memory. Only
some amount of time elapses with the read access, the write one master is allowed to access memory at a time owing
access is initiated, yielding an overlap between the read and to the collision and other masters than the master granted
the write. The data transfer by the processor is seemingly access will all suffer some delay. The bus arbiter grants
clearer and simpler than that by the hardware accelerator but access to a master according to the priority among the masters
more time will be consumed to transfer an item of data and and accordingly the read or write request is processed in
also the efficiency will be lower since one processor deals sequence. If the request underway is over, then the top priority
with all the operations internally. master is granted access after prioritizing the masters again.
Figure 7 shows the process in which a hardware accelerator Memory collisions may be subdivided into collisions by
is involved in the data transfer. The hardware accelerator two DMAs, by two processors, and by a DMA and a

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FIGURE 9. System configurations to identify memory collisions: no

collision (left) and collision (right).

FIGURE 10. DMA Transaction with no collision.

with two processors, and the case with one processor and
one DMA.
FIGURE 7. Data transfer associated with a hardware accelerator. Figure 10 shows the case with two DMAs and two
memories, which corresponds to the left half of Figure 9.
DMA 0 and DMA 1 read from memory 0 and memory 1
by delivering addresses A1 and D1, respectively. No col-
lision occurs since different memories are accessed and
addresses A1 and D1 are delivered without delay such that
memory 0 and memory 1, respectively, dispatch data burst
with length 4 without delay. Owing to the allowed multiple
outstanding transactions, DMAs send addresses B1 and E1
before their first data transfers are finished. However, each
memory receives its next address after its currently ongoing
data transfer is completed. Namely, addresses B1 and E1 are
not immediately input to memories. On the other hand, the
DMA data channel can transfer at almost every interval and
hence the delay in the address does not impact the actual data
transfer, incurring no data transfer delay in effect.
FIGURE 8. Memory collision: address channel. Figure 11 shows the case with two DMAs and one mem-
ory, corresponding to the right half of Figure 9, assuming
DMA 0 has a higher priority. DMA 0 and DMA 1 deliver
processor. Assume that the time consumed on the bus is read addresses A1 and D1 to memory 0. Since the MAMD
ignored and the MAMD mode is considered for the sake of bus is unable to deliver two addresses simultaneously mem-
examining only the memory collision situation. Also assume ory 0, address A1 of the higher priority DMA 0 is first
that the DMA uses bursts with burst length 4 and sup- delivered. Subsequently, DMA 0 tries to send address B1
ports multiple outstanding transactions (i.e., a new transfer while memory 0 dispatches data corresponding to address
request is allowed before the currently ongoing transfer is A1. The first address D1 of DMA 1 is delayed at memory
terminated) whereas memory does not support multiple out- 0 until the data transfer of DMA 0 corresponding to A1 is
standing transactions. The processor is assumed to support terminated, which is different from the situation illustrated in
neither burst transfers nor multiple outstanding transactions. Figure 10. After the data transfer of DMA 1 corresponding
Figure 9 shows two situations: two masters read from two to D1 starts, the opposite situation occurs: the second address
memories (left) and two masters read from one memory, B1 of DMA 0 is delayed at memory 0 until the data transfer of
leading to collision (right). The master can be a processor DMA 1 corresponding to D1 is finished. To sum up, memory
or a DMA and hence three cases are considered with the collisions alternately incur transfer delays on DMA 0 and
two masters in Figure 9: the case with two DMAs, the case DMA 1 caused by each other, thus entailing more time to

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FIGURE 11. DMA Transaction with memory collision. FIGURE 15. Processor core and DMA transactions in combination:
memory collision case.

A1 and B1, respectively, to memory 0. Owing to the collision

at memory, the MAMD bus arbiter plays a part. The higher
priority PS, PS 0, first delivers A1 and receives the corre-
sponding data. B1 of PS1 is delayed until the ongoing data
transfer of PS 0 corresponding to A1 is completed. However,
this delay suffered by the lower priority PS is different than
that associated with the DMA. The delay associated with
the processor is temporary, namely, the delay occurs only
FIGURE 12. Processor core transactions with no collision.
once in the beginning and does not cumulate with time.
Here assume that the two processors run at the same speed
and hence the read interval is the same. As a consequence,
memory collisions between processor and processor will not
be factored in during the performance estimation process
which will explained in Section IV.
Figure 14 and Figure 15 show the cases with one processor
and one DMA in combination, where no collision occurs
FIGURE 13. Processor core transactions with memory collision.
and memory collisions occur, respectively. In Figure 14, data
are read at the correct timing without any transfer delay,
assuming an ideal bus. In Figure 15, by contrast, a DMA
and a PS read from a memory simultaneously, leading to
memory collisions. More specifically, PS 0 and DMA 0 send
addresses A1 and B1 to memory 0, respectively. A collision
is detected in the bus arbiter. According to the assumed
priority, A1 of the higher priority PS 0 is first delivered to
memory 0, whereby B1 of DMA 0 is delayed until the read
of PS 0 corresponding to A1 is finished. In the middle of
FIGURE 14. Processor core and DMA transactions in combination: no the read of DMA 0 corresponding to B1, PS 0 requests a
collision case. new read corresponding to A2, which cannot be processed
in memory 0 and thus is delayed until the read of DMA
finish memory accesses when compared with no collision (in 0 is terminated. In this manner, delay is incurred alternately
Figure 10). henceforth. The delay inflicted on DMA 0 is caused by a
Figure 12 shows the case where two processors or PS data transfer of PS 0 inserted between two separate DMA
individually read from one of the two different memories, transfers which are based on bursts with the maximum burst
corresponding to the left half of Figure 9. In the absence of length of 256. Therefore, the inserted transfer delay of PS 0 is
both burst transfers and the multiple outstanding transactions, typically negligible, compared with the burst length. On the
each PS transfers only a single item of data corresponding other hand, the delay inflicted on PS 0 is as long as the burst
to an address and also the next address can be sent only length of DMA 0 and hence seems to be in sync with the
after the current data transfer is terminated. PS 0 and PS burst transfer. This data transfer behavior is also identified in
1 send addresses A1 and B1 to memory 0 and memory 1, the SAMD collision which will be depicted shortly. The delay
respectively, to execute two reads. No collision occurs since that is incurred in the SAMD mode also occurs when different
different memories are accessed, no delay is assumed to occur memories are accessed. Thus the delay inflicted on PS 0 will
on the bus, and memories dispatch data for A1 and B1 right be factored in when we deal with the SAMD collision shortly.
away. The AXI bus may be subdivided into the MAMD bus,
Figure 13 shows the case with two processors and one the SAMD bus, and the SASD bus. The SAMD bus oper-
memory, the collision case, corresponding to the right half ates while having no practically noticeable performance
of Figure 9. PS 0 and PS 1 simultaneously send addresses difference from the MAMD bus, except for the multiple

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FIGURE 16. SAMD collision between DMAs. FIGURE 18. SAMD collision between processor core and DMA.

dissimilar to the DMA that supports multiple outstanding

transactions, sequentially executes instructions to fulfill indi-
vidual reads and writes such that it does not occupy an address
channel for a long time. As a consequence, the SAMD colli-
sion does not show up except for the case when simultaneous
bus requests occur. Moreover, the collision occurs only once
in the beginning and hence impacts negligibly on the overall
execution time.
Figure 18 shows the situation when collisions occur
between DMA and processor during transactions through
the SAMD bus. The processor, PS 0, and DMA 0 request
FIGURE 17. SAMD collision between processor cores. addresses A1 and B1, respectively, to read data. PS 0 hav-
ing the higher priority first occupies the bus and transfers
its address to HW 0, followed by the address of DMA 0.
outstanding transaction situation. The SAMD collision may
DMA 0 sends C1 corresponding to the second burst before
occur between masters which operate in conjunction with one
the first burst is finished but C1 is not to be processed in
SAMD bus. It arises when the number of multiple outstand-
the slave and thus occupies the address channel of the bus.
ing transactions supported by the master is larger than that
After this, PS 0 tries to send the new address A2 to HW 0 but
supported by the slave. Assume that the DMA supports up
A2 has to wait since the shared address channel of the bus is
to 2 multiple outstanding transactions and its burst length is
already occupied. When the first DMA burst is finished and
64. Also assume that the processor supports neither multiple
thus HW 1 can afford to process new data, then HW 1 receives
outstanding transactions nor burst transfers. Slave is also
C1 that has occupied the address channel of the bus and
assumed to not support multiple outstanding transactions.
finally A2 of PS 0 pending goes up on the bus. As above, the
Figure 16 shows two DMAs access their individual slaves
DMA transfer typically does not suffer a delay whereas the
through the SAMD bus. Namely, DMA 0 and DMA 1 send
processor transfer is subject to the delay that is proportional
addresses A1 and D1 at once to hardware slaves HW 0 and
to the DMA burst length since the transfer of the processor
HW 1, respectively. Since only one address channel exists in
goes on in sync with the burst transfer of the DMA.
the bus, A1 of DMA 0 is first delivered to HW 0, according
to the priority. Before the current data transfer is completed,
the next address can be sent to the hardware since multiple IV. PERFORMANCE ESTIMATION METHODS
outstanding transactions are supported. DMA 0 and DMA Performance estimation methods in this work are explained in
1 send addresses B1 and E1, respectively, to the bus which terms of partitioning, scheduling, and memory merging on the
then tries to deliver the address that has arrived earlier of the transaction level. The modeling for performance estimation
two, B1, to HW 0. However, as HW 0 is under data transfer, is depicted in Subsection A and the process of performance
the request is not acceptable and hence B1 occupies the bus estimation is described in Subsections B and C.
till the transfer is over, by which E1 of DMA 1 is delayed.
Because the DMA transfer is in units of bursts, though the A. MODELING
address is delayed, the current data transfer is ongoing and First, some assumptions are made to model a digital sys-
the next data will not be delayed. In brief, the SAMD collision tem based on, say, a signal processing algorithm. A system
between DMAs is typically on a negligible level. is subdivided into individual operation units or functional
Figure 17 shows the situation when two processors access units which are executed in a block-interlacing manner [33],
their respective slaves via the SAMD bus. The processor, as illustrated in Figure 19. After the S1 operation is finished

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To employ the hardware accelerator, the DMA is typically

utilized to put data into the hardware whereas the DMA
setting prior to the data transfer is taken care of by the
processor. In this manner, the data computation and transfer
can be accelerated with a higher speed than in the case of
FIGURE 19. Block-interlacing.
the processor alone, apart from the overhead of DMA setting.
All the possibilities as regards partitioning are covered in this
work, namely, from all operations carried out by processors
to all operations conducted in hardware.
The order or sequence of operations impacts the execu-
tion time of the given system and therefore the optimization
FIGURE 20. Data transfer by the burst. process in view of the so-called scheduling is addressed in
this work. Each operation will necessitate its relevant data
and depending on whether the processor or the hardware is
employed for the operation, the execution time will vary.
Depending on the scheduling or the operation sequence,
memory collision or SAMD collision may occur owing to
FIGURE 21. Transaction-level model structure of the operation unit or interaction between different operations in the sequence.
functional unit. The optimal scheduling or operation sequence exhibiting the
shortest execution time is sought after in this work in view of
with data 1, its output data are delivered for the S2 operation collisions or conflicts between operations.
and at the same time new data 2 are fed for the S1 operation. Memory merging is considered in this work for optimiza-
In this manner, all the operations from S1 to S4 do their tion. Generally, each data item has its lifetime during which
works with their individual data at every moment. No data it should not be overwritten or altered in memory but be
dependency exists between operation units within a frame. retained. Accordingly, each data item needs its own memory
The data movement arising in each operation unit is region during its lifetime. On the other hand, to reduce the
expressed in units of bursts, as shown in Figure 20. The number of memory blocks being used, a memory region may
burst length in the processor is 1 and that in the DMA is be allocated to two different data items. In this case, if two
predetermined. The data to be transferred are matched to different operations read their data items located in the same
the burst length: if more data are to be transferred than the memory region, a collision occurs in this region, retarding the
burst length, appropriate number of bursts are created and execution and potentially affecting the system performance.
the remnant data shorter than the burst length is carried by If the effect on the execution time is negligible and the gain
an extra burst. In this way, the conventional data transfer of fewer memory blocks is large, memory merging may be
time by the cycle is represented by the burst in this work adopted to reduce system resources. Memory merging may
for performance estimation, whereby the overall simulation be considered partly or overall, depending on the predicted
time is reduced. The time required to send a single data beat performance.
is multiplied by the number of beats in a burst to obtain the Figure 21 shows the transaction-level model of the opera-
burst-unit data transfer time. tion unit considered in an algorithm. The basic unit of parti-
It is assumed that up to two processors are employed in our tioning is the operation unit or functional unit. The C struct,
systems during performance estimation but by necessity more step, is at the top level, where the information including data
than two processors can be employed. The two processors parameters, time parameters, and DMA parameters are set as
are allowed to execute their respective operations at the same user inputs. The struct, data, is to model the input data and the
time. Alternatively, one processor is allowed to perform an output data in each operation unit. At the bottom level, read
operation while the other is engaged in the DMA control for and write transactions, Rtransaction and Wtransaction, are
hardware utilization. used to model data transfers according to the processor and
System modeling is based on the elements that influence hardware characteristics. Besides, the DMA setting time and
the data transfer when hardware accelerators are included the DMA FIFO latency are modeled in case of the hardware
in the system. The memory collision when two bus masters use and the computation time is modeled as well. Each step,
access one memory and the SAMD collision when masters data, and transaction has its start time and length information,
access the shared address channel in the bus are taken into e.g., the number of beats.
account in the modeling. Furthermore, in the context of col-
lisions, the optimal combination of partitioning, scheduling, B. PERFORMANCE ESTIMATION ALGORITHM
and memory merging is sought for. The performance estimation process proposed in this work is
One thing to consider in an algorithm for system optimiza- shown in Algorithm 1. Initially, user inputs and the schedule
tion is whether each operation is executed by the processor are set up, followed by description of constraints of hard-
or by the hardware accelerator. This is called partitioning. ware accelerators and processors together with depiction of

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Algorithm 1 Performance Estimation

Input: NoPart, NoStep, NoSched, NoFunc and MemMerge
Output: T
1: for p = 1:NoPart do
2: for s = 1:NoSched do
3: for m = 1:MemMerge do
4: idealArch = heterogeneousSoC (p, s, m);
5: swConstArch = swCosntraints (idealArch);
6: hwConstArch = hwCosntraints (swConstArch);
7: busConstArch = busConstraints (hwConstArch);
8: T = performance(busConstArch);
9: end for
10: end for
11: end for

memory and bus conflicts or collisions. Algorithm 1 proposed lower the complexity of the heterogeneous SoC architecture
in this study can predict the performance of a heteroge- while performing memory merging to gain almost the same
neous SoC architecture. This algorithm considers hardware- performance improvement as having an on-chip memory for
software partitioning, memory merging, and scheduling in each function of the target application. We assume three situ-
each loop, to determine the optimal design combination ations in this loop: 1) If all functions share the same memory
when implementing a heterogeneous SoC using a hardware (m=0). 2) If all functions share two memories (m=1). 3) if
accelerator. all functions use different memories (m=2).
First, the partitioning loop determines that the primary When design options are determined by the index of the
thing to consider in an algorithm for system optimization three loops, an ideal heterogeneous SoC architecture (ide-
is whether each operation is executed by the processor or alArch) that does not reflect memory collisions and bus col-
by the hardware accelerator. Through this loop, it is pos- lisions is returned by a predefined function. The returned
sible to consider the cases where all functions of the tar- ideal heterogeneous SoC architecture (idealArch) is used as
get application to be implemented in a heterogeneous SoC an input to predefined functions (swConstraints) to reflect the
are mapped with the software domain, and the cases where constructs related to the software and hardware domains. This
all functions are mapped with the hardware domain. The function returns the architecture (swConstArch), wherein
total number of partitioning (NoPart) considered in the pro- time information (e.g., memory load/store time information)
posed estimation algorithm is determined by the power of 2 is updated to the processor core in a heterogeneous SoC archi-
(i.e., 2NoStep ). Next, each function (i.e., step) of the target tecture. The heterogeneous SoC architecture, which reflects
applications determines the scheduling in which each func- software domain time information, is used as an input for
tion mapped to the hardware domain or the software domain predefined functions to reflect constructions related to hard-
is executed. This loop considers the effects of memory and ware domains. This function returns the architecture (hwCon-
bus conflicts that occur when each function shares one mem- stArch), which updates information regarding the hardware
ory simultaneously. In addition, it can be considered that accelerator to be designed in the heterogeneous SoC archi-
the execution time of this loop differs depending on the tecture (e.g., burst length and computation time). Next, in the
domain in which each function is to be performed. The total heterogeneous SoC architecture (hwConstArch), which is an
number of scheduling, considered in the proposed estimation output from the hardware domain function (hwConstraints),
algorithm, is determined by a factorial (i.e., NoFunc!) of the the time information of memory collisions and bus collisions
number of functions. Finally, a memory merging step is per- is not reflected. Therefore, it uses the collision modeling
formed to predict the performance of the heterogeneous SoC function (busConstraints), written in Algorithm 2, to update
architectures according to the number of on-chip memories. the heterogeneous SoC architecture (busConstArch) latency
In general, on-chip memory collisions degrade the perfor- due to memory collision and bus collision. Finally, the perfor-
mance of accelerators implemented with heterogeneous SoC mance (T ) of the heterogeneous SoC architecture, reflecting
architectures. In other words, if the variables of different func- all the constraints, is returned by the predefined perf function.
tions do not use the same on-chip memory, the performance The performance estimation algorithm proposed simulates all
of the accelerator implemented with a heterogeneous SoC design points for a heterogeneous SoC architecture that can
architecture can be improved. However, using a large amount be obtained through each design option of hardware-software
of on-chip memory can increase the hardware complexity of partitioning, memory merging, and scheduling. Among the
the heterogeneous SoC architecture that needs to be imple- simulation results of all heterogeneous SoC architectures
mented. Therefore, in this loop, we merge on-chip memory to obtained through the combination of design options, the

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Algorithm 2 Bus Constraints

Input: hwConstArch
Output: busConstArch
1: for p = 1:NoStep-1 do
2: if hwConstArch.master[s] = DMA && hwConstArch.master[s+1] = DMA then
3: if hwConstArch.master[s].memory == hwConstArch.master[s+1].memory then
4: busConstArch = memoryConflicts (hwConstArch, s, s+1);
5: else
6: busConstArch = samdConflicts (hwConstArch, s, s+1);
7: end if
8: else
9: busConstArch = samdConflicts (hwConstArch, s, s+1);
10: end if
11: end for

optimum design point is determined to have the minimum are explored and generated beforehand and called afterward
execution time and minimum hardware complexity. The exe- to predict each performance. In case of a system with, for
cution time of many design points can be quickly estimated instance, three operations, six distinct sequences exist.
according to the combination of design options because the Subsequently, the constraint on hardware accelerators is
time information of each component of each heterogeneous set in Algorithm 1. The number of hardware accelerators is a
SoC is obtained through emulation in the target platform representative constraint. Among the operations constituting
(e.g., ZedBoard [12]). Based on this information, it is pos- the given system, any operation(s) may be chosen to be
sible to calculate the execution time of combinations for all executed by the hardware accelerator(s). In this phase, other
possible heterogeneous SoC architectures. conditions such as conflicts (or collisions) are not yet set.
In summary, the time information of each domain (hard- The number of processors needed to set DMAs for hard-
ware and software) is reflected in an ideal heterogeneous ware accelerators is assumed to be infinite and hence all the
SoC architecture, to which three design options are applied. operations are potentially allowed get started at once. Also,
Additionally, the latency due to bus and memory collisions no bus or memory conflict is assumed to exist. Based on these
is reflected in the heterogeneous SoC architecture. We mea- assumptions and the time information from the user inputs,
sured the performance of a heterogeneous SoC architecture the execution time of each operation is predicted, which is
that reflects all these factors. not accurate yet. As conditions on processors in conjunction
with bus and memory conflicts are taken into consideration,
C. CASE STUDY: ORTHOGONAL MATCHING the system performance will get more accurate.
PURSUIT (OMP) ALGORITHM In succession, the constraint on processors is set in
The design space is explored over all partitioning and Algorithm 1. The number of processors in the system is the
scheduling methods. A detailed explanation is given constraint. Processors are used for both the operations (com-
with an example application, orthogonal matching pur- putation) and the hardware accelerators (DMA setting). The
suit (OMP) [34], [35], as follows. Figure 22 shows user number of operations that can be started concurrently is
inputs (right) of the OMP algorithm (left) (based on least determined by the number of processors. On the basis of
squares to iteratively recover sparse data), which is the initial the sequence or order of operations, only after the cur-
phase to obtain the necessary data preceding the simulation rent operation by a processor is terminated, the next opera-
run. The OMP algorithm will be revisited in Section V. tion by the processor is allowed to get started. The limited
To implement a digital system architecture from an algorithm, number of processors renders the system simulator more
parameters are needed at the initial phase: To predict the practical.
overall execution time, basic information and the required Then, memory and bus conflicts (or collisions) are con-
time of each operation in the system should be fed as user sidered in Algorithm 1. In this phase, which operations are
inputs. Namely, the number of operations (the number of affected and how large the operations are affected by each
computations), the number of input and output data used in conflict can be predicted. Owing to the use of the SAMD bus,
each operation, the order of input and output data (in/out, a conflict on the address channel may occur between, e.g.,
timing), and information on times (time parameters) such as processor and DMA, yielding some data transfer delay in the
the operation time consumed inside the hardware accelerator, processor. This delay may cause another (equal-length) delay
the required time for the processor to transfer a data item, and of the following operation executed by the same processor.
the required time for the hardware to transfer a data item. As a result, the lastly ending operation in the system may
Next, schedule setting is conducted in Algorithm 1. Based change from one to another and the frame execution time in
on the number of operations, all the sequences of operations block interlacing may become longer.

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FIGURE 22. User inputs in an example algorithm.

FIGURE 23. Impact of the memory conflict.

FIGURE 24. Impact of the SAMD bus conflict.

Algorithm 2 shows the means to model the memory con-

flict (or collision) and the SAMD bus conflict and to pre- are assumed to conduct read operations simultaneously at
dict the performance. For every distinct two-step pair, where the same memory, memory A, as shown in time point 1
the step corresponds to an operation unit, memory and bus of Figure 23. As a result, a memory conflict occurs by
conflicts are examined in the pseudo-code of Algorithm 2. which DMA1 read is delayed since DMA0 is assumed to
If the two masters are different, only the SAMD bus conflict have a higher priority. This is shown in time point 2 of
is considered (samdConflicts) (Line 9). As was elaborated on Figure 23. DMA0 and DMA1 access memory A three times
in Section III.B, for the memory conflict, the conflict between in total and at time point 2, no overlap occurs between
DMA and DMA is significant whereas for the SAMD bus these three accesses to memory A. However, the delay in
conflict, the conflict between DMA and processor is signif- DMA0 and DMA1 regarding memory A affects the following
icant (Line 2). Each master is identified and the conflict is read operations and now a conflict is newly encountered in
examined according to the combination or pair of masters. memory C, leading to the final situation shown in time point 3
The smallest unit of data transfer is denoted as hwCon- of Figure 23.
straint.master in Algorithm 2. In the inner-most loop, hwCon-
straint.master[i] and hwConstraint.master[i+1] are checked
to see whether they are associated with the same memory Algorithm 3 Orthogonal Matching Pursuit (OMP)
access (memoryConflicts) (Line 3). If so, the access timing Input: y, r, A
is identified to see whether they overlap with each other. If so Output: x [i]
as well, their access types (read or write) are identified. In the 1: for i = 1; i = i + 1 till ||r [i] || = 0 do
AXI protocol, the read channel and the write channel act 2: g[i] = AT r [i−1] ;
separately and hence a conflict may not occur if both a read j[i] = argmax |g[i]
3: j |/||Aj ||;
and a write occur simultaneously at the same memory. Lastly, j
if two transactions do not access the same memory at the same 4: T [i] = T [i−1] ∪ j[i] ;
time, only SAMD conflicts are considered (samdConflicts) 5: x [i] = argmax ||y − AT[i] x||;
(Line 6). x
Figure 23 shows the effect of the memory conflict between 6: r [i] = y − Ax [i] ;
two DMAs on transactions. In the beginning, two DMAs 7: end for

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Figure 24 shows how the transactions are affected by the TABLE 1. Simulation conditions.
SAMD bus conflict between DMA and processor. Assume
that the masters individually access separate slaves during
their reads. The first read of the DMA and the first read of
the processor get started almost at the same time, as shown in
time point 1 of Figure 24, and subsequently the SAMD bus
receives the data for the DMA and the data for the processor
on its two distinct data channels. At this time, the DMA which
allows multiple outstanding transactions sends the address of
the second read but since the corresponding slave cannot pro-
cess this read address, the address is held on the bus. Owing TABLE 2. Block interlacing applied to the OMP algorithm.

to this address held on the bus, the address of the second read
sent by the processor is not delivered immediately to the bus
but delayed until the first read burst of the DMA is finished,
as shown in time point 2 of Figure 24. In this manner, the
read operation of the processor appears to be in sync with
the data transfer of the DMA. This condition will last up to the
penultimate DMA read burst and subsequently at the instant unit steps accompany the initialization phase: computing the
of the last DMA read burst, the DMA no longer has an address correlation (S1), finding the location with the maximum cor-
to send and hence the address channel of the SAMD bus is relation and adding that location to the set with locations
empty and the read operations of the processor are carried on found up to now (S2), estimating the x value by using the
without delay, as shown in time point 3 of Figure 24. least mean squares method (S3), calculating the new r value
by using the estimated x value (S4), and judging whether to
V. SIMULATION proceed or not by using the calculated r value (S5). These
To validate the proposed performance estimation meth- steps are iterated, where if the r value in S5 is small enough
ods, an example algorithm, OMP [34], [35], is taken and to meet the performance required by the system, the x value
modeled. The OMP algorithm is utilized in compressive estimated so far is printed and the algorithm is terminated.
sensing and long-term evolution (LTE) to estimate the wire- If the r value is not sufficiently small, the steps are iterated
less channel. In order to prove that the proposed perfor- unceasingly and hence the maximum number of iterations is
mance estimation algorithm is generally applicable to any typically specified, which is set to 10 in this work.
other application, we have included additional experimen- The simulation conditions are listed in Table 1, where
tal results on CNNs (AlexNet [36]) and wireless commu- 4 conditions, case 1–case 4, are shown. Case 1 is the optimal
nications (LDPC-coded MIMO-OFDM [37], [38]). In the case in case that 3 hardware (HW) accelerators are used.
case of CNNs, the third layer for AlexNet is assumed as Case 2–case 4 are the cases which deviate from the optimal
the example applications. Moreover, in the case of wire- by altering some condition(s). Case 2 uses a shared memory
less communications, the LDPC-coded MIMO-OFDM con- while case 1 uses separate memories for data items and hence
sists of five functions, including initial synchronization, fast memory conflicts become more frequent in case 2. Case 3 has
Fourier transform (FFT), channel estimation, multiple-input a scheduling different from case 1. Namely, the order and
and multiple-output (MIMO) and low-density parity-check the number of operations executed by processors P1 and P2
code (LDPC). The system architecture for the OMP, CNN are changed, leading to changes in the conflict order and
and LDPC-coded MIMO-OFDM is implemented in the full- locations. Case 4 has a different partitioning. Namely, S4
system simulator [7] and Xilinx Zynq 7020 SoC chip on executed by hardware is executed by software (SW), leading
ZedBoard [12] for comparison and verification. to the change in conflict in S4 from memory conflict to
SAMD bus conflict and hence the potential increase in the
A. SIMULATION METHODS execution time.
The OMP algorithm can estimate the LTE channel with a The proposed performance estimation methods are applied
5MHz bandwidth and is converted to a system architecture as follows. Block interlacing is assumed and different
implemented on dual-core Zynq 7020 [12]. The algorithm is data items are processed in different steps in parallel.
subdivided into 5 steps, S1-S5, corresponding to 5 operation Table 2 shows the block interlacing applied to OMP. Each
units. Block interlacing is utilized to enable all the steps to step operates on one of the data items 1-5 at every instant.
concurrently run without data dependency. Hardware acceler- By using the proposed methods, the performance of the last
ators, DMAs, processors, and memories are connected to one phase (or stage) of the fifth iteration (of the 10 iterations in
another through an SAMD bus. Each data item is assumed to total), which is the shaded area in Table 2, is predicted. Thus
have its respective memory unless otherwise stated. the first data item (the data entry numbered 1 in Table 2)
The OMP algorithm is revisited in Algorithm 3, which for the fifth iteration is the target. Partitioning between pro-
is equivalent to the left half of Figure 22. Five operation cessors and hardware accelerators to execute the operations

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FIGURE 25. Memory conflict: Case 1. FIGURE 27. Scheduling: Case 3.

FIGURE 26. Memory conflict: Case 2. FIGURE 28. Partitioning: Case 4.

from S1 to S5 is determined and scheduling (or the operation fetched by the operation and the lower half expresses the
order) is also determined to predict the overall execution time. outcome of the operation. The computation time is typically
The performance is predicted in view of the effect of memory much smaller than the data transfer time and not visible
merging (or the number of memories) as well. from the outside but in case of S3, the computation time is
relatively long and explicitly denoted as comp in Figure 25.
B. SIMULATION RESULTS AND ANALYSIS In the first place, data r and then A are read by S1. As data A
According to the simulation conditions mentioned above, are read, outputs g is produced. In S2, all of data g are read
simulation results from the system simulator are provided and the outcome T is produced. In case of S1, data A and g can
in this subsection. The performance of each of the modeled be processed concurrently since S1 is assumed to be handled
system architectures mapped from the example algorithm, by a hardware accelerator and hence two distinct DMAs take
OMP, is predicted and estimated and also compared with charge of the input and the output of the operation. Whereas
the result from the Zynq-on-ZedBoard implementation. First, both a read and a write are conducted concurrently in S1,
simulation results and analysis of case 1 to case 4 in terms either a read or a write is conducted at a time in S2 since S2 is
of memory merging, scheduling, and partitioning will be assumed to be handled by a processor. Therefore, in case of
provided. Then, implementation through optimization will be S2, the output of the operation is produced after all the inputs
explained. Lastly, simulation results will be briefly compared are fetched. Figure 25 shows the case when each data item
with those of an existing work. is allotted a separate memory. The memory conflict between
Errors between the performance of the system simulator two distinct hardware accelerators is only modeled and its
for the algorithm and the performance of the implementation effect is predicted in this work. Operation units or steps S1,
in Zynq 7020 on ZedBoard are under 5% for all the simula- S3, and S4 which are implemented in hardware accelerators
tion conditions, case 1–case 4. These errors come from the are subject to memory conflict if the identical data item is read
modeling based on the data transfer unit (by the burst) which (or written) at the same time. Accordingly, memory conflict
exhibits lower accuracy than the cycle-accurate modeling occurs where S1 and S3 read data A at once, which is the
(by the clock cycle). However, the details that impact the shaded area in Figure 25.
performance marginally are simplified in our modeling and Figure 26 shows the memory conflict for case 2 which is
instead the speed is enhanced by a factor of 10 to 100 in defined in Table 1. The simulation with case 2 is to identify
the proposed system simulator for expeditious performance the effect of memory merging by using an integrated or shared
prediction and large design space exploration. memory instead of separate memories in case 1. In case 2, all
Figure 25 shows the timing diagram of input and output the data are assigned one memory. All the other simulation
data of each operation (e.g., S1) for case 1. In other words, conditions of case 2 are identical to those of case 1. The
for each operation or step, the upper half expresses the data execution time will grow in case 2 because only one master

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 J. Wang et al.: Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

FIGURE 29. Execution time according to the number of hardware

accelerators.

can access memory during a read or a write. The shaded

areas where memory conflicts occur are shown in Figure 26.
Memory conflicts occur between the read (or write) data
transfer intervals of S1 and S3 regardless of what the data
item is. The extent of memory conflict is affected by the
amount of data read by S3, which is predicted to be 730 cycles
from the system simulator and 620 cycles from the board
implementation.
The effect of scheduling is illustrated in case 3 in compar-
ison with case 1. As was shown in Figure 25 for case 1, S1
to S3 can operate concurrently, followed by S4 and S5. The
maximum number of concurrent operations is 3. Figure 27
shows the scheduling of case 3 which was defined in Table 1.
By means of the different scheduling in case 3 than in case 1,
the maximum number of concurrent operations is 2 for case 3.
For S2, more memory conflicts occur in case 1, leading
to the execution time of 3000 cycles whereas less conflicts
occur in case 3, exhibiting the execution time of 2900 cycles.
However, the overall execution time is 1000 cycles longer for
case 3 owing to the smaller number of concurrent operations.
Lastly, the effect of partitioning is illustrated in case 4 in
comparison to case 1. Figure 28 shows the partitioning of
case 4 which was defined in Table 1. The operation or step
S4 in case 4 is implemented in software by processor P1
instead of hardware in case 1. This change in partitioning
significantly increased the execution time of S4, yielding an FIGURE 30. Illustration of the optimum design parameter combinations
for (a) two processor cores, (b) two processor cores and one hardware
increase in the overall execution time as well, which stems accelerator, (c) two processor cores and two hardware accelerators,
from the fact that the processor is slower in processing oper- (d) two processor cores and three hardware accelerators, (e) one
processor core and four hardware accelerators, (f) five hardware
ations than the hardware accelerator. accelerators, and (g) comparison of memory area between separated
Figure 29 shows the overall execution time as a function of memories and merged memory.
the number of hardware accelerators according to the hard-
ware and software partitioning. The optimum bar (minimum
time) is obtained by choosing the minimum execution time memory merging for each number of hardware accelerators.
across all combinations of scheduling and memory merging The mean bar is obtained by calculating the average execution
for each number of hardware accelerators. The least opti- time for all combinations of scheduling and memory merging
mum bar (maximum time) is obtained by choosing the maxi- for each number of hardware accelerators. Generally, as more
mum execution time over all combinations of scheduling and hardware accelerators are used, the execution time tends to

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J. Wang et al.: Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

drop since more operations can be carried on concurrently. TABLE 3. Optimized design option.
The optimum execution time is improved maximally, rela-
tive to the mean execution time, when only one hardware
accelerator is used. This means a specific operation will
occupy a large percentage of the overall execution time when
processors deal with operations and also the gain will be
large if the operation is managed by the hardware accelerator.
In the architecture optimization process below, two hard-
ware accelerators are assumed to be used. Figure 30 shows
the heterogeneous SoC architecture of each optimum bar in
Figure 29, their timing diagram and memory complexity.
As mentioned earlier, the execution time tends to decrease
when more hardware accelerators and memories are used
in the heterogeneous SoC architecture, because more tasks
can be performed simultaneously without memory collision.
Additionally, since it is more efficient for the hardware accel-
erator to access the memory in burst units than for CPUs to
read and write to the memory, the performance of the hetero-
geneous SoC architecture improves as the number of hard-
ware accelerators increases. For example, in Figure 30 (a), FIGURE 31. Comparison of computational complexity between the
CAG-based optimization and the proposed optimization: (a) throughput
since the steps assigned to each CPU are executed sequen- optimization and (b) memory area optimization.
tially, scheduling cannot be freely performed through block-
interlacing manner [33]. However, as Figure 30 (f) assumes
that all steps are implemented with a hardware accelerator, hardware accelerators are employed and to run S2, S4, and
block interlacing can be applied to execute all steps simul- S5, processors are used. According to the chosen schedul-
taneously and without dependency. Figure 30 shows that ing, processor P1 runs one hardware accelerator for S1 and
allocating memory for each variable further improves perfor- then runs the S5 operation, followed by the S4 operation.
mance. Furthermore, as shown in Figure 30 (c), if bus masters Processor P2 first runs the other hardware accelerator for S3
do not access memory simultaneously by hardware-software and runs the S2 operation. The simulated execution time of
partitioning and scheduling, hardware complexity can be the optimized architecture is 10295 cycles, obtained from
reduced, and high-performance gain can be obtained through the system simulator, and the actual execution time of the
merged memory. This shows that using separate memory for optimized architecture is 10788 cycles, obtained from the
a heterogeneous SoC architecture is not always optimal for board implementation, resulting in a 4.8% error.
execution time. Figure 30 (g) illustrates the hardware area Some comparison is made with an existing work [14]
measured by the memory model based on the commercial where the performance difference according to scheduling
SRAM memory compiler provided with the TSMC 28-nm is not considered but a predetermined scheduling is fixed
standard cell library. The simulation result indicates that the during the simulation. However, if the timing of an operation
hardware area of the merged memory manner (Figure 30 (c)) to access data coincides with the timing of another operation
is approximately 67.6% smaller than that of the separated to access the same data, a conflict occurs and the performance
memory manner (Figure 30 (a), (b), (d), (e), and (f)). The is impacted accordingly. Thus the effect of scheduling for
separate memory manner allocates additional input/output the OMP algorithm is considered for comparison with the
(I/O) ports than the merged memory manner, which is the method in [14]. Assuming two hardware accelerators are
primary reason the memory area is different between the used, the optimum architecture for the algorithm is shown in
two methods using the same capacity of memory. In addi- Table 3, which has an execution time of 10295 cycles from
tion, multiple separated memories make the AXI interconnect simulation. If the optimum scheduling is not explored but the
more complex. It leads to making the overall heterogeneous operations are executed from S1 to S5 in order, then the exe-
SoC architecture more complex. As a result, the proposed cution time is 11604 cycles, even if partitioning and memory
simulator can achieve a heterogeneous SoC architecture merging are the same for the two architectures. Scheduling
that can achieve high-performance gains with low memory is not considered in [14] while the optimum execution order
complexity. can be explored in this work which models the data transfers
For the OMP algorithm, various system architecture can- with both the processor and the DMA. The execution time
didates are searched for in terms of partitioning, schedul- difference between the architecture with optimum scheduling
ing, and memory merging, where two hardware accelerators and the architecture without scheduling is about 1309 cycles,
are assumed to be used. The optimum architecture has the leading to a 12.7% discrepancy if conflicts are not taken into
parameters listed in Table 3. To execute S1 and S3, two account.

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 J. Wang et al.: Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

FIGURE 33. Comparison of simulation time between the proposed

performance estimation (this work) and conventional simulation-based
approach [7].

throughput optimization. The reason is that the proposed

optimization helps determine the scheduling that minimizes
the collision-induced latency in the heterogeneous SoC
architecture. Therefore, it can be concluded that the pro-
posed optimization outperforms the CAG-based optimiza-
tion, regardless of the optimization goal.
Figure 32 shows that the proposed performance estimation
algorithm can predict the communication performance of het-
erogeneous SoC architectures for the OMP algorithm more
FIGURE 32. Performance estimation results of heterogeneous SoC
architecture based on static analysis-based [28], statistics-based [29] and accurately compared with the static analysis-based estima-
this work (proposed). tion [28] and statistics-based estimation [29]. The proposed
estimation algorithm considers both the bus protocol over-
C. COMPARISON OF THE OPTIMIZATION head (bus conflict) and memory latency (memory collision)
Figure 31 (a) compares the computational complexity when using the evaluation board (e.g., ZedBoard [12]) for eval-
the optimization goal is to maximize the throughput, or, uating the time information of the hardware and software.
equivalently, to minimize the execution time. The simulation The experimental results show that the proposed algorithm
results show that the design options optimized by the pro- approaches the full-system simulator [7] more closely than
posed simulator can improve the throughput performance by the conventional algorithms. For example, the proposed algo-
up to 32%, compared to that of the CAG-based optimization. rithm reduces the estimation error to 6%, whereas the conven-
This can be explained by the fact that the proposed opti- tional algorithms in [28] and [29] experience the estimation
mization can minimize the memory collision by optimizing errors of 18% and 16%, respectively.
both the hardware-software partitioning and the scheduling,
as opposed to the CAG-based optimization. In addition, the D. COMPARISON OF SIMULATION TIME
proposed optimization can also reduces the latency induced Figure 33 compares the proposed performance estimation
by bus conflicts by optimizing the scheduling. However, it is and the conventional simulation-based approach in terms
shown in the figure that the throughput improvement comes of simulation time. As shown in figure, compared with the
at the expense of memory area, more specifically, by 61%, conventional simulation-based [7] approach, the proposed
compared to the CAG-based optimization. However, this does performance-estimation algorithm provides a speedup of two
not imply that the proposed optimization always results in orders of magnitude. The simulation-based approach is accu-
more memory area. rate enough to capture the dynamic nature of the commu-
Figure 31 (b) shows the computational complexity when nication bandwidth, but it often takes a prohibitively long
the optimization goal is to minimize the memory area. For time to simulate. According to our experiments, the conven-
fair comparison, the maximum memory size has been set tional simulation-based approach takes a few hours to eval-
to 24.4 Kbytes. The simulation results show that, com- uate a single heterogeneous SoC architecture with hundreds
pared with the previous throughput optimization, the through- of different combinations of hardware-software partitioning,
put improvement of the proposed optimization has been memory merging, and scheduling. Using the conventional
reduced to 19%. Instead, the proposed optimization can pro- simulation-based approach, we run the full-system simulator
vide the average memory area saving of 20%, as shown proposed in [7], once for each design point, taking approxi-
in Figure 31 (b). In other words, the proposed optimization mately 12.5 seconds per design point. In contrast, to minimize
outperforms the CAG-based optimization in terms of both the simulation time and maintain estimation accuracy, the
throughput and memory area, as opposed to the previous proposed performance estimation algorithm constrains the

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J. Wang et al.: Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

Algorithm 4 The Third Convolutional Layer of AlexNet

Input: NoBatch, IAs, Wts and OAs
Output: poolout
1: for b=1:NoBatch do
2: convout = convlayer (IAs, Wts, OAs);
3: biasout = bias (convout);
4: reluout = relu (biasout);
5: lrnout = LocalRespNorm(reluout);
6: poolout = pool(lrnout);
7: end for

Algorithm 5 LDPC-Coded MIMO-OFDM

FIGURE 34. Execution time according to the number of hardware
Input: Symbols and NoSymbols accelerators: (a) third convolutional layer of AlexNet [36] and
Output: ldpcout (b) LDPC-coded MIMO-OFDM [37], [38].
1: for s=1:NoSymbols do
2: syncout = synchronization (Symbols); performance gain i.e., 48% for the third convolutional layer
3: fftout = fft (syncout, Symbols); of AlexNet. This is also the case when the proposed per-
4: chest = channelestimation (fftout); formance estimation algorithm is applied to a LDPC-coded
5: mimoout = mimo (chest, fftout); MIMO-OFDM. Figure 34 (b) shows that the estimation
6: ldpcout = ldpc (mimoout); error for a LDPC-coded MIMO-OFDM is smaller than 5.6%
7: end for compared to the performance estimation result of AccTLM-
Sim [7], and the performance gain is 56%. The experimental
results show that although the optimum hardware-software
partitioning, scheduling, and memory merging tend to vary
use of an evaluation board [12] to evaluate the time infor-
with the application, the proposed performance estimation
mation of the heterogeneous SoC architecture. Since a few
algorithm is generally applicable to any heterogeneous SoC
tens of time information is sufficient to express most of the
with a reasonably small estimation error and a noticeable
heterogeneous SoC architectures of interest, the extra simu-
performance gain.
lation time required to obtain the time information of each
hardware component becomes negligible, particularly in the VI. CONCLUSION
case of broad design space (i.e., a space of hundreds of design The system speed can be improved by using hardware accel-
points). In the case of thousands of design points, the per- erators. However, if the data transfer pattern is not optimized,
formance estimation algorithm accelerates the conventional the heterogeneous SoC may give rise to increased conflicts
simulation-based approach by two orders of magnitude. or collisions, delaying the data transfer in the bus and mem-
Figure 33 shows that the extra time required for prior simula- ory and degrading the system performance more than the
tions becomes negligible as the design space increases. Thus, ideally predicted one. In this work, conflicts or collisions
it can be concluded that the proposed performance-estimation are modeled to predict the performance and also a system
algorithm can estimate orders of magnitude faster than the simulator is developed to cover a large design space in terms
conventional time-consuming simulation-based approach. of partitioning, scheduling, and memory merging, by which
the optimum architecture to minimize the execution time can
E. EXTENSION TO OTHER APPLICATIONS be found. In a setting where multiple masters and slaves are
In this subsection, the proposed performance estimation algo- connected to a bus, the SAMD bus conflict and the memory
rithm is extended to CNNs (the third convolutional layer conflict are modeled in consideration of multiple outstanding
of AlexNet [36]) wireless communications (LDPC-coded transactions and operation units.
MIMO-OFDM [37], [38]) applications. As shown in By using the proposed performance estimation methods,
Algorithm 4, the third convolutional layer consists of five an example algorithm, OMP, for LTE 5MHz channel esti-
functions, including convolutional accelerator, bias, ReLU, mation is implemented for four cases. The performance
LRN and Pooling. As shown in Algorithm 5, the LDPC-coded from simulation and the performance from actual implemen-
MIMO-OFDM consists of five functions, including initial tation are compared to validate the reliability of the sys-
synchronization, fast Fourier transform (FFT), channel esti- tem simulator. For all the simulation conditions, the error
mation, multiple-input and multiple-output (MIMO) and low- between the predicted execution time and the actual exe-
density parity-check code (LDPC). cution time is under 5%. Assuming the number of hard-
Figure 34 (a) shows that the performance estimation error ware accelerators is 2, the optimum architecture for the
of the third convolutional layer of AlexNet [36] is less OMP algorithm is extracted. In addition, compared with
than 5.9% compared to the performance estimation result the conventional simulation-based approaches, the proposed
of AccTLMSim [7]. Moreover, it achieves a significant estimation algorithm provides a speedup of one to two orders

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Sep. 2020. in 2002. From 2002 to 2004, he was with Sam-
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a Professor. His research interests include design and modeling of SoC,
pp. 1245–1248.
hardware accelerators, and virtual platforms for neural networks and 5G.
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ing high bandwidth memory on FPGAS,’’ in Proc. IEEE 28th Annu.
Int. Symp. Field-Program. Custom Comput. Mach. (FCCM), May 2020, CHESTER SUNGCHUNG PARK (Senior Mem-
pp. 111–119. ber, IEEE) received the Ph.D. degree in electrical
[44] G. Singh, D. Diamantopoulos, C. Hagleitner, J. Gomez-Luna, S. Stuijk, engineering from the Korea Advanced Insti-
O. Mutlu, and H. Corporaal, ‘‘NERO: A near high-bandwidth memory tute of Science and Technology (KAIST), Dae-
stencil accelerator for weather prediction modeling,’’ in Proc. Field-
jeon, in 2006. From 2006 to 2007, he was
Program. Log. Appl. (FPL), Sep. 2020, pp. 9–17.
with Samsung Electronics, Giheung, South Korea.
[45] A. Kurth, W. Rönninger, T. Benz, M. Cavalcante, F. Schuiki, F. Zaruba, and
L. Benini, ‘‘An open-source platform for high-performance non-coherent
From 2007 to 2013, he was with Ericsson
on-chip communication,’’ 2020, arXiv:2009.05334. Research, Plano, TX, USA, as a Senior Engineer.
[46] P. Gu, X. Xie, S. Li, D. Niu, H. Zheng, K. T. Malladi, and Y. Xie, ‘‘DLUX: Since 2013, he has been with the Department
A LUT-based near-bank accelerator for data center deep learning training of Electronics Engineering, Konkuk University,
workloads,’’ IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., South Korea, as an Associate Professor, where he is working on the design
vol. 40, no. 8, pp. 1586–1599, Aug. 2021. and modeling of SoC, hardware accelerators, and virtual platforms for neural
[47] E. Azarkhish, D. Rossi, I. Loi, and L. Benini, ‘‘Neurostream: Scalable and networks and 5G. His research interests include SoC architecture design for
energy efficient deep learning with smart memory cubes,’’ IEEE Trans. artificial intelligence, processing in memory, and wireless communication.
Parallel Distrib. Syst., vol. 29, no. 2, pp. 420–434, Feb. 2018.

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