Unit -2 notes

INSTRUCTION SET ARCHITECTURE: Instruction codes, instruction set formats(fixed, variable, hybrid),
types of instructions, memory reference

Typ Types of Instructions in Computer

es of Instructions in Computer
Architecture
A computer instruction refers to a binary code that controls how a computer performs micro-
operations in a series. They, together with the information, are saved in the memory. Every
computer has its own set of instructions. Operation codes or Opcodes and Addresses are the
two elements that they are divided into.

In this article, we will dive deeper into the types of instructions in Computer Architecture
according to the GATE Syllabus for (Computer Science Engineering) CSE. Keep reading
ahead to learn more.

Table of Contents

 What are the Types of Instructions in Computer Architecture?

 Three Address Instructions
 Two Address Instructions
 One Address Instruction
 Zero Address Instructions
 Video on Computer Architecture

What are the Types of Instructions in

Computer Architecture?
A computer’s instructions can be any length and have any number of addresses. The
arrangement of a computer’s registers determines the different address fields in the
instruction format. The instruction can be classified as three, two, and one address instruction
or zero address instruction, depending on the number of address fields.

Three Address Instructions

A three-address instruction has the following general format:
source 1 operation, source 2 operation, source 3 operation, destination

ADD X, Y, Z

Here, X, Y, and Z seem to be the three variables that are each assigned to a distinct memory
location. The operation implemented on operands is ‘ADD.’ The source operands are ‘X’ and
‘Y,’ while the destination operand is ‘Z.’

In order to determine the three operands, bits are required. To determine one operand, n bits
are required (one memory address). In the same way, 3n bits are required to define three
operands (or three memory addresses). To identify the ADD operation, bits are also required.

Two Address Instructions

A two-address instruction has the following general format:

source and destination of the operation

ADD X, Y

Here X and Y are the two variables that have been assigned to a specific memory address.
The operation performed on the operands is ‘ADD.’ This command combines the contents of
variables X and Y and stores the result in variable Y. The source operand is ‘A,’ while ‘B’ is
used as both a source and a destination operand.

The two operands must be determined using bits. To define one operand, n bits are required
(one memory address). To determine two operands, 2n bits are required (two memory
addresses). The ADD operation also necessitates the use of bits.

One Address Instructions

One address instruction has the following general format:

operation source

INCLUDE X

Here X refers to the variable that has access to a specific memory region. The operation
performed on operand A is ‘ADD.’ This instruction adds the value of variable A to the
accumulator and then saves the result inside the accumulator by restoring the accumulator’s
contents.

Zero Address Instructions

In zero address instructions, the positions of the operands are implicitly represented. These
instructions use a structure called a pushdown stack to hold operands.

memory reference
Control instructions are used to control the flow of instructions within the
computer system. These instructions include branch instructions, which
transfer control to different parts of the program based on specified
conditions, and jump instructions, which transfer control to a specified
memory location.
The basic computer has 16-bit instruction register (IR) which can denote
either memory reference or register reference or input-output instruction.
1. Memory Reference – These instructions refer to memory address as
an operand. The other operand is always accumulator. Specifies 12-bit
address, 3-bit opcode (other than 111) and 1-bit addressing mode for
direct and indirect addressing.

Example – IR
register contains = 0001XXXXXXXXXXXX, i.e. ADD after fetching and
decoding of instruction we find out that it is a memory reference
instruction for ADD operation.
Hence, DR ← M[AR]
AC ← AC + DR, SC ← 0
1. Register Reference – These instructions perform operations on
registers rather than memory addresses. The IR(14 – 12) is 111
(differentiates it from memory reference) and IR(15) is 0 (differentiates
it from input/output instructions). The rest 12 bits specify register

operation. Exa
mple – IR register contains = 0111001000000000, i.e. CMA after fetch
and decode cycle we find out that it is a register reference instruction
for complement accumulator.
Hence, AC ← ~AC
1. Input/Output – These instructions are for communication between
computer and outside environment. The IR(14 – 12) is 111
(differentiates it from memory reference) and IR(15) is 1 (differentiates
it from register reference instructions). The rest 12 bits specify I/O
 operation. Exa
mple – IR register contains = 1111100000000000, i.e. INP after fetch
and decode cycle we find out that it is an input/output instruction for
inputing character. Hence, INPUT character from peripheral device.
Essential PC directions are the principal tasks that a PC can perform.
These directions are executed by the focal handling unit (central
processor) of a PC, and they structure the reason for additional perplexing
tasks. A few instances of essential PC directions include:
1.Load: This guidance moves information from the memory to a computer
processor register.
2.Store: This guidance moves information from a computer chip register
to the memory.
3.Add: This guidance adds two qualities and stores the outcome in a
register.
4.Subtract: This guidance deducts two qualities and stores the outcome
in a register.
5.Multiply: This guidance duplicates two qualities and stores the outcome
in a register.
6.Divide: This guidance isolates two qualities and stores the outcome in a
register.
7.Branch: This guidance changes the program counter to a predefined
address, which is utilized to execute restrictive and genuine leaps.
8.Jump: This guidance changes the program counter to a predefined
address.
9.Compare: This guidance looks at two qualities and sets a banner
demonstrating the consequence of the examination.
10.Increment: This guidance adds 1 to a worth in a register or memory
area.
The set of instructions incorporated in16 bit IR register are:
1. Arithmetic, logical and shift instructions (and, add, complement,
circulate left, right, etc)
2. To move information to and from memory (store the accumulator, load
the accumulator)
3. Program control instructions with status conditions (branch, skip)
4. Input output instructions (input character, output character)

Addressing Modes
Addressing Modes– The term addressing modes refers to the way in
which the operand of an instruction is specified. The addressing mode
specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually executed.
Addressing modes for 8086 instructions are divided into two
categories:
1) Addressing modes for data
2) Addressing modes for branch
The 8086 memory addressing modes provide flexible access to memory,
allowing you to easily access variables, arrays, records, pointers, and
other complex data types. The key to good assembly language
programming is the proper use of memory addressing modes.
An assembly language program instruction consists of two parts

The memory address of an operand consists of two components:

IMPORTANT TERMS
 Starting address of memory segment.
 Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and
index.
o Displacement: It is an 8 bit or 16 bit immediate value given in
the instruction.
o Base: Contents of base register, BX or BP.
o Index: Content of index register SI or DI.
According to different ways of specifying an operand by 8086
microprocessor, different addressing modes are used by 8086.
Addressing modes used by 8086 microprocessor are discussed below:
 Implied mode:: In implied addressing the operand is specified in the
instruction itself. In this mode the data is 8 bits or 16 bits long and data
is the part of instruction.Zero address instruction are designed with
implied addressing mode.

 Immediate addressing mode (symbol #):In this mode data is present

in address field of instruction .Designed like one address instruction
format.
Note:Limitation in the immediate mode is that the range of constants
 are restricted by size of address field.

Example: MOV AL, 35H (move the data 35H into AL register)
 Register mode: In register addressing the operand is placed in one of
8 bit or 16 bit general purpose registers. The data is in the register that
is specified by the instruction.
Here one register reference is required to access the data.

Example: MOV AX,CX (move the contents of CX register to AX

register)
 Register Indirect mode: In this addressing the operand’s offset is
placed in any one of the registers BX,BP,SI,DI as specified in the
instruction. The effective address of the data is in the base register or
an index register that is specified by the instruction.
Here two register reference is required to access the data.

The 8086 CPUs let you access memory indirectly through a register
using the register indirect addressing modes.
 MOV AX, [BX](move the contents of memory location s
addressed by the register BX to the register AX)
 Auto Indexed (increment mode): Effective address of the operand is
the contents of a register specified in the instruction. After accessing
the operand, the contents of this register are automatically incremented
to point to the next consecutive memory location.(R1)+.
Here one register reference,one memory reference and one ALU
operation is required to access the data.
Example:
 Add R1, (R2)+ // OR
 R1 = R1 +M[R2]
R2 = R2 + d
 Useful for stepping through arrays in a loop. R2 – start of array d – size
of an element
 Auto indexed ( decrement mode): Effective address of the operand is
the contents of a register specified in the instruction. Before accessing
the operand, the contents of this register are automatically
decremented to point to the previous consecutive memory location. –
(R1)
Here one register reference,one memory reference and one ALU
operation is required to access the data.
Example:
Add R1,-(R2) //OR
R2 = R2-d
R1 = R1 + M[R2]
Auto decrement mode is same as auto increment mode. Both can also
be used to implement a stack as push and pop . Auto increment and Auto
decrement modes are useful for implementing “Last-In-First-Out” data
structures.
 Direct addressing/ Absolute addressing Mode (symbol [ ]): The
operand’s offset is given in the instruction as an 8 bit or 16 bit
displacement element. In this addressing mode the 16 bit effective
address of the data is the part of the instruction.
Here only one memory reference operation is required to access the
data.

Example:ADD AL,[0301] //add the contents of offset

address 0301 to AL
 Indirect addressing Mode (symbol @ or () ):In this mode address
field of instruction contains the address of effective address.Here two
references are required.
1st reference to get effective address.
2nd reference to access the data.
Based on the availability of Effective address, Indirect mode is of two
kind:
1. Register Indirect:In this mode effective address is in the register,
and corresponding register name will be maintained in the address
field of an instruction.
Here one register reference,one memory reference is required to
access the data.
2. Memory Indirect:In this mode effective address is in the memory,
and corresponding memory address will be maintained in the
 address field of an instruction.
Here two memory reference is required to access the data.
 Indexed addressing mode: The operand’s offset is the sum of the
content of an index register SI or DI and an 8 bit or 16 bit
displacement.
Example:MOV AX, [SI +05]
 Based Indexed Addressing: The operand’s offset is sum of the
content of a base register BX or BP and an index register SI or DI.
Example: ADD AX, [BX+SI]
Based on Transfer of control, addressing modes are:
o PC relative addressing mode: PC relative addressing mode is
used to implement intra segment transfer of control, In this mode
effective address is obtained by adding displacement to PC.
o EA= PC + Address field value
PC= PC + Relative value.
o Base register addressing mode:Base register addressing
mode is used to implement inter segment transfer of control.In
this mode effective address is obtained by adding base register
value to address field value.
EA= Base reg
operations in the instruction set

Some operations that are part of an instruction set include:

 Addressing modes: Determines how and where an operand is fetched from memory
 Memory reference instructions: These instructions are divided into three parts: mode,
opcode, and address
 Registers: These are volatile memory systems that provide the CPU with quick
access to information it is currently using
 Memory address: This is specified as part of the instruction
 Bit manipulation instructions: These instructions shift or rotate bits within a value,
which is often used for effective multiplication or division
 Comparison operations: These operations evaluate two values and establish a
condition flag based on the outcome
Instruction set commands are used for a variety of purposes,
including: Data handling and memory management and Arithmetic and
logic operations.
arithmetic and logical
What is ALU?
ALU is a digital circuit that provides arithmetic and logic operations. It is
the fundamental building block of the central processing unit of a computer.
A modern central processing unit(CPU) has a very powerful ALU and it is
complex in design. In addition to ALU modern CPU contains a control unit
and a set of registers. Most of the operations are performed by one or
more ALUs, which load data from the input register. Registers are a small
amount of storage available to the CPU. These registers can be accessed
very fast. The control unit tells ALU what operation to perform on the
available data. After calculation/manipulation, the ALU stores the output in
an output register.

The CPU can be divided into two sections: the data section and
the control section. The data section is also known as the data path.
BUS
In early computers BUS were parallel electrical wires with multiple
hardware connections. Therefore a bus is a communication system that
transfers data between components inside a computer, or between
computers. It includes hardware components like wires, optical fibers, etc
and software, including communication protocols. The Registers, ALU,
and the interconnecting BUS are collectively referred to as data paths.
Types of the bus
There are mainly three type of bus:-
1. Address bus: Transfers memory addresses from the processor to
components like storage and input/output devices. It’s one-way
communication.
2. Data bus: carries the data between the processor and other
components. The data bus is bidirectional.
3. Control bus: carries control signals from the processor to other
components. The control bus also carries the clock’s pulses. The
control bus is unidirectional.
The bus can be dedicated, i.e., it can be used for a single purpose or it
can be multiplexed, i.e., it can be used for multiple purposes. when we
would have different kinds of buses, different types of bus organizations
will take place.
Registers
In Computer Architecture, the Registers are very fast computer memory
which is used to execute programs and operations efficiently. but In that
scenario, registers serve as gates, sending signals to various components
to carry out little tasks. Register signals are directed by the control unit,
which also operates the registers.
The following list of five registers for in-out signal data storage:
1. Program Counter
A program counter (PC) is a CPU register in the computer processor
which has the address of the next instruction to be executed
from memory. As each instruction gets fetched, the program counter
increases its stored value by 1. It is a digital counter needed for faster
execution of tasks as well as for tracking the current execution point.
2. Instruction Register
In computing, an instruction register (IR) is the part of a CPU’s control
unit that holds the instruction currently being executed or decoded. The
instruction register specifically holds the instruction and provides it to
the instruction decoder circuit.
3. Memory Address Register
The Memory Address Register (MAR) is the CPU register that either
stores the memory address from which data will be fetched from the
CPU, or the address to which data will be sent and stored. It is a
temporary storage component in the CPU(central processing unit) that
temporarily stores the address (location) of the data sent by the
memory unit until the instruction for the particular data is executed.
4. Memory Data Register
The memory data register (MDR) is the register in a computer’s
processor, or central processing unit, CPU, that stores the data being
transferred to and from the immediate access storage. Memory data
register (MDR) is also known as memory buffer register (MBR).
5. General Purpose Register
General-purpose registers are used to store temporary data within
the microprocessor. It is a multipurpose register. They can be used either
by a programmer or by a user.
What is Data Path?
Suppose that the CPU needs to carry out any data processing action,
such as copying data from memory to a register and vice versa, moving
register content from one register to another, or adding two numbers in
the ALU. Therefore, whenever a data processing action takes place in the
CPU, the data involved for that operation follows a particular path, or data
path.
Data paths are made up of various functional components, such as
multipliers or arithmetic logic units. Data path is required to do data
processing operations.
One Bus Organization

In one bus organization, a single bus is used for multiple purposes. A set
of general-purpose registers, program counters, instruction registers,
memory address registers (MAR), memory data registers (MDR) are
connected with the single bus. Memory read/write can be done with MAR
and MDR. The program counterpoints to the memory location from where
the next instruction is to be fetched. Instruction register is that very
register will hold the copy of the current instruction. In the case of one bus
organization, at a time only one operand can be read from the bus.
As a result, if the requirement is to read two operands for the operation
then the read operation needs to be carried twice. So that’s why it is
making the process a little longer. One of the advantages of one bus
organization is that it is one of the simplest and also this is very cheap to
implement. At the same time a disadvantage lies that it has only one bus
and this “one bus” is accessed by all general-purpose registers, program
counter, instruction register, MAR, MDR making each and every operation
sequential. No one recommends this architecture nowadays.
Two Bus Organization
To overcome the disadvantage of one bus organization another
architecture was developed known as two bus organization. In two bus
organizations, there are two buses. The general-purpose register can
read/write from both the buses. In this case, two operands can be fetched
at the same time because of the two buses. One bus fetch operand for
ALU and another bus fetch for register. The situation arises when both
buses are busy fetching operands, the output can be stored in a
temporary register and when the buses are free, the particular output can
be dumped on the buses.
There are two versions of two bus organizations, i.e., in-bus and out-bus.
From in-bus, the general-purpose register can read data and to the out
bus, the general-purpose registers can write data. Here buses get
dedicated.
Three Bus Organization
In three bus organizations we have three buses, OUT bus1, OUT bus2,
and an IN bus. From the out buses, we can get the operand which can
come from the general-purpose register and evaluated in ALU and the
output is dropped on In Bus so it can be sent to respective registers. This
implementation is a bit complex but faster in nature because in parallel
two operands can flow into ALU and out of ALU. It was developed to
overcome the busy waiting problem of two bus organizations. In this
structure after execution, the output can be dropped on the bus without
waiting because of the presence of an extra bus. The structure is given
below in the figure.
The main advantages of multiple bus organizations over the single bus
are as given below.
1. Increase in size of the registers.
2. Reduction in the number of cycles for execution.
3. Increases the speed of execution or we can say faster execution

4. classification of processors (RISC, CISC,

and their comparison).

What is RISC?
RISC stands for Reduced Instruction Set Computers. RISC is a microprocessor and
as the name indicates, it performs a smaller number of computer instructions. Thus,
it has a high speed to operate. It works on a fixed instruction format that keeps less
than 100 instructions to be processed with a register-based instruction used by a few
simple addressing modes. The LOAD/STORE is the only instruction used to access
the memory as it is a compiler development mechanism.
What is CISC?
CICS stands for Complex Instruction Set Computer. CISC is the kind of chip that can
be easily programmed and makes the best and efficient use of memory. The main
motive of CISC is to make compiler development easy and simple. There is no need
for the machine to generate instructions for the processor as CISC eliminates the
need.

Difference between RISC and CISC Processor

S.No. RISC CISC

1. RISC is a reduced instruction set. CISC is a complex instruction set.

2. The number of instructions is less as compared The number of instructions is more as compared
to CISC. to RISC.

3. The addressing modes are less. The addressing modes are more.

4. It works in a fixed instruction format. It works in a variable instruction format.

5. The RISC consumes low power. The CISC consumes high power.

6. The RISC processors are highly pipelined. The CISC processors are less pipelined.

7. It optimizes the performance by focusing on It optimizes the performance by focusing on

software. hardware.

8. Requires more RAM. Requires less RAM

types of interrupts;
What is an Interrupt?
The interrupt is a signal emitted by hardware or software when a process
or an event needs immediate attention. It alerts the processor to a high-
priority process requiring interruption of the current working process. In
I/O devices one of the bus control lines is dedicated for this purpose and
is called theInterrupt Service Routine (ISR) .
Interrupts play a key role in managing CPU tasks and system
performance. If you’re preparing for GATE or simply want to master
operating systems, the GATE CS Self-Paced Course offers a solid
foundation.
When a device raises an interrupt at let’s say process i, the processor first
completes the execution of instruction i. Then it loads the Program Counter
(PC) with the address of the first instruction of the ISR. Before loading the
Program Counter with the address, the address of the interrupted
instruction is moved to a temporary location. Therefore, after handling the
interrupt the processor can continue with process i+1.
While the processor is handling the interrupts, it must inform the device
that its request has been recognized so that it stops sending the interrupt
request signal. Also, saving the registers so that the interrupted process
can be restored in the future, increases the delay between the time an
interrupt is received and the start of the execution of the ISR. This is
called Interrupt Latency.
Types of Interrupt
Event-related software or hardware can trigger the issuance of interrupt
signals. These fall into one of two categories: software interrupts or
hardware interrupts.
1. Software Interrupts
A sort of interrupt called a software interrupt is one that is produced by
software or a system as opposed to hardware. Traps and exceptions are
other names for software interruptions. They serve as a signal for the
operating system or a system service to carry out a certain function or
respond to an error condition. Generally, software interrupts occur as a
result of specific instructions being used or exceptions in the operation. In
our system, software interrupts often occur when system calls are made.
In contrast to the fork() system call, which also generates a software
interrupt, division by zero throws an exception that results in the software
interrupt.
A particular instruction known as an “interrupt instruction” is used to create
software interrupts. When the interrupt instruction is used, the processor
stops what it is doing and switches over to a particular interrupt handler
code. The interrupt handler routine completes the required work or
handles any errors before handing back control to the interrupted
application.
2. Hardware Interrupts
In a hardware interrupt, all the devices are connected to the Interrupt
Request Line. A single request line is used for all the n devices. To
request an interrupt, a device closes its associated switch. When a device
requests an interrupt, the value of INTR is the logical OR of the requests
from individual devices.
Hardware interrupts are further divided into two types of interrupt
 Maskable Interrupt: Hardware interrupts can be selectively enabled
and disabled thanks to an inbuilt interrupt mask register that is
 commonly found in processors. A bit in the mask register corresponds
to each interrupt signal; on some systems, the interrupt is enabled
when the bit is set and disabled when the bit is clear, but on other
systems, the interrupt is deactivated when the bit is set.
 Spurious Interrupt: A hardware interrupt for which there is no source
is known as a spurious interrupt. This phenomenon might also be
referred to as phantom or ghost interrupts. When a wired-OR interrupt
circuit is connected to a level-sensitive processor input, spurious
interruptions are typically an issue. When a system performs badly, it
could be challenging to locate these interruptions.
Sequences of Events Involved in Handling an IRQ(Interrupt
Request)
 Devices raise an IRQ.
 The processor interrupts the program currently being executed.
 The device is informed that its request has been recognized and the
device deactivates the request signal.
 The requested action is performed.
 An interrupt is enabled and the interrupted program is resumed.
Flowchart of Interrupt Handling Mechanism
The Image below depicts the flowchart of interrupt handling mechanism

Step 1:- Any time that an interrupt is raised, it may either be an I/O
interrupt or a system interrupt.
Step 2:- The current state comprising registers and the program counter is
then stored in order to conserve the state of the process.
Step 3:- The current interrupt and its handler is identified through the
interrupt vector table in the processor.
Step 4:- This control now shifts to the interrupt handler, which is a function
located in the kernel space.
Step 5:- Specific tasks are performed by Interrupt Service Routine (ISR)
which are essential to manage interrupt.
Step 6:- The status from the previous session is retrieved so as to build on
the process from that point.
Step 7:- The control is then shifted back to the other process that was
pending and the normal process continues.
Managing Multiple Devices
When more than one device raises an interrupt request signal, then
additional information is needed to decide which device to be considered
first. The following methods are used to decide which device to select:
Polling, Vectored Interrupts, and Interrupt Nesting. These are explained
below.
 Polling: In polling, the first device encountered with the IRQ bit set is
the device that is to be serviced first. Appropriate ISR is called to
service the same. It is easy to implement but a lot of time is wasted by
interrogating the IRQ bit of all devices.
 Vectored Interrupts: In vectored interrupts, a device requesting an
interrupt identifies itself directly by sending a special code to the
processor over the bus. This enables the pro cessor to identify the
device that generated the interrupt. The special code can be the
starting address of the ISR or where the ISR is located in memory and
is called the interrupt vector.
 Interrupt Nesting: In this method, the I/O device is organized in a
priority structure. Therefore, an interrupt request from a higher-priority
device is recognized whereas a request from a lower-priority device is
not. The processor accepts interrupts only from devices/processes
having priority.
Processors’ priority is encoded in a few bits of PS (Process Status register) .
It can be changed by program instructions that are written into the PS.
The processor is in supervised mode only while executing OS routines. It
switches to user mode before executing application programs.
What is Interrupt Latency?
The amount of time between the generation of an interrupt and its
handling is known as interrupt latency. The number of created interrupts,
the number of enabled interruptions, the number of interrupts that may be
handled, and the time required to handle each interrupt all affect interrupt
latency. When the device generating the interrupt needs a specific length
of time to generate the interrupt, interrupt latency is required. For
instance, if a printer is printing paper, the computer needs to stop the
printing program and wait for the document to finish printing. The interrupt
latency is the amount of time the computer has to stop the program from
operating.
How CPU React when Interrupt occurs?
 Interrupt Detection: The CPU continuously video displays unit interrupt
lines or alerts from diverse resources, consisting of hardware gadgets
or software program commands, to hit upon interrupt requests.
 Interrupt Acknowledgment: Upon detecting an interrupt request, the
CPU acknowledges the interrupt using sending an acknowledgment
sign to the interrupting device or software program.
 Interrupt Handling: The CPU identifies the form of interrupt primarily
based on its supply, together with a hardware interrupt from a device or
a software interrupt from a training. It then seems the cope with the
corresponding interrupt handler habitual within the interrupt vector
desk.
 Context Saving: Before moving manipulate to the interrupt handler
ordinary, the CPU saves the present-day execution context, inclusive
of the program counter (PC), processor state, and any applicable sign-in
contents, onto the stack or in the devoted garage.
 Transfer Control: The CPU transfers manipulation to the interrupt
handler ordinary with the aid of placing this system counter (PC) to the
address of the handler habitual retrieved from the interrupt vector desk.
 Interrupt Servicing: The interrupt handler habitual executes to carrier
the interrupt. It plays responsibilities to interrupt, such as reading facts
from a device, processing enter/output operations, or coping with a
software program request.
Triggering Methods
Every interrupt signal input is intended to be activated by a certain signal
edge (level change) or a logic signal level. Level-sensitive inputs make
constant requests for processor attention as long as they are treated with
a specific logic level (high or low). Edge-sensitive inputs are responsive to
signal edges; a service request will latch on to a specific (rising or falling)
edge. When the interrupt handler runs, the CPU resets the latch.
 Level-Trigger: The interrupt signal must be held at its specific active
logic level (high or low) to request a level-triggered interrupt. A level-
triggered interrupt is triggered when a device drives the signal to the
active level and maintains it there. When the CPU instructs it to do so,
usually after the device has been serviced, it denies the signal.
 Edge-Trigger: An interrupt that is caused by a level change on the
interrupt line—either a rising or lowering edge—is known as an edge-
triggered interrupt (low to high). A pulse is driven onto the line and
released to its inactive state by a device that wishes to indicate an
interrupt. It can be necessary to use specialized hardware to detect the
pulse if polled I/O is unable to pick it up due to its short duration.
Benefits of Interrupt
 Real-time Responsiveness: Interrupts permit a system to reply
promptly to outside events or signals, permitting real-time processing.
 Efficient Resource usage: Interrupt-driven structures are more
efficient than system that depend on busy-waiting or polling strategies.
Instead of continuously checking for the incidence of event, interrupts
permit the processor to remain idle until an event occurs, conserving
processing energy and lowering energy intake.
 Multitasking and Concurrency: Interrupts allow multitasking with the
aid of allowing a processor to address multiple tasks concurrently.
 Improved system Throughput: By coping with occasions
asynchronously, interrupts allow a device to overlap computation with
I/O operations or other responsibilities, maximizing system throughput
and universal overall performance.
