DIGITAL DESIGN WITH HDL

Chapter 2: Structural model design

Computer Engineering – CSE – HCMUT 1

 Structure model

• A schematic in text form

• Structural module can be designed using (instances):
– Primitive gates (predefined simple gates)
– User defined modules (previously designed and tested)
• Interconnections between instances are specified using
nets data-type

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 2

 Structural model - design steps
1. Create module interface
– Define the module name
– Declare the port list
2. Declare the internal wires needed to connect gates
3. Instantiate the primitive gates in the circuit
4. Instantiate user defined modules in the circuit (if required)
5. Put the names of the wires in the correct port locations of the
gates
– For primitives, outputs always come first
– For user defined instantiation, use connection methods (discussed
later)
Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 3
 Example
module half_adder_struc(a, b, sum, cout);
input a, b;
output sum, cout;
module fulladder_struc(a, b, cin, sum, cout);
xor(sum, a, b); input a, b, cin;
and(cout, a, b); output sum, cout;
Connection wires wire c1, c2, s1;
endmodule
User defined modules half_add_struc PARTSUM(a, b, s1, c1);
half_add_struc SUM(s1, cin, sum, c2);

Primitive gates or(cout, c2, c1);

endmodule

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 4

 Primitive gates

• Verilog provides a set of gate primitives (part of language)

– One or more scalar inputs and only one scalar output
• eg. and, nand, or, nor, xor, xnor, not, buf, etc.
– Names of primitive are keywords
– Known “behavior”
– Cannot access “inside” description
• Can also model at the transistor level
– Most people don’t, we won’t
• Note: Flip-flops are not primitives
Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 5
 Primitive gates
• Output port is always the first port
– Inputs follows (unlimited) - except not
nand (y, a, b, c);
• Optional: instantiation name & delay

nand N1 (y, a, b, c);

Optional instantiation name Inputs
syntax:
gate_type delay inst1 (output_1, input_11, input_12, . . . , input_1n),
delay inst2 (output_2, input_21, input_22, . . . , input_2n),
...
delay instm (output_m, input_m1, input_m2, . . . ,input_mn);

Optional
Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 6
 Gate delay

• All gates have propagation delay • Types of delay

– Time for processing signals – Rise delay: 0 → 1
– Technology-dependent – Fall delay: 1 → 0
– Only simulation cares delay – Turn-off delay: 0,1 → x, z
– Synthesis process will not take
into account

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 7

 Gate delay - Verilog

• Can specify all three types of delay

– But, mainly use one value for all

Syntax: #(rise, fall, turn-off)

Mainly used: #delay

• Notes:
– All values must be constant expression
– Can be specify more precisely: <minimum : typical : maximum>

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 8

 Example
module log_eqn_sop8 (x1, x2, x3, x4, z1);
input x1, x2, x3, x4;
output z1;
wire net1, net2;
and #3 inst1 (net1, x1, x2);
and #3 inst2 (net2, ~x3, x4);
or #5 inst3 (z1, net1, net2);
endmodule

Waveform generated by icarus-verilog and displayed by gtkwave

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 9

 Data types: wire

• Verilog defines two data types

– Net: physical wire or group wires (bus) for connecting
hardware elements
• wire, tri, wand,…
– Register: storage elements whose values are retained until
updated
• reg
• Structural model uses only net data type, especially wire
– Values are determined by logic driving the net

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 10

 Scalar & vector signals

• Scalar: single/one bit - do not need to specify the size

– wire a; //the size of signal a is one bit
• Vector: multiple bit (bus) - specify size using range
– Syntax: [MSB : LSB]
• MSB, LSB ∈ ℤ, constant expression

– Size of the vector: | MSB − LSB | + 1

• MSB > LSB✓
• MSB < LSB✓
– Example:
• wire [3:0] a; //4 bit a bus
• wire [1:4] b; //4 bit b bus
– Can access the whole vector, a part of vector, or a single bit

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 11

 Vectors
• Part select
– Syntax: <name>[MSB : LSB]
– The relationship between MSB and LSB must be in accordance with
declaration
– Example:
• wire [3:0] a;
• a[3:1]; //correct part-select
• a[1:2]; //wrong part-select because of reverse order
• a[4:2]; //wrong part-select because of out-of-range
• Bit select
– Syntax: <name>[posi on]
– Example: a[1]; a[3];

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 12

ti
 Connections

• Port connection rules

– input:
• Internally: net
• Externally: reg or net
– output:
• Internally: reg or net
• Externally: net
– inout:
• Internally/externally: net
• Error messages will be
indicated if violated
Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 13
 Intermodules connections

• Method 1: positional or implicit connections

– Used for the primitive gates (no choice)
– Look like function/procedure call in software
– Acceptable with few ports or interchangeable ports
– Need to remember the position of each port
• Method 2: connecting by port names
– Easy to read and manage
– No need to follow the order of ports declared
– Syntax: .<port name>(<connected signal>)

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 14

 Example
module decoder(In, En, Out);
input [1:0] In;
input En;
output [3:0] Out;
….
endmodule module name(…);
module positional(…); wire [1:0] nIn;
wire [1:0] pIn; wire nEn;
wire pEn; wire [3:0] nOut;
wire [3:0] pOut; ….
…. decoder D1(.En(nEn),
decoder D1(pIn, pEn, pOut); .In(nIn),
endmodule .Out(nOut));
endmodule
Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 15
 Empty port connections
• General rules of unconnected ports
– Input: high-impedance state (high-Z)
– Output: unused port
• Note: do not leave an input port empty due to unmanageable high-Z
states
– Connect the input to the inactive value
• Active high ⇒ 0; active low ⇒ 1
• Make a port unconnected
– Position method: a blank between two commas
• decoder D1(pIn, , pOut);
– Name method: empty signal name
• decoder D1(.In(nIn), .En(), .Out(nOut));

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 16

 Hierarchy and scope

• A module cannot access “internal” signals of instantiations

– Must make a port when needed
module add8bit(cout, sum, a, b);
output [7:0] sum;
To access cout6 when instantiating
output cout;
input [7:0] a, b; the add8bit must output cout6
wire cout0, cout1,… cout6;
FA A0(cout0, sum[0], a[0], b[0], 1’b0);
FA A1(cout1, sum[1], a[1], b[1], cout0);
…
FA A7(cout, sum[7], a[7], b[7], cout6);
endmodule

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 17

 Design example

• A 4:1 multiplexer diagram

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 18

 Design example - Verilog code
module mux_4to1 (d, s, enbl, z1);
input [3:0] d;
input [1:0] s;
input enbl;
output z1;

not inst1 (net1, s[0]),

inst2 (net2, s[1]);

and inst3 (net3, d[0], net1, net2, enbl),

inst4 (net4, d[1], s[0], net2, enbl),
inst5 (net5, d[2], net1, s[1], enbl),
inst6 (net6, d[3], s[0], s[1], enbl);

or inst7 (z1, net3, net4, net5, net6);

endmodule Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 19
 Exercises
1. Using Verilog HDL to implement a three bit comparator that consists of two
3-bit inputs a, b and three 1-bit output a_lt_b, a_eq_b, and a_gt_b to
indicate if a is less than b, a is equal to b, and a is greater than b,
respectively. Given that the following boolean expressions can be used to
compare (a[2], b[2]: MSB):

(a < b) = a[2] ⋅ b[2] + a[2] ⊕ b[2] ⋅ a[1] ⋅ b[1]

+a[2] ⊕ b[2] ⋅ a[1] ⊕ b[1] ⋅ a[0] ⋅ b[0]

(a = b) = a[2] ⊕ b[2] ⋅ a[1] ⊕ b[1] ⋅ a[0] ⊕ b[0]

(a > b) = a[2] ⋅ b[2] + a[2] ⊕ b[2] ⋅ a[1] ⋅ b[1]

+a[2] ⊕ b[2] ⋅ a[1] ⊕ b[1] ⋅ a[0] ⋅ b[0]

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 20

 Exercise
2. Using Verilog HDL to implement a mod 8 counter whose diagram is shown
as follow. Assume that there exist a D-flip-flop module whose interface is
shown below

module dff(input clk, d, output q, qbar, input rst);

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 21

 Answer - exercise 1

• Block diagram

Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 22

 Answer - exercise 1
module comparator3 (a, b, a_lt_b, a_eq_b, a_gt_b);
input [2:0] a, b;
output a_lt_b, a_eq_b, a_gt_b;
and inst1 (net1, ~a[2], b[2]);
xnor inst2 (net2, a[2], b[2]),
inst3 (net3, a[1], b[1]),
inst4 (net4, a[0], b[0]);
and inst5 (net5, a[2], ~b[2]),
inst6 (net6, net2, ~a[1], b[1]),
inst7 (net7, net2, net3, ~a[0], b[0]),
inst9 (net9, net2, a[1], ~b[1]),
inst10 (net10, net2, net3, a[0], ~b[0]);
//generate the outputs
or inst11 (a_lt_b, net1, net6, net7),
inst12 (a_gt_b, net5, net9, net10);
and inst8 (a_eq_b, net2, net3, net4);
endmodule Digital Design with HDL (c) Cuong Pham-Quoc/HCMUT 23
 The end

Computer Engineering – CSE – HCMUT 24