Anna University ECE - Reg 2021

1st Semester 2nd Semester 3rd Semester

Random Process & Linear
Professionsal English I Professional English II
Algebra
Statistics and Numerical C Programming & Data
Matrices and Calculas Methods Structures
Engineering Graphics Signals and Systems
Engineering Physics
Physics for Electronics
Electronic Devices and Circuits
Engineering
Engineering Chemistry
Electrical and Instrumentation Control Systems
Engineering
Problem Solving & Python
Programming Circuit Analysis Digital Systems Designs

4th Semester 5th Semester 6th Semester

Electromagnetic Fields Embedded System & IOT

Wireless Communication Design

Networks & Security Artificial Intelligence &

VLSI and Chip Design
Machine Learning
Linear Integrated Circuits Transmission Lines & RF Open Elective I
Systems
Digital Signal Processing Professional Elective I Professional Course III

Communication Systems Professional Elective II Professional Course IV

Environmental Sciences &

Sustainability Mandatory Course I Mandatory Course II

7th Semester 8th Semester

Human Values & Ethics Project Work

Elective Management

EEE ECE
Open Elective II CSE
Open Elective III Click on clouds to navigate
other departments
Open Elective IV

MECH CIVIL
http://www.poriyaan.in
4931_Grace college of Engineering,Thoothukudi

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

B.E. Electronics and Communication Engineering

E
Anna University Regulation: 2021
CO
EC 3352 –DIGITAL SYSTEM DESIGN

II Year / III Semester

E
AC

Hand Written Notes

GR

Unit – IV

ASYNCHRONOUS SEQUENTIAL CIRCUITS

Prepared by,
Mrs. E. M. Uma selvi , AP/ECE

EC3352_DSD

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4931_Grace college of Engineering,Thoothukudi

E
Unit – IV

CO
ASYNCHRONOUS SEQUENTIAL CIRCUITS
E
AC
GR

EC3352_DSD

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 4931_Grace college of Engineering,Thoothukudi
NIT- 1
CIRCUI TS
AsyNCE1Ro NousS SEQUENTIAL

htnodutuen ciucuuh do not

do no
A e e n t a l

Auncheros change e nteual

but the
Ule clock Pulto
a dhan n
thee
ush en
Mtto Occe Only

o npt Vauialles.
aynchare
ayn
elemext
The hneme unclocked pl,

E
ethe
Squential cicuit ae
CO
tune2 delay elemer
crteit
easynchiensus
seGeental
Block
Block iagam
CE

n
(emlralirml
22 'r Op
Valialde
RA

input citewl
Vovalle Zm
G

k Secendeay enctahn
Valialles
Voualles

(Pres to) Dehy (Pretcr taie)

Dela
The twe p e e- ychoneus Joguotial caul

Furdamental mude cait

modle Ciuà
Pulse
EC3352_DSD

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 4931_Grace college of Engineering,Thoothukudi
fendanestal ode Cucit
cucut
* i/P Vabiatdes change only cwhen he

Jtalle

xOnly Vaialules con change at a J "

time
P au Jevel 4not pules elemeL
Ate ued asm@mey
Delay June
Hode Ciucuut
feulle
levek
pulses
inctcad o
vaualles a
n
imultanebuy
Pulke dhould hot occ
npuct
E lneg
CO
mem8y eknek
as a
cused
Fhp eps aa COmmmy

Only tho
Yp Vaalleae cueol
bth.
o t n , Lut rst
CE

9L
Complermented
ncomplemeted

CiACt
Pulte. Kode
Derign 4 s
A ta
tete
t
doagoam
RA

a
draw
stales

Step; ine dheuit.

C U h c u i t .

talle of
96
stato
ot stata. talule
G

S t e p 2 : M i n i m i z e

astignment
Jlate te l
le caAOd
e u od
Step 3 Do te
t e
tlop
tpe o
cheese
cheote
Step 4
tep Cxcitatbn tib
clet emine talue o cicuit
OXcitaton

Steps: Constuut leip-Hop iL:

tho 0p egunlt
tep 6 Leteumine k- mep implpcat

Cuatuo
Asug yptops R
logic duaqra ates

EC3352_DSD

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4931_Grace college of Engineering,Thoothukudi
PhoblemO
ccuit hasing us
pulue mocde
gn Oesign a
2
e 2
ihe
l
as houn i
oneg I, X 2 DneDne %
sheld produce
an Pul4o. th
The chcuit
sOgiiOrca
cuth lat p pulsa
Cercude 3hoild
-JqLionCo.

AJo ethbe
pulse AsAig
Outyout
produca
pube2
P Paa z
Moda
2 vcut

E
Jtep t e t So lho. ho. lait w a l
CO
Sdethe ogueno. , -2 0ccued
S e te eguenca C-X2-X bi leo
CE

Sto WJh the Conditio gien o talle

ehred wtth , 4 og.
RA

Skato talo

Pruent Neatd statn, op z'

Stato
G

Sa/ S1lo
t -
Sofo
Step 3: Stato duaga4.lo

lo

EC3352_DSD

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Letcollege
: ofoo
Engineering,Thoothukudi
So1 S 10 e
hee. Jtate Vaialile & i stata auqnmen s
Stote ale wish augnmert
Peekt

S
sbep S Osing eccitttia
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State
E
CO
NeNt ato
PneAnt Fe Flop ioputi
Stata

A
CE

o
RA

Sbep6 K map t 4e
e T
As X
G

eAX,67

EC3352_DSD
X6 www.Poriyaan.in
4931_Grace college of Engineering,Thoothukudi

Step 7 Logic diaqran.

CP

Asunchshoud equontial crcu

uhtai4

Preent NOt slut

E
Stabla o tata
CO
t ato Stalal

00
CE

State tall
d
Flou a l l e
RA
G

TS1ansito talla

b, o utput

Flow talla 1olo

EC3352_DSD

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 4931_Grace college of Engineering,Thoothukudi
Ra res
Atrta
X Race CDndutio uhen oL mela
L
Vaualle change Mesprua te
thoi valte in
a change. un Jnput Vavaldos

Race
R ace canditim Caes Jkat. Vaialle te
an uhprecidalla. manne
ehorge
i state Vavaluk. change -b9 d
en delay

el given ip, then

due te dHfeonca
Vasualule ould hange.aute

Vaviall
E could Change a
CO
Theete Jtat
O0oi||
O0 ol |I

naJtalule
stata deos rot depenok on

change, it i
CE

Jkato Valialle
in wich
eRde
hon-CUtical Aace
lde wich the
Cn
RA

firal steta Cepend

rac
Clitical
Vavallo. chage it s
stato
G

tianlion N
osble tanutin

0 Possible
O0
00 Oo 00
O0O
)
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10
Non- Cxiticod ACa
directcd to
direetcd
to
l

an
e le.
.

aces, i
C eCuutt

dvoid
ares,
talule. Mates
X To
7o jhtesmediata crste

iame.
harye
thAogh Va
V vvaall
i le
e..

Atate -
tatu
-

wvgue.
wth
EC3352_DSD

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 Crcit makes bandi
4931_Grace college of Engineering,Thoothukudi
a asunthtaLs
hen Cstable.
s ,cye
t a t ee
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cutical sae t
Techniques e nmert

tata adig
Shated Jou
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state
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Shaed JO Jtat

uucch
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Dntroduce
at
at y dna

E
stata.Yavialle
Can charge
CO
tanstbn
hen Atato
time
bol
a brol
CE

Race ae
COndita
Races
RA

C d lo
Une hot Stato aign mert

Onley Vaualle is ackive. /et fel eah

G

cne

stato tale

Trthodue hew intenal states te avoid Jace

Stert Valialsles
Ctat Je 2,72
F 3 F2 F
A

8c
EC3352_DSD

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 annion OrnA to B is
o0d
4931_Grace college of Engineering,Thoothukudi to
Two yaaLe4 dhange Tkotolog. odditionel stata
indtrodueodl. 6.DoI
tctt A s t a t hanitibn
o!
- E 8.
Ha zalal:

Hazaudt hio un atedsuit ching

barsiert

6 pike, algutch that ay

eppeas at

Maun caue o hazads

E alieunc tn
CO
pagatie alelays at diesont pabhs

m a y aPpeaL th
ale Velue
Cembinational ccuutt Temp etaiy
CE

Sequontial ciscuits

ynohionous
dYous Nb pwblem
RA

Wsong Stalile tato

Psynchsondus tiTuwt

pe e lHo2alda
G

Static dazalos
Static 'o Mazaid
Static Raz2aids.

2 Dynamic ho zosds Static 'o Hozard

Stotic Hazald
geerte
momentaily g9erte
momertaidy

Omentauly goe to |¥ p tha olp

p Stata1 ohen
m

hon
te o/p te temain tn
Stat'o te emaun n
Oxpected

State o ' .
epecteo oatic
Stato Hazald

EC3352_DSD

Stabe
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4931_Grace college of Engineering,Thoothukudi

Dunami cHazald
e
* When he op
supposed

he
harg
c

ircuit
t mBR anuontt
taniont
my go thiough
may
a tatie hazad,
le eliminated.
D an

t gMoupirg
y en
clesur9

(e)

liminatng
E
dazakds
CO
Conside the tuncub
FC 6,) = Z CuS,6,7)
CE

BC
RA

F Bc +AB
G

10->

Dnitially, arbicdes -BrC I,

Then AND gate o/p u 4 OR gato p *i
when te i/p e Changes om to o

EC3352_DSD

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 4931_Grace college of Engineering,Thoothukudi
inveLte
Due
Propagotuo delou in to
n tha

ba
eheta
Lueheta AND qato chang
cAND at1eCmes ta *
olplp ,4

skelt peiod tire

the propagatin elelay, te p F

yAte
A gtes
ieccmos
eas
vecaus A ND gato-2 output

eli
o eli minalo Ba zatdi, ctuit

edurdant gates
te dhe
ef

E
¥Additisn

9et pndutt
CO
aue mtemu,
ka
Enclsse.
gioypings.
eth
that oyelaps
tem
CE
RA

ovelap
G

diagam
Kazatd hlee gic

A
D F

3in
3 input
ptt
independent

is
AND
gat -3
EC3352_DSD

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4931_Grace college of Engineering,Thoothukudi

erctial Hazaid
Ao9ontial
cinet
OccLJ th aynchiêneus
to ncglualL delas aloro
Casco dua

that oliginato om Aamo.

Ot mehe paths

Input
Cannet le. ceuected. ly adding ridat
ateu as tabc hazaidd.

can Le csikncted yadjuuting tho ambut

-tha ambu

E
CO
pak,
un ho aftected
edelays
The pro Hen alepends n thepantteaulan
The
Clcit wod te tima cfdlehy
CE

encourteled in yavos paths.

RA

sqDeign a ha zard oe. circuit to mplemest

Design
folbusogtnctio A
the
B,C,DEEm3,62s
G

k-map with ha2ad

CD

A'eD A'BCA8D.
EC3352_DSD

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 K- map Hazail a
4931_Grace college of Engineering,Thoothukudi
-map e row

A'cD t8(D
F A''b + Alec t+ ReD+

crouit u gen Lolo

leloon,
azad Rao
C D

E
CO
D
CE

D
RA
G

EC3352_DSD

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 Chat with Lecture Send Your Notes /
QP

Anna University ECE - Reg 2021

1st Semester 2nd Semester 3rd Semester
Random Process & Linear
Professionsal English I Professional English II
Algebra
Statistics and Numerical C Programming & Data
Matrices and Calculas Methods Structures
Engineering Graphics Signals and Systems
Engineering Physics
Physics for Electronics
Electronic Devices and Circuits
Engineering
Engineering Chemistry
Electrical and Instrumentation Control Systems
Engineering
Problem Solving & Python
Programming Circuit Analysis Digital Systems Designs

4th Semester 5th Semester 6th Semester

Electromagnetic Fields Embedded System & IOT

Wireless Communication Design

Networks & Security Artificial Intelligence &

VLSI and Chip Design
Machine Learning
Linear Integrated Circuits Transmission Lines & RF Open Elective I
Systems
Digital Signal Processing Professional Elective I Professional Course III

Communication Systems Professional Elective II Professional Course IV

Environmental Sciences &

Sustainability Mandatory Course I Mandatory Course II

7th Semester 8th Semester

Human Values & Ethics Project Work

Elective Management

EEE ECE
Open Elective II CSE
Open Elective III Click on clouds to navigate
other departments
Open Elective IV

MECH CIVIL
http://www.poriyaan.in