Lecture 1 – Welcome & Introduction

Digital Integrated Circuits

Yoonmyung Lee
[email protected]
College of Information & Communication Engineering
Sungkyunkwan University
Kang Ch. 1.9
Rabaey Ch. 1.3
Integrated Circuits & Systems Design Lab.
Course Information
 PBL (Project-Based Learning)
 온라인 사전제작 + 오프라인 수업 운영 (자율 시간 배분)
 오프라인 수업 빈도: 평균 1주일에 1번 목표
 매 주 직전 일요일까지 온라인 강의 자료 및 해당 주차 온/오프 진행 계획 공지
(월/수 수업시간은 반드시 일정을 비워야 합니다)
 온라인 수업
 이론 수업: online 위주로 진행
 월요일 수업분  화요일 자정까지 수강 완료
 수요일 수업분  목요일 자정까지 수강 완료
 오프라인 수업
 이론 수업 질의 응답 / 사례 분석
 CAD 과제 관련 tutorial / 질의응답

 Time & Place

 Assigned time slots: Mon 4:30pm-5:45pm, Wed 3:00pm-4:15pm
 Offline Lecture @ 400126

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Course Information
 Instructor
 이윤명 : Yoonmyung Lee ([email protected], Rm. 400416, 031-290-7979)
 집적회로 및 시스템 설계 연구실 (Integrated Circuits & Systems Design lab. (ICAS))
 Lab Homepage: http://icas.skku.edu
 Office Hour:
 After class
 Other time available by appointment

 Teaching Assistants
 박동현, 김정호, 이경준 (연락처 iCampus 참조)
 Office: 반도체관 400417

 i-Campus
 Official notice and other communication
 Lecture notes will be uploaded

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Textbook and References
 Lecture Notes will be the main course material
 Textbook
 CMOS Digital Integrated Circuits, 4th Edition, S.M. Kang
 Reference
 Digital Integrated Circuits, A Design Perspective, 2nd Edition, J. Rabaey

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Objectives & Prerequisites
 Objectives
 Learning the characteristics and metrics
of building blocks of digital integrated circuits

 Prerequisites
 Electronic circuits
 Basic MOS device physics, models
 Basic Boolean algebra, Logic circuits
 Netlist and HSPICE simulation environment

 Official language: Korean/English

 Handouts, and exams are all in English

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Policy
 Grading
 Attendance 5%
 Exams
 Midterm 30%
 Final 35%
 CAD Assignments 30%
 Exams and CAD assignments are equally important

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Policy
 Attendance / Participation
 Online attendance will be monitored
 Offline attendance  Electronic attendance check (전자 출결)
 Don’t be late
 Absence for medical/official reason:
– Notify instructor/TA before class
– Submit doctor’s note after class
 Active participation / good questions will count as plus

 Exams
 Midterm & Final
 ~1.5hr / ~2hr exam
 Handwritten Summary Note Allowed (1pg per exam)
 Cumulative

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Policy
 CAD Assignments
 4~5 CAD Assignments
 Tutorial will be given first for Cadence® IC design tools
 Schematic Editor + Analog Design Environment (simulation)
 Layout Editor + Verification (DRC, LVS)
 Afterwards, CAD assignments will be given: every 2~3 weeks.

 Questions
 Students are encouraged to ask questions
 No need to be shy or worry too much about other students
 It is instructor’s role to manage time/pace for questions/lecture

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Policy
 Comments on cheating
 Students are trusted in general
 Attendance check
 CAD assignment grading
 Calculator/Cell phone usage in exam
 etc…

 But cheating will be harshly punished, if caught

 Entire class can be zero-graded
 NEVER leave after attendance check

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Tentative Schedule

Week Topic Week Topic

1 Introduction 9 Midterm Exam
(9/2, 9/4) & Metrics of ICs (10/28, 10/30) Sequential Logic
2 Manufacturing Process 10 Sequential Logic
(9/9, 9/11) & Layout (11/4, 11/6)

3 11 Sequential Logic
(9/16, 9/18) Wire Models
추석연휴
(11/11, 11/13) Adder
4 12
(9/23, 9/25) CMOS Inverter Adder
(11/18, 11/20)
건학기념일

5 13 Timing
CMOS Inverter
(9/30, 10/2) (11/25, 11/27) Design Methodology
6 14 Multiplier & Shifter
(10/7, 10/9) Combinational Logic 1
한글날
(12/2, 12/4) Memory
7 Combinational Logic 1 15 Memory
(10/14, 10/16) (12/9, 12/11)

8 Combinational Logic 2 16 Final Exam

(10/21, 10/23) (12/16 or 12/18)

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What Do We Learn in Digital Integrated Circuit?

What You What You

Have Learned Use Everyday

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What Do We Learn in Digital Integrated Circuit?

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What Do We Learn in Digital Integrated Circuit?

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What Do We Learn in Digital Integrated Circuit?

Arithmetic Registers / Analog

Memory
& Logic Unit Building Blocks Circuits

Adder SRAM Logic Gates Regulators Amplifiers

Multiplier DRAM Flip Flops Sensors Clock Generator

Shifter Flash Latches Modem Timer

Others Others Others ADC Others

Covered in Digital Integrated IC Class!!

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The First Electronic Computer
 ENIAC - 1946
 The first electronic general-purpose computer
 17k Vacuum tube based, 70k R, 10k C, …
 Expensive: $500,000 (approximately $6,000,000 today)
 Power hungry, unreliable, large

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The First Transistor
 John Bardeen, Walter Brattain, and William Shockley 1947
 jointly awarded the 1956 Nobel Prize in Physics for their achievement

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The First IC
 Jack Kilby (TI) – July 1958
 Recorded his initial idea of IC, in which all passive and active components
are integrated on a single semiconductor substrate
 Robert Noyce
 Also came up with his own idea of IC half year later

Bipolar logic IC in 1960’s

ECL 3-input Gate

Motorola 1966

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MOS Integrated Circuits
 MOSFET: Metal-Oxide-Semiconductor Field Effect Transistors
 Voltage applied to insulated gate controls current between source and drain
 Low power allows very high integration
 1970’s processes usually had only nMOS transistors
 Inexpensive, but consume power while idle

Intel 1101 256-bit SRAM Intel 4004 4-bit mProc

 1980s-present: CMOS processes for low idle power

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Integrated Circuits (CPU)

Intel 4004 (`71)

8080 (`74) 8086 (`78) 80386 (`85)

Pentium (`93) Pentium4 (`00) Core2 Duo (`08)

Source:
19 Intel 3rd gen.
DigitalCore (`12)
Integrated Circuits
Moore’s Law: Then
 1965: Gordon Moore plotted transistor on each chip
 Fit straight line on semilog scale
 Transistor counts have doubled every 24 months

Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

[Moore65]
Electronics Magazine

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Moore’s Law: Now

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Technology Scaling Trend
 Biggest source of improvement is from technology scaling
 Smaller C, Lower V, smaller T

Source: http://cpudb.stanford.edu/
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Performance Trend
 Processor performance is keep improving
 Despite the degradation on improvement rate

+21%
per year

+64%
per year

Source: Jeff Preshing

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Clock Frequency Trend
 However, clock period (T) doesn’t improve much since ~2004, why?
 Main reason for change in improvement rate

Source: http://cpudb.stanford.edu/
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Microprocessor Trends
 Putting the trends altogether shows better picture…

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Power Density Trend
 Thermal dissipation limits processor performance
 Low Power Design is Important!!

Nuclear Reactor →

←Hot Plate

Source: http://cpudb.stanford.edu/
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Introduction:
Metrics of ICs

Integrated Circuits & Systems Design Lab.

What is and Why digital?

Ideal

With Noise

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How to evaluate performance/quality of IC?

 Cost

 Reliability

 Scalability

 Speed (delay, operating frequency)

 Power dissipation

 Energy to perform a function

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Cost of IC
 NRE (non-recurrent engineering) costs
 one-time cost factor
 design cost (time and effort)
 Influenced by: complexity of design, aggressiveness of spec.,
designer productivity, design methodology
 mask generation cost

 Recurrent costs
 Silicon fabrication
 Packaging, test
 proportional to volume
 proportional to chip area

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Die Cost

Single die

Wafer

From http://www.amd.com

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Yield
No. of good chips per wafer
Y 100%
Total number of chips per wafer
Wafer cost Wafer cost
Die cost  
Number of good dies Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer  
die area 2  die area

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Defects


 defects per unit area  die area 
die yield  1  
  
 is approximately 3

die cost  f (die area)4

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Reliability
 Noise = unwanted variations of voltages and current at the nodes
 Reliable circuit: Immune to noise
 Noise sources in digital circuits

v(t) V DD
i(t)

Inductive coupling Capacitive coupling Power and ground

noise

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Fan-in & Fan-out

M
N

Fan-out N Fan-in M

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Performance Metric: Delay Definitions

tp = ½ (tpHL + tpLH)
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Power Dissipation

Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:
Ppeak = Vsupplyipeak

Average power:
1 t T Vsupply t T
Pave   p(t )dt   isupply t dt
T t T t

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Energy and Energy-Delay

Power-Delay Product (PDP) =

E = Energy per operation = Pav  tp

Energy-Delay Product (EDP) =

Quality metric of gate = E  tp

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