Lecture 2 – Manufacturing Process & Layout

Digital Integrated Circuits

Yoonmyung Lee
[email protected]
College of Information & Communication Engineering
Kang Ch. 2.1-2.5
Sungkyunkwan University Rabaey Ch. 2.1-2.3
Materials adapted from Textbook,
KW Kwon, SY Kim (SKKU)
Blaauw, Zhang (U of Michigan)
Integrated Circuits & Systems Design Lab.
Modern Digital Systems

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Integrated MOSFET
 NMOS (or PMOS)
 Four terminals: Gate, Source, Drain, Body
 Gate-oxide-body stack looks like a capacitor
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal – oxide – semiconductor (MOS) capacitor

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Fabrication
 Chips are built in huge factories called fabs
(Fab = Semiconductor fabrication plant)
 Contain clean rooms as large as football fields

Source:Samsung
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Silicon Ingot
 Grown from Silicon Seed Crystal
 Heating polycrystalline above its melting point
and slowly cooling it from one end of its container
 Crystal of the same orientation as the seed material
is grown on the seed and is progressively formed
along the length of the container

Silicon Ingot

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CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or etched
 Easiest to understand by viewing both top and cross-section
of wafer in a simplified manufacturing process

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CMOS Inverter Fabrication
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors

SiO2

n+ diffusion

n+ n+ p+ p+ p+ diffusion

n well polysilicon
p substrate
metal1

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Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
 Cover wafer with protective layer of SiO2 (oxide)
 Remove layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer
 Strip off SiO2

p substrate

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Oxidation
 Grow SiO2 on top of Si wafer
 900 – 1200 ⁰C with H2O or O2 in oxidation furnace

p substrate

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Photoresist
 Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Originally insoluble, but softens where exposed to light (Positive)
 Originally soluble, but hardens where exposed to light (Negative)

p substrate

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Photolithography
 Expose photoresist
through photomask
 Hardens where
exposed to light
 Dissolve off
unexposed photoresist
 Example is Negative

p substrate

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Etch
 Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed

p substrate

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Strip Photoresist
 Strip off remaining photoresist
 Use mixture of acids called Piranha etch
 Necessary so resist doesn’t melt in next step

p substrate

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N-well
 n-well is formed with doping
 diffusion or ion implantation

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N-well
 Diffusion
 Place wafer in furnace with arsenic gas
 Heat until As atoms diffuse into exposed Si
 Ion Implantation
 Blast wafer with beam of ions
 Ions blocked by SiO2, only enter exposed Si where mask was

Source: Daniel Schwen

Doping by Diffusion Doping by Ion Implantation

Digital Integrated Circuits
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Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

p substrate

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Polysilicon
 Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers) (@65nm 1.5nm or 15 Å )
 Chemical Vapor Deposition (CVD) of silicon layer
 Place wafer in furnace with Silane gas (SiH4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

n well
p substrate

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Polysilicon Patterning
 Use same lithography process to pattern polysilicon

n well
p substrate

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N-diffusion
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms NMOS source, drain, and n-well contact

n well
p substrate

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N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates because it doesn’t
melt during later processing

n+ n+ n+

n well
p substrate

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N-diffusion
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called “diffusion” or “active”

n+ n+ n+

n well
p substrate

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N-diffusion
 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

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P-Diffusion
 Similar set of steps form p+ diffusion regions for
PMOS source and drain and substrate contact

p+ n+ n+ p+ p+ n+

n well
p substrate

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Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed
 Metal deposition

p+ n+ n+ p+ p+ n+
n well
p substrate

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Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

Top Metal

A Metal 3

Via23

Metal 2

Via12

Metal 1

Contact

p+ n+ n+ p+ p+ n+
n well
p substrate

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Advanced Metallization

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Multilevel Interconnects & Metallization

 Actual cross-section of a modern IC (IBM’s Power6 microprocessor).

 Most part: the multiple layers of metal for wiring above the silicon surface.

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Inverter Mask Set
A
A

p+ n+ n+ p+ p+ n+
Y
n well
p substrate

GND nMOS transistor pMOS transistor VDD

substrate tap well tap

 Transistors and wires

are defined by masks

 Six masks required

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Silicon on Insulator (SOI)

Gate oxide
n+ p+

n+ STI p+ p+
nFET pFET

BOX

 Silicon on Insulator (SoI)

 Build the transistor structures on insulating
material rather than a common substrate (bulk)
 Significantly reduces parasitic capacitances
and eliminates substrate noise coupling.
 Also reduces power consumption and increases performance
 The latch-up eliminated by isolating n- and p-well structures completely

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High-K Metal Gate
 “Metal” in Metal-Ox-Si FET?
 Traditional metal gate replaced with polysilicon
 Manufacturing issues: easy deposition, thermal stability
 High-K Metal gate (Intel 45nm and beyond)
Gate Leakage Trend
 HfO2, ZrO2, TiO2
 Higher K (permittivity) = increased capacitance = better gate control
 Thicker gate dielectric = less gate leakage (>25x NMOS, >1000x PMOS)
 Back to metal gate due to depletion in poly gate

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Source: Intel Digital Integrated Circuits
3-Dimensional Devices
 For increased driving current and better gate control
 FinFET (Intel 22n, Samsung/TSMC 14n)

Single gate Double gate

Gate

Gate Oxide

Si

BOX
SOI GAA, SON MIGFET FinFET

Triple gate Surrounding gate

Trigate FET  -gate FET  -gate FET Quadruple Cylindrical Multi-bridge/stacked

gate FET FET nanowire FET

Source: Intel
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Layout
 Chips are specified with set of masks
 Substrate or wells
 Diffusion regions (n+ or p+) = active area
 Polysilicon (gate)
 Metal layer
 Minimum dimensions of masks determine transistor size
(and hence speed, cost, and power)
 Feature size f = distance between source and drain
 Set by minimum width of polysilicon (=length of gate)
 180n, 130n, 90n, 65n, 45n, 32n, 22n,14n,…

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Design Rules
 Design Rules: Set of geometric constraints or rules that physical mask
layout must conform

 Interface between circuit designer and process engineer

 Why do we need design rules?

 Mask misalignment
 Mask resolution
 Process variation
 To maximize yield
 To guarantee correct functionality

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Design Rules
 Illustration of some of the
typical layout design rules

 Only a few of many

possibilities for the layout
of this circuit

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Design Rules
 Design rules for minimum-size transistor
 Design rules for separation between the nMOS and the pMOS

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Design Rules

Contact
and via rules M1 contact to p-diffusion
M1 contact to n-diffusion Contact Mask
M1 contact to poly

Via Masks
Mx contact to My

both materials mask misaligned

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Antenna Rules
 Charging in semiconductor processing
 Many process steps use plasmas, charged particles
 Charge collects on conducting poly, metal surfaces
 Large amounts of charge on poly can create huge E-fields
across the thin gate oxide and lead to breakdown
 Amount of charge collected is proportional to area of conductors
 Important ratio: antenna ratio defined as:
 Q / Agate_ox
 Q is proportional to area of Metal
 If a diode is attached along the line,
antenna rules are relaxed

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Fixing Antenna Rules Violations

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Latch-up

 Most commonly a problem for I/O pads with big drivers,

large currents, possible voltage overshoots

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How to Avoid Latch-up
 Reduce the gain product β1 x β2
 move n-well and n+ source/drain farther apart increases width of the base
of Q2 and reduces gain β2
 Reduce the well and substrate resistances, producing lower voltage drops
 higher substrate doping level reduces Rsub
 reduce Rwell by making low resistance contact to GND
 guard rings around p- and/or n-well, reduces the parasitic resistances

Aim for 1 well or substrate

plug per gate

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Inverter NAND2 NOR2 Layout
 Transistor dimensions specified as Width / Length
 Minimum size is sometimes called 1 unit
 In 0.13 mm process, this is 0.16 mm wide, 0.12 mm long

A
Y Z
A B
Z Y
B

Inverter NAND2 NOR2

VDD VDD VDD
320nm/120nm
Y Y
A Y B B
A A
160nm/120nm

GND GND GND

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Simplified Layout Diagram

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Stick Diagram
 Contains no dimensions
 Represents relative positions of transistors

VDD VDD

Out Out

In A B
GND GND

Inverter NAND2

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