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LB6 Vlsi

The document outlines a lab exercise focused on implementing Boolean functions using CMOS and Pseudo-NMOS logic. It details the design process, required software, and expected outcomes, including truth tables and circuit diagrams for specific functions. The results indicate that while CMOS logic offers low power consumption and high efficiency, Pseudo-NMOS logic simplifies design but incurs higher static power usage and slower transitions.

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ANANTHAKRISHNAN M
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25 views5 pages

LB6 Vlsi

The document outlines a lab exercise focused on implementing Boolean functions using CMOS and Pseudo-NMOS logic. It details the design process, required software, and expected outcomes, including truth tables and circuit diagrams for specific functions. The results indicate that while CMOS logic offers low power consumption and high efficiency, Pseudo-NMOS logic simplifies design but incurs higher static power usage and slower transitions.

Uploaded by

ANANTHAKRISHNAN M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VLSI Design Lab 19ECE383, 26-11-2024

Labsheet 6 :IMPLEMENTATION OF BOOLEAN


FUNCTION USING CMOS LOGIC AND
PSEUDO NMOS LOGIC

Aim :
• Boolean Function Implementation.
• Implement: (a) Using CMOS logic. (b) Using Pseudo-NMOS logic (with proper sizing). (c)
Using symbols (NAND, NOR, Inverter).

Softwares and Libraries Required :


• Cadence
• GPDK 090
• Analog Library

Theory :
The implementation of Boolean functions using CMOS logic involves designing complementary pull-
up and pull-down networks using PMOS and NMOS transistors, respectively. The pull-up network
connects the output to VDD,while the pull-down network connects it to ground, ensuring low power
consumption and high noise immunity. In contrast, Pseudo-NMOS logic simplifies this design by
replacing the pull-up network with a single always-on PMOS transistor and using an NMOS-based
pull-down network to implement the logic function. While Pseudo-NMOS reduces transistor count
and design complexity, it consumes static power due to the always-on PMOS, making it less efficient
compared to CMOS.

Schematic Diagram :
a) F = (A · B + C)

A B C F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

Table 1: Truth table for F = (A · B + C)

PREPARED BY AM.EN.U4EAC22056
VLSI Design Lab 19ECE383, 26-11-2024

Circuit diagram :CMOS Logic

Graph :

Circuit diagram :Pseudo Logic

Graph :

PREPARED BY AM.EN.U4EAC22056
VLSI Design Lab 19ECE383, 26-11-2024

b) F = (A + B · C) article amsmath

A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

Table 2: Truth table for F = (A + B · C)

Circuit diagram :Pseudo Logic

Graph :

Result:
• CMOS Logic: The output F = (A B· + C) transitions sharply and accurately, with low static
power consumption and high noise immunity. It efficiently implements the function with
minimal delay.
• Pseudo-NMOS Logic: The output also follows the correct logic but has slightly slower tran-
sitions and higher static power consumption due to the always-on PMOS transistor in the pull-
up network. It is simpler but less power-efficient compared to CMOS.

PREPARED BY AM.EN.U4EAC22056
VLSI Design Lab 19ECE383, 26-11-2024

• The transient response graph shows the behavior of the Boolean function and the output
correctly follows the logic, The transitions in the output reflect the expected behavior of the
function, with some delay due to the characteristics of Pseudo-NMOS logic, which uses an
always-on PMOS transistor for the pull-up network, causing slight delays in the response.

Signature of Faculty with date:

PREPARED BY AM.EN.U4EAC22056
VLSI Design Lab 19ECE383, 26-11-2024

Figure 1: Rubrics

PREPARED BY AM.EN.U4EAC22056

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