ARM Processors

Introduction
This architecture introduced in 1980 by Acorn Computers. ARM1 was designed by the team led by Sophie
Wilson and Steve Furber in 1985 and served as the foundation for subsequent ARM processors. ARM processor is
stands for Advanced RISC Machines processor. It is a 32-bit processor.

The architecture of this processor id RISC architecture that is contained in the name as R. Because if that this
is the first RISC micro-processor that was released to the commercial use. Mainly these processors used in portable
devices because the low power consumption of this processors. It means ARM processors are basically used in
devices that powered by batteries.

What is the RISC?

When we are considering about the RISC architecture, we can’t forget about the CISC architecture. Because
it helps to understand about the functionality of the RISC processors. A short comparison between the RISC and CISC
architectures, is given below.

RISC CISC
➢ Reduces Instruction Set Computers ➢ Complex Instruction Set Computers

➢ It emphasizes on Software to optimize the ➢ It emphasizes on Hardware to optimize the

Instruction Set. Instruction Set.
➢ It is a Hard-wired unit of programming in RISC
➢ Micro-programming unit in CISC processor.
processor.

➢ RISC has simple decoding of instructions. ➢ CISC has complex decoding of instructions.

➢ Pipelining is simple. ➢ Pipelining is complex.

➢ Uses a smaller number of instructions. ➢ Uses large number of instructions.

➢ Execute the instructions in less time. ➢ Execution of instruction takes long time.
➢ This architecture can be used in high-end ➢ This architecture can be used in low-end
applications. applications.
➢ E.g.: - Telecommunication, Image processing, ➢ E.g.: - Home automations, Security systems and
Video processing and etc. etc.
➢ RISC has fixed format of instructions. ➢ CISC has variable format of instructions.

➢ Programs that written for RISC processors take ➢ Programs that written for CISC processors takes
large memory space. low memory space.
➢ E.g.: - Motorola 68000, System/360, AMD, Intel
➢ E.g.: - ARM, ARC, SPARC … x86 CPUs …
 • Called as ARM.
• 1st version of ARM processors.
• It had 26-bit addressing.
ARMv1 • Didn't have Multipy or Co-processor

• Called as ARM2.
• This is the first commercial chip.
ARMv2 • It had 32-bit result Multiply instructions and Co-processor.

• Called as ARM3.
• On-Chip-Cache. It means Cache memory was on the chip.
ARM v2 a • Added Load & Store architecture and cache management

• Called as ARM6.
• It had 32-bit addressing.
ARMv3 • Supports to the Virtual memory.

ARM family comparison

ARM 7 ARM 9 ARM 10 ARM 11

Pipeline depth 3-Stages 5-Stages 6-Stages 8-Stages
Typical MHz 80 150 260 335
mW/MHz 0.19 mW/MHz 0.5 mW/MHz 0.4 mW/MHz
0.06 mW/MHz
(Power loss) (+ cache) (+ cache) (+ cache)
MIPSb / MHz 0.97 1.1 1.3 1.2
Architecture Von Neuman Harvard Harvard Harvard
Multiplier 8 x 32 8 x 32 16 x 32 16 x 32

Features of ARM processors

➢ It has Load & Store instructions.
➢ It uses fixed-length 32-bit instructions.
➢ 3-address instruction format
o Uses each address fields to specify either a processor register or a memory operand.
ADD A B C
• A, B, C have three different addresses.
• ADD is Opcode, A is destination operand and B, C are source operands.
➢ Has High code density.
➢ From ARM 1 to ARM 7 processors made as 32-bit processors. After that from ARM 8 it was made as 64-bit
processors.
o When we are talking about word length of these processors there is some standard words can be
understood such as,
▪ Word => 32-bit
▪ Half-word => 16-bit
▪ Byte => 8-bit
Explanations for some key features of ARM processors.

Load & Store instructions

The important fact about these instructions is, it accesses the memory and all other instructions use
registers as operands. Let’s consider about the Load and Store instructions separately.

➢ Load instructions
o LDR R0, [R1]
▪ The “R1” is the address of the memory location.
▪ “R0” is the content of the address that in the “R1”.
▪ “LDR” stands for “Load Register”.
▪ These instructions are allowed to access the memory.

➢ Store instructions
o ADD R0, R1, R2
▪ “R1” and “R2” are Source operands.
▪ Can’t access to the memory. It can access only the register.
▪ The simple procedure of instruction that given above is,
R0 = R1 + R2
▪ The instructions will only process values which are in registers and it will always place result
of such processing into a register.

The only operand which applies to memory are that,

o Copy memory values into registers (Load Instructions)

o Copy registers values into memory (Store Instructions)

The main benefit of this method is it can increase the processing speed.
Basic architecture of ARM processor

Considering above architecture, we can recognize some special units.

Multiplier: - Responsible for multiplication and accumulate operations.

Barrel shifter: - It can do shifting and rotating operations. And it also a 32-bit unit. Barrel shifter can execute
various types of operations.

Shift operations

Logical operations

Arithmetic operations

Rotate operations

Bit manipulation

Immediate operand generation

Features of ARM instruction set
Using 32-bit long Load and Store instructions and most of the instructions execute in a single cycle. Also,
every instruction can be conditionally executed. There are three types of instructions in ARM instruction set. Those
are,

Data processing instructions

The ARM instruction set includes a variety of data processing instructions, which are fundamental for
performing arithmetic, logical, compare and register movement on data. These instructions operate on registers and
immediate values, enabling the manipulation of data within the processor. Here's an overview of the main data
processing instructions from the ARM instruction set.

Arithmetic: - Addition (ADD), Subtraction (SUB), Reverse subtract (RSB)

Logical: - Bitwise AND (AND), Bitwise OR (ORR), Bitwise exclusive or (EOR)

Compare: - Compares two operands and updates the processor flags based on the result, without
storing the result. (CMP)

Register movement: - Copies the one operand value to register (MOV), Move NOT (MVN)

data processing instructions operate on operands, which are the inputs to the instructions. These operands
can take various forms, allowing for flexibility in performing arithmetic, logical, and control operations. Here are the
types of operands commonly used in data processing instructions.

Simple register operands

registers are denoted by symbolic names such as R0, R1, ..., R15 (or alternatively, r0, r1, ..., r15).
Registers can be used as both source and destination operands in data processing instructions.

E. g.: - ADD R0, R1, R2 ➔ R0 = R1 + R2

SUB R0, R1, R2 ➔ R0 = R1 - R2

Immediate operands

Replace the second source operand with an immediate operand, which is a literal constant,
preceded by “#”.

E. g.: - ADD R3, R4, #1 ➔ R3 = R4 + 1

SUB R5, R6, #2 ➔ R5 = R6 – 2

Shifted register operands

Shifted register values involve shifting the bits of a register left or right by a specified number of
positions before using them as operands. There are some shifting instructions,

those are Logical Shift Left (LSL), Logical Shift Right (LSR), Arithmetic Shift Left (ASL), Arithmetic Shift
Right (ASR), Rotate Right (ROR), Rotate Right Exclusive (RRX).

E. g.: - AND R1, R2, R3, LSL #2 ➔ Perform a logical AND operation between R2 and

R3, where R3 is shifted left by 2 positions.

 Memory Addresses operands

Memory addresses specify locations in the system's memory where data is stored. Memory
addresses can be used as operands to load or store data from or to memory.

E. g.: - LDR R1, [R2] ➔ Load the data from the memory location pointed to by R2 into register R1

Data transfer instructions

Transfer data from one location to another location and that location can be register. There are three types
of instructions in this. Those are,

o Single register Load & Store instructions

o Multiple register Load & Store instructions
o Single register SWAP instructions

Control flow instructions

It can change the flow of the execution of instructions. There are various types of control flow instructions.
Some of them are given below,

▪ Branch instructions (B)

▪ Branch with link instructions (BL)
▪ Conditional branches (Bcc)
▪ Branch exchange (BX)
▪ Branch and link with exchange (BLX)
▪ Software interrupt (SWI)

Applications of ARM processors

➢ Mobile phones
➢ Portable cameras
➢ Raspberry Pie and etc