Digital Logic Laboratory Manual 1

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EXPERIMENT: 1 LOGIC GATES

AIM: To study and verify the truth table of logic gates

LEARNING OBJECTIVE:
• Identify various ICs and their specification.

COMPONENTS REQUIRED:
• Logic gates (IC) trainer kit.
• Connecting patch chords.
• IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486

THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These logic gates
perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-
OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean function, and truth. It is
seen from the Fig that each gate has one or two binary inputs, A and B, and one binary output,
C. The small circle on the output of the circuit symbols designates the logic complement. The
AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can
be extended to have multiple inputs if the binary operation it represents is commutative and
associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part
of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital
IC gates are classified not only by their logic operation, but also the specific logic-circuit
family to which they belong. Each logic family has its own basic electronic circuit upon which
more complex digital circuits and functions are developed. The following logic families are
the most frequently used.

TTL Transistor-transistor logic

ECL Emitter-coupled logic
MOS Metal-oxide semiconductor
CMOS Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well-established popularity
among logic families. ECL is used only in systems requiring high-speed operation. MOS and
CMOS, are based on field effect transistors. They are widely used in large scale integrated
circuits because of their high component density and relatively low power consumption.
CMOS logic consumes far less power than MOS logic. There are various commercial
integrated circuit chips available. TTL ICs are usually distinguished by numerical designation
as the 5400 and 7400 series.

PROCEDURE:
1. Check the components for their working.
2. Insert the appropriate IC into the IC base.

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3. Make connections as shown in the circuit diagram.
4. Provide the input data via the input switches and observe the output on output LEDs

VIVA QUESTIONS:

1. Why NAND & NOR gates are called universal gates?

2. Realize the EX – OR gates using minimum number of NAND gates.
3. Give the truth table for EX-NOR and realize using NAND gates?
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s?
5. Compare TTL logic family with CMOS family?
6. Which logic family is fastest and which has low power dissipation?

DIGITAL LOGIC BCA DEPARTMENT

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EXPERIMENT: 2 REALIZATION OF A BOOLEAN FUNCTION.

AIM: To simplify the given expression and to realize it using Basic gates and Universal
gates

LEARNING OBJECTIVE:
To simplify the Boolean expression and to build the logic circuit.
Given a Truth table to derive the Boolean expressions and build the logic circuit to
realize it.

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, Patch Cords & IC Trainer Kit.

THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms). A
Boolean function can be represented by a Karnaugh map in which each cell corresponds to a
minterm. The cells are arranged in such a way that any two immediately adjacent cells
correspond to two minterms of distance 1. There is more than one way to construct a map
with this property. Karnaugh Maps

For a function of two variables, say, f(x, y),

For a function of three variables, say, f(x, y, z)

For a function of four variables: f(w, x, y, z)

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Realization of Boolean expression:

__ _ _ _ _ _ _ ___ __ _

1) Y= ABCD+ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
AB

1
1
1 1 1 1

_ _

After simplifying using K-Map method we get Y =A B + C D

Realization using Basic gates

Realization using NAND gates

Realization using NOR gates

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TRUTH TABLE
Inputs Output
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

2) For the given Truth Table, realize a logical circuit using basic gates and NAND gates

Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0

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0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

PROCEDURE:
Check the components for their working.
Insert the appropriate IC into the IC base.
Make connections as shown in the circuit diagram.
Provide the input data via the input switches and observe the output on output LEDs Verify
the Truth Table

RESULT: Simplified and verified the Boolean function using basic gates and universal gates

VIVA QUESTIONS:
1) What are the different methods to obtain minimal expression?
2) What is a Min term and Max term
3) State the difference between SOP and POS.
4) What is meant by canonical representation?
5) What is K-map? Why is it used?
6) What are universal gates?

DIGITAL LOGIC BCA DEPARTMENT

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EXPERIMENT: 3 ADDERS AND SUBTRACTORS

AIM: To realize
i) Half Adder and Full Adder
ii) Half Subtractor and Full Subtractor by using Basic gates and NAND gates

LEARNING OBJECTIVE:
To realize the adder and subtractor circuits using basic gates and universal gates
To realize full adder using two half adders
To realize a full subtractor using two half subtractors

COMPONENTS REQUIRED:
IC 7400, IC 7408, IC 7486, IC 7432, Patch Cords & IC Trainer Kit.

THEORY:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit,
S, and the other is the carry bit, C. The Boolean functions describing the half-adder are:
⊕
S =A B C=AB

Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:
S = (x ⊕ y) ⊕ Cin C = xy + Cin (x ⊕ y)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B )

produces a difference bit D and a borrow out bit B-out. This operation is called half
subtraction and the circuit to realize it is called a half subtractor. The Boolean functions
describing the half- Subtractor are:
⊕
S =A B C = A’ B

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtracter are:
⊕ ⊕
D = (x y) Cin Br= A’B + A’(Cin) + B(Cin)

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I. TO REALIZE HALF ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS
⊕
S=A B C=A B
A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

i) Basic Gates ii) NAND Gates

II. FULL ADDER

TRUTH TABLE BOOLEAN EXPRESSIONS:
INPUTS OUTPUTS
⊕ ⊕
S= A B C
A B Cin S C

0 0 0 0 0 C=A B + B Cin + A Cin

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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i)BASIC GATES

ii) NAND GATES

III. HALF SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS ⊕
D=A B
A B D Br _

Br = AB
0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

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i)BASIC GATES ii) NAND Gates

IV. FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS D= A ⊕ B ⊕ C
_ _

A B Cin D Br Br= A B + B Cin + A Cin

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

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i) BASIC GATES

ii) To Realize the Full subtractor using NAND Gates only

PROCEDURE:
• Check the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT: The truth table of the above circuits is verified.

VIVA QUESTIONS:

1) What is a half adder?

2) What is a full adder?
3) What are the applications of adders?
4) What is a half subtractor?
5) What is a full subtractor?
6) What are the applications of subtractors?
7) Obtain the minimal expression for above circuits.
8) Realize a full adder using two half adders
9) Realize a full subtractors using two half subtractors

DIGITAL LOGIC BCA DEPARTMENT

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EXPERIMENT: 4 PARALLEL ADDER AND SUBTRACTOR

AIM: To design and set up the following circuit using IC 7483.

i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.

LEARNING OBJECTIVE:
To learn about IC 7483 and its internal structure.
To realize a subtractor using adder IC 7483

COMPONENTS REQUIRED:
IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

THEORY:
The Full adder can add single-digit binary numbers and carries. The largest sum that can be
obtained using a full adder is 112. Parallel adders can add multiple-digit numbers. If full
adders are placed in parallel, we can add two- or four-digit numbers or any other size desired.
Figure below uses STANDARD SYMBOLS to show a parallel adder capable of adding two,
two-digit binary numbers The addend would be on A inputs, and the augend on the B inputs.
For this explanation we will assume there is no input to C0 (carry from a previous circuit)

To add 102 (addend) and 012 (augend), the addend inputs will be 1 on A2 and 0 on A1. The
augend inputs will be 0 on B2 and 1 on B1. Working from right to left, as we do in normal
addition, let’s calculate the outputs of each full adder. With A1 at 0 and B1 at 1, the output
of adder1 will be a sum (S1) of 1 with no carry (C1). Since A2 is 1 and B2 is 0, we have a sum
(S2) of 1 with no carry (C2) from adder1. To determine the sum, read the outputs (C2, S2, and
S1) from left to right. In this case, C2 = 0, S2 = 1, and S1 = 1. The sum, then, of 102 and 012
is 0112. To add four bits we require four full adders arranged in parallel. IC 7483 is a 4- bit
parallel adder whose pin diagram is shown.

MSB LSB
Cin
INPUTS A3 A2 A1 A0
B3 B2 B1 B0
OUTPUT Cout S3 S2 S1 S0

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IC 7483 pin diagram

i) 4-Bit Binary Adder

An Example: 7+2=11 (1001)

• 7 is realized at A3 A2 A1 A0 = 0111
• 2 is realized at B3 B2 B1 B0 = 0010
Sum = 1001

ADDER CIRCUIT:

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Apply augend and addend bits on A and B and cin=0.
• Verify the results and observe the outputs.

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ii) 4-BIT BINARY SUBTRACTOR.

Subtraction is carried out by adding 2’s complement of the subtrahend.
Example: 8 – 3 = 5 (0101)

• 8 is realized at A3 A2 A1 A0 = 1000
• 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
• Output of X-OR gate is 1’s complement of 3 = 1100
• 2’s Complement can be obtained by adding Cin = 1

Therefore
Cin = 1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1 Cout
= 1 (Ignored)

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Apply Minuend and subtrahend bits on A and B and cin=1.
• Verify the results and observe the outputs.

RESULTS: Verified the working of IC 7483 as adder and subtractor.

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EXPERIMENT: 5 BCD TO EXCESS- 3 CODE CONVERTERS.

AIM: To design and realize the following using IC 7483.
I) BCD to Excess- 3 Code
II) Excess-3 to BCD Code.

LEARNING OBJECTIVE:
To learn to realize BCD to Excess-3 code using adder IC 7483
To learn to realize Excess-3 to BCD Code using adder IC 7483

COMPONENTS REQUIRED:
IC 7483, IC 7486, Patch Cords & IC Trainer Kit.

THEORY:
Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCDcode
to the 4-bit adder as the first operand and then feed constant 3 as the second operand. The
output is the corresponding excess-3 code.

To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first operand
and then feed 2's complement of 3 as the second operand. The output is the BCD code.

Circuit Diagram

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TRUTH TABLE:

i) BCD - EXCESS-3 CODE ii) EXCESS-3 TO BCD CODE

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Apply BCD code as first operand(A) and binary 3 as second operand(B) and cin=0 for

Realizing BCD-to-Excess-3-code:
• Apply Excess-3-code code as first operand(A) and binary 3 as second operand(B) and
Cin=1 for realizing Excess-3-code to BCD.
• Verify the Truth Table and observe the outputs.
RESULT: Realized BCD code to Excess-3 code conversion and vice versa using 7483 IC

VIVA QUESTIONS:
1) What is the internal structure of 7483 IC?
2) What do you mean by code conversion?
3) What are the applications of code conversion?
4) How do you realize a subtractor using full adder?
5) What is a ripple Adder? What are its disadvantages?
DIGITAL LOGIC BCA DEPARTMENT
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EXPERIMENT: 6 BINARY TO GRAY CODE CONVERTER

AIM: To realize Binary to Gray code converter and vice versa.

LEARNING OBJECTIVE:
To learn the importance of non-weighted code
To learn to generate gray code
COMPONENTS REQUIRED:

IC 7400, IC 7486, and IC 7408, Patch Cords & IC Trainer Kit

I) BINARY TO GRAY CONVERSION Binary Gray

B3 B2 B1 B0 G3 G2 G1 G0
0 0 1 1
0 0 0 0 0 0 0 0
0 0 1 1
0 0 0 1 0 0 0 1
0 0 1 1
0 0 1 0 0 0 1 1
0 0 1 1
0 0 1 1 0 0 1 0
G3 = B3 0 1 0 1 0 1 0 0 0 1 1 0
0 1 0 1 0 1 0 1 0 1 1 1
0 1 0 1 0 1 1 0 0 1 0 1
0 1 0 1 0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0
0 1 1 0
1 0 0 1 1 1 0 1
0 1 1 0
1 0 0 1 1 0 1 0 1 1 1 1

1 0 0 1 G1=B1 ⊕ B2 1 0 1 1 1 1 1 0

⊕ 1 1 0 0 1 0 1 0
G2= B3 B2
1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

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0 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1 G0=B1 ⊕ B0

BOOLEAN EXPRESSIONS:
G3=B3
G2=B3 ⊕ B2
G1=B1 ⊕ B2; G0=B1 ⊕ B0

BINARY TO GRAY CODE USING EX-OR GATES

REALIZATION USING NAND GATES:

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II) GRAY TO BINARY CONVERSION

0 0 1 1

0 0 1 1

0 0 1 1
B3 = G3 Gray Binary
0 0 1 1

G3 G2 G1 G0 B3 B2 B1 B0
B2=G3⊕G2
0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 1 0 0 0 1
0 1 0 1
0 0 1 1 0 0 1 0
0 1 0 1
0 0 1 0 0 0 1 1
0 1 0 1
0 1 1 0 0 1 0 0

B1=G3⊕G2⊕G1 0 1 1 1 0 1 0 1
0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 1 0 1 0 0 0 1 1 1

1 0 1 0 1 1 0 0 1 0 0 0

1 0 1 0 1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0
B0=G3 ⊕ G2⊕ G1⊕ G0
1 1 1 0 1 0 1 1
0 1 0 1
1 0 1 0 1 1 0 0
1 0 1 0

0 1 0 1 1 0 1 1 1 1 0 1

1 0 1 0 1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

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BOOLEAN EXPRESSIONS:
B3=G3
B2=G3 ⊕ G2
B1=G3 ⊕ G2⊕ G1
B0=G3 ⊕ G2⊕ G1⊕ G0

GRAY TO BINARY CODE CONVERSION USING EX-OR GATES

REALIZATION USING NAND GATES:

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PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT: Binary to gray code conversion and vice versa is realized using EX-OR gates and
NAND gates.

VIVA QUESTIONS:

1) What are code converters?

2) What is the necessity of code conversions?
3) What is gray code?
4) Realize the Boolean expressions for a) Binary to gray code conversion
b) Gray to binary code conversion

DIGITAL LOGIC BCA DEPARTMENT

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EXPERIMENT: 7 MULTIPLEXER AND DEMULTIPLEXER
AIM: To design and set up the following circuit
1) To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.
2) To design and set up a 1:4 Demultiplexer(DE-MUX) using only NAND gates.
3) To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX).
4) To set up a Half/Full Adder and Half/Full Subtractor using IC 74153.

LEARNING OBJECTIVE:
To learn about various applications of multiplexer and de-multiplexer
To learn and understand the working of IC 74153 and IC 74139
To learn to realize any function using Multiplexer

THEORY:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control
of selection signals. Multiplexer means many to one. A multiplexer is a circuit with many
inputs but only one output. By using control signals (select lines) we can select any input to
the output. Multiplexer is also called as data selector because the output bit depends on the
input data bit that is selected. The general multiplexer circuit has 2n input signals, n
control/select signals and 1 output signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small number
of information units (usually one unit) over a larger number of channels under the control of
selection signals. The general de-multiplexer circuit has 1 input signal, n control/select signals
and 2n output signals. De-multiplexer circuit can also be realized using a decoder circuit with
enable.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7404, IC 74153, IC 74139, Patch Cords & IC Trainer Kit.

i) 4:1 MULTIPLEXER

4:1
Inputs MUX
Y

E’ Select
inputs

Output Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

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REALIZATION USING NAND GATES TRUTH TABLE

Select Enable Out

Inputs
Inputs Input puts

S1 S0 E I0 I1 I2 I3 Y

X X 1 X X X X 0

0 0 0 0 X X X 0

0 0 0 1 X X X 1

0 1 0 X 0 X X 0

0 1 0 X 1 X X 1

1 0 0 X X 0 X 0

1 0 0 X X 1 X 1

1 1 0 X X X 0 0

1 1 0 X X X 1 1
VERIFY IC 74153 MUX (DUAL 4:1
MULTIPLEXER)

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ii) DE-MUX USING NAND GATES
Enable Data Select
Inputs Input Inputs Outputs

E D S1 S0 Y3 Y2 Y1 Y0

1 0 X X X X X X
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 1 0 0
0 1 1 1 1 0 0 0

VERIFICATION OF IC 74139 (DEMUX)

TRUTH TABLE

Inputs Outputs

Ea S1 S0 Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

HALF ADDER USING MUX:

DESIGN: TRUTH TABLE
SUM CARRY
I0 I1 I0 I1 Inputs Outputs
0 1 0 1
A B S C
2 3 2 3
0 0 0 0
A A’ 0 A
0 1 1 0
1 0 1 0
1 1 0 1
CIRCUIT:
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FULL ADDER USING MUX:

DESIGN:
SUM CARRY

I0 I1 I3 I3 I0 I1 I3 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A A 1

TRUTH TABLE
Inputs Outputs
A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

FULL ADDER CIRCUIT

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HALF SUBTRACTOR USING MUX:

DESIGN:

DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’

CIRCUIT: TRUTH TABLE

Inputs Outputs

A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

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FULL SUBTRACTOR USING MUX:

DESIGN:
DIFFERENCE BORROW

I0 I1 I2 I3 I0 I1 I2 I3
0 1 2 3 0 1 2 3
4 5 6 7 4 5 6 7
A A’ A’ A 0 A’ A’ 1

TRUTH TABLE

Inputs Outputs
A B C D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT: Adder and subtractor circuits are realized using multiplexer IC 74153.

VIVA QUESTIONS:
1) What is a multiplexer?
2) What is a de-multiplexer?
3) What are the applications of multiplexer and de-multiplexer?
4) Derive the Boolean expression for multiplexer and de-multiplexer.
5) How do you realize a given function using multiplexer
6) What is the difference between multiplexer & demultiplexer?

DIGITAL LOGIC BCA DEPARTMENT

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EXPERIMENT: 8 COMPARATORS

AIM: To realize One & Two Bit Comparator and study of 7485 magnitude comparator.

LEARNING OBJECTIVE:
To learn about various applications of comparator
To learn and understand the working of IC 7485 magnitude comparator
To learn to realize 8-bit comparator using 4-bit comparator

THEORY:
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high
speed 4-bit Magnitude comparator , which compares two 4-bit words . The A = B
Input must be held high for proper compare operation.

COMPONENTS REQUIRED:
IC 7400, IC 7410, IC 7420, IC 7432, IC 7486, IC 7402, IC 7408, IC 7404, IC 7485, Patch
Cords & IC Trainer Kit.

1) 1- BIT COMPARATOR TRUTH TABLE

_

A>B = AB
_

A<B = AB INPUTS OUTPUTS

__

A=B = A B +AB A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

2) 2- BIT COMPARATOR
_ _ _ _

+ +
(A>B)= A1 B1 A0B1B0 B0A1A0 (A=B)
= (A0 ⊕ B0) (A1⊕ B1)
(A<B) = B1

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2-bit comparator circuit diagram

TRUTH TABLE

INPUTS OUTPUTS
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

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3) TO COMPARE THE GIVEN DATA USING 7485 CHIP.

A B Result
A3 A2 A1 A0 B3 B2 B1 B0
0 0 0 1 0 0 0 0 A>B
0 0 0 1 0 0 0 1 A=B
0 0 0 0 0 0 0 1 A<B

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

RESULT: One bit, two bit and four bit comparators are verified using basic gates and magnitude
comparator IC7485

VIVA QUESTIONS:

1) What is a comparator?
2) What are the applications of comparator?
3) Derive the Boolean expressions of one bit comparator and two bit comparators. 4) How
do you realize a higher magnitude comparator using lower bit comparator 5) Design a 2
bit comparator using a single Logic gates?
6) Design an 8 bit comparator using a two numbers of IC 7485?

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EXPERIMENT: 9 DECODERS

AIM: To realize a decoder circuit using basic gates and to verify IC 74LS139

LEARNING OBJECTIVE:
To learn about working principle of decoder
To learn and understand the working of IC 74LS139
To realize using basic gates as well as universal gates

COMPONENTS REQUIRED:
IC74LS139, IC 7400, IC 7408, IC 7432, IC 7404, IC 7410, Patch chords, & IC Trainer Kit

THEORY:

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. Decoder is also called a min-term generator/maxterm
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic). The IC 74139 accepts two
binary inputs and when enable provides 4 individual active low outputs. The device has 2 enable
inputs (Two active low).

CIRCUIT DIAGRAM:

2:4 DECODER (MIN TERM GENERATOR):

TRUTH TABLE:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

BOOLAEN EXPRESSIONS:
Y0 = AB
Y1= AB

Y2 = AB
Y3 = AB

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CIRCUIT DIAGRAM:

2:4 DECODER (MAX TERM GENERATOR):

TRUTH TABLE:

INPUT OUTPUT
A B Y0 Y1 Y2 Y3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

CIRCUIT DIAGRAM:

STUDY OF IC 74LS139:

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PROCEDURE:
1. Make the connections as per the circuit diagram.
2. Change the values of G1, G2A, G2B, A, B, and C, using switches.
3. Observe status of Y0, to Y7 on LED’s.
4. Verify the truth table.

RESULT: Verified the Operation of 3 to 8 Decoder

VIVA QUESTIONS:
1. What are the applications of decoder?
2. What is the difference between decoder & encoder?
3. For n- 2n decoder how many i/p lines & how many o/p lines?
4. What are the different codes & their applications?
5. What are code converters?
6. Using 3:8 decoder and associated logic, implement a full adder?
7. Implement a full subtractor using IC 74138?
8. What is the difference between decoder and de-mux?

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EXPERIMENT: 10 BCD TO 7-SEGMENT DECODER/DRIVER

AIM: To set up and test a 7-segment static display system to display numbers 0 to 9.

LEARNING OBJECTIVE:
To learn about various applications of decoder
To learn and understand the working of IC 7447
To learn about types of seven-segment display

COMPONENTS REQUIRED:
IC7447, 7-Segment display (common anode), Patch chords, resistor (1KΩ) & IC Trainer Kit

THEORY:

The Light Emitting Diode (LED) finds its place in many applications in these modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any number
out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven
Segment LED arrangement.

The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contains the
arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead
(Anode or Cathode). The purpose of arranging it in that passion is that we can make any number
out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven
Segment LED arrangement.

LED’s are basically of two types-

Common Cathode (CC) -All the 8 anode legs uses only one cathode, which is common. Common
Anode (CA)-The common leg for all the cathode is of Anode type.

A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The
IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment
code.

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CIRCUIT DIAGRAM:

TRUTH TABLE:

Decimal
BCD Inputs Output Logic Levels from IC 7447 to 7-segments number
display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 1 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0 2
0 0 1 1 0 0 0 0 1 1 0 3
0 1 0 0 1 0 0 1 1 0 0 4
0 1 0 1 0 1 0 0 1 0 0 5
0 1 1 0 1 1 0 0 0 0 0 6
0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 1 1 0 0 9

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

VIVA QUESTIONS:
1. What are the different types of LEDs?
2. Draw the internal circuit diagram of an LED.
3. What are the applications of LEDs?

EXPERIMENT: 11 ENCODERS

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AIM:
1. To set up a circuit of Decimal-to-BCD Encoder using IC 74147.
2. To design and set up a circuit of Hexadecimal-to-Binary Encoder using IC
3. 74148 Encoders and IC 74157 Multiplexer

LEARNING OBJECTIVE:
To learn about various applications of Encoders
To learn and understand the working of IC 74147 , IC 74148 & IC 74157
To learn to do code conversion using encoders

COMPONENTS REQUIRED:
IC 74147, IC 74148, IC 74157, Patch chords & IC Trainer Kit

THEORY:
An encoder performs a function that is the opposite of decoder. It receives one or more signals in
an encoded format and output a code that can be processed by another logic circuit. One of the
advantages of encoding data, or more often data addresses in computers, is that it reduces the
number of required bits to represent data or addresses. For example, if a memory has 16 different
locations, in order to access these 16 different locations, 16 lines (bits) are required if the
addressing signals are in 1 out of n format. However, if we code the 16 different addresses into a
binary format, then only 4 lines (bits) are required. Such a reduction improves the speed of
information processing in digital systems.

CIRCUIT DIAGRAM:

1) DECIMAL-TO BCD ENCODER USING IC 74147.

TRUTH TABLE
INPUTS OUTPUTS
I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A1 A0
1 1 1 1 1 1 1 1 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1

0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1

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2) OCTAL TO BINARY ENCODER USING IC 74148. TRUTH TABLE

Inputs Outputs

E1 I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS E0

1 X X X X X X X X 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1 1 0

0 X X X X X X X 0 0 0 0 0 1

0 X X X X X X 0 1 0 0 1 0 1

0 X X X X X 0 1 1 0 1 0 0 1

0 X X X X 0 1 1 1 0 1 1 0 1

0 X X X 0 1 1 1 1 1 0 0 0 1

0 X X 0 1 1 1 1 1 1 0 1 0 1
3) HEXADECIMAL TO BINARY
0 X 0 1 1 1 1 1 1 1 1 0 0 1
ENCODER
0 0 1 1 1 1 1 1 1 1 1 1 0 1

TRUTH TABLE

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INPUTS OUTPUTS
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 Y3 Y2 Y1 Y0
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 0 0
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 0 1
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

VIVA QUESTIONS:
1. What is a priority encoder?
2. What is the role of an encoder in communication?
3. What is the advantage of using an encoder?
4. What are the uses of validating outputs?

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EXPERIMENT: 12 FLIP FLOPS

AIM: Truth Table verification of
1) RS Flip Flop
2) T type Flip Flop.
3) D type Flip Flop.
4) JK Flip Flop.
5) JK Master Slave Flip Flop.

LEARNING OBJECTIVE:
To learn about various Flip-Flops
To learn and understand the working of Master slave FF
To learn about applications of FFs
Conversion of one type of Flip flop to another

COMPONENTS REQUIRED:
IC 7408, IC 7404, IC 7402, IC 7400, Patch Cords & IC Trainer Kit.

THEORY:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation. The
latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic
circuits. Usually there are two outputs, Q and its complementary value. Some of the most
widely used latches are listed below.

SR LATCH:
An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using
cross-coupled NAND gates as shown. The truth tables of the circuits are shown below.
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A clocked S-R flip-flop has an additional clock input so that the S and R inputs are active
only when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot
change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
“enabled” S-R flip-flop.
A D latch combines the S and R inputs of an S-R latch into one input by adding an inverter. When
the clock is high, the output follows the D input, and when the clock goes low, the state is latched.
A S-R flip-flop can be converted to T-flip flop by connecting S input to Qb and R to Q.

1) S-R LATCH:

(A) LOGIC DIAGRAM (B) SYMBOL

TRUTH TABLE
S R Q+ Qb+
0 0 Q Qb
0 1 0 1
1 0 1 0
1 1 0* 0*

SR LATCH: TRUTH TABLE

S R Q+ Qb+
0 0 1* 1*
0 1 1 0
1 0 0 1
1 1 Q Qb
2) SR FLIP FLOP:

CIRCUIT DIAGRAM:

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(A) LOGIC DIAGRAM (B) SYMBOL TRUTH TABLE

S R Q+ Qb+

0 0 Q Qb
0 1 0 1
1 0 1 0
1 1 0* 0*

3) CONVERSION OF SR-FLIP FLOP TO T-FLIP FLOP (Toggle)

LOGIC DIAGRAM SYMBOL

T FLIP FLOP USING IC 7476 TRUTH TABLE

T Qn + 1

0 Qn

1 Qn

4) CONVERSION OF SR-FLIP FLOP TO D-FLIP FLOP :

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LOGIC DIAGRAM SYMBOL

D FLIP FLOP USING IC 7476 TRUTH TABLE

CLOCK D Q+ Q+
0 X Q Q
1 0 0 1
1 1 1 0

5. JK MASTER SLAVE FLIP FLOP

LOGIC DIAGRAM

TRUTH TABLE

PRE = CLR = 1

Clock J K Q+ Q’+ Comment

No Change
1 0 0 Q Q’

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1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 Race Around

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

VIVA QUESTIONS:
1. What is the difference between Flip-Flop & latch?
2. Give examples for synchronous & asynchronous inputs?
3. What are the applications of different Flip-Flops?
4. What is the advantage of Edge triggering over level triggering?
5. What is the relation between propagation delay & clock frequency of flip-flop?
6. What is race around in flip-flop & how to over come it?
7. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
8. List the functions of asynchronous inputs?

EXPERIMENT: 13 SHIFT REGISTERS

AIM: To realize and study of Shift Register. 1)

SISO (Serial in Serial out)
2) SIPO (Serial in Parallel out)
3) PIPO (Parallel in Parallel out)
4) PISO (Parallel in Serial out)

COMPONENTS REQUIRED: IC 7495, Patch Cords & IC Trainer Kit.

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

1) SERIAL IN SERIAL OUT (SISO) (Right Shift)

Serial
Shift
i/p QA QB QC QD
Pulses
data
- - X X X X
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0 t1 0 X X X
1 t2 1 0 X X
0 t3 0 1 0 X
1 t4 1 0 1 0
X t5 X 1 0 1
X t6 X X 1 0
X t7 X X X 1
X t8 X X X X

2) SERIAL IN PARALLEL OUT (SIPO)

Serial Shift
QA QB QC QD
i/p data Pulses
- - X X X X
0 t1 0 X X X
1 t2 1 0 X X
0 t3 0 1 0 X
1 t4 1 0 1 0

3) PARALLEL IN PARALLEL OUT (PIPO)

Clock
Input Shift
QA QB QC QD
Terminal Pulses

- - X X X X
CLK2 t1 1 0 1 0
4) PARALLEL IN SERIAL OUT (PISO)

Clock
Shift
Input QA QB QC QD
Pulses
Terminal
- - X X X X

CLK2 t1 1 0 1 0

CLK2 t2 X 1 0 1

0 t3 X X 1 0

1 t4 X X X 1

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X t5 X X X X

VCC QA QB QC QD CLK1 CLK2

14 13 12 11 10 9 8

IC 7495

1 2 3 4 5 6 7

SERIAL A B C D MODE GND

INPUT CONTROL
( Right PARALLEL
Shift)
INPUTS

RESULT: The various operations of a shift register is verified

EXPERIMENT: 14 RING COUNTER AND JOHNSON COUNTER

AIM: To realize and study Ring Counter and Johnson counter.

LEARNING OBJECTIVE:
To learn about Ring Counter and its application
To learn about Johnson Counter and its application

COMPONENTS REQUIRED:
IC 7495, IC 7404, Patch Cords & IC Trainer Kit.

THEORY:
Ring counter is a basic register with direct feedback such that the contents of the register
simply circulate around the register when the clock is running. Here the last output that is QD in
a shift register is connected back to the serial input.
A basic ring counter can be slightly modified to produce another type of shift register counter
called Johnson counter. Here complement of last output is connected back to the not gate input
and not gate output is connected back to serial input. A four bit Johnson counter gives 8 state
output.

PROCEDURE:
• Check all the components for their working.
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• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Apply clock to pin number 9 and observe the output

CIRCUIT DIAGRAM:

1) RING COUNTER TRUTH TABLE

Clock
QA QB QC QD
pulses
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1
8 1 0 0 0

2) JOHNSON COUNTER TRUTH TABLE

Clock
QA QB QC QD
pulses
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0

RESULT: The truth table & working of Ring and Johnson counters is verified

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EXPERIMENT: 15 STUDY OF ASYNCHRONOUS COUNTER

AIM: To design and test 3-bit binary asynchronous counter using flip-flop IC 7476 for the given
sequence.

LEARNING OBJECTIVE:
To learn about Asynchronous Counter and its application
To learn the design of asynchronous up counter and down counter

COMPONENTS REQUIRED:
IC 7476, Patch Cords & IC Trainer Kit

THEORY:
A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all the
flip-flops do not change state simultaneously spike occur at the output. To avoid this, strobe pulse
is required. Because of the propagation delay the operating speed of asynchronous counter is low.
Asynchronous counter are easy and simple to construct.

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.
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MOD-8 UP COUNTER

CIRCUIT DIAGRAM:

TRUTH TABLE

CLK QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

MOD_6 UP COUNTER CIRCUIT

DIAGRAM:

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TRUTH TABLE
CLK QC QB QA

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 0 0 0

MOD-8 DOWN COUNTER

CIRCUIT DIAGRAM:

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TRUTH TABLE

CLK QC QB QA

0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1

MOD-6 DOWN COUNTER

CIRCUIT DIAGRAM:

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TRUTH TABLE
CLK QC QB QA

0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 1 1 1

RESULT: The working of Mod-N Asynchronous counters is verified

VIVA QUESTIONS:

What is an asynchronous counter?

How is it different from a synchronous counter?
Realize asynchronous counter using T flip-flop

EXPERIMENT: 16 SYNCHRONOUS COUNTERS

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AIM: To design and test 3-bit binary synchronous counter using flip-flop IC 7476 for the given
sequence.

LEARNING OBJECTIVE:
To learn about synchronous Counter and its application
To learn the design of synchronous counter counter

COMPONENTS REQUIRED:
IC 7476, Patch Cords & IC Trainer Kit

THEORY:
A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all the
flip-flops do not change states simultaneously in asynchronous counter, spike occur at the output.
To avoid this, strobe pulse is required. Because of the propagation delay the operating speed of
asynchronous counter is low. This problem can be solved by triggering all the flip-flops in
synchronous with the clock signal and such counters are called synchronous counters.

PROCEDURE:
• Check all the components for their working.
• Insert the appropriate IC into the IC base.
• Make connections as shown in the circuit diagram.
• Verify the Truth Table and observe the outputs.

MOD 5 COUNTER:
TRUTH TABLE: Present count next count

QC QB QA QC QB QA QC QB QA
0 0 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 0
0 1 0 0 1 0 0 1 1
0 1 1 0 1 1 1 0 0
1 0 0 1 0 0 0 0 0
0 0 0

JK FF excitation table:
Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

DESIGN:

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1 X X 1 X 1 X X
0 X X X X X X X

JA = QC KA = 1

0 1 X X X X 1 0
0 X X X X X X X

JB = QA KB = QA

X X X X
0 0 1 0
1 X X X
X X X X
JC = QBQA KC = 1

MOD 8 COUNTER:
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TRUTH TABLE: Present count next count

QC QB QA QC QB QA QC QB QA
0 0 0 0 0 0 0 0 1
0 0 1 0 0 1 0 1 0
0 1 0 0 1 0 0 1 1
0 1 1 0 1 1 1 0 0
1 0 0 1 0 0 1 0 1
1 0 1 1 0 1 1 1 0
1 1 0 1 1 0 1 1 1
1 1 1 1 1 1 0 0 0
0 0 0

JK FF excitation table:

Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

DESIGN:
X 1 1 X
1 X X 1 X 1 1 X
1 X X 1
KA = 1

JA = 1

X X 1 0
X X 1 0
0 1 X X
X 1 X X KB = QA

JB = QA
X X X X
0 0 1 0
0 0 1 0
JC = QBQA KC = QBQA
X X X X

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RESULT: The working of synchronous counters is verified.

VIVA QUESTIONS:

What are synchronous counters?

What are the advantages of synchronous counters?
What is an excitation table?
Write the excitation table for D, T FF
Design mod-5 synchronous counter using T FF

DIGITAL LOGIC BCA DEPARTMENT