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VLSI Design Flow (Verification)

This document discusses the critical role of verification and testing in the VLSI design flow, highlighting various methodologies employed to ensure chip functionality and quality. It covers techniques such as simulation, model checking, and physical design verification, as well as the importance of testing for manufacturing defects and yield. The integration of Design for Testability (DFT) principles is emphasized as a means to enhance testability and facilitate efficient fault diagnosis.

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23 views7 pages

VLSI Design Flow (Verification)

This document discusses the critical role of verification and testing in the VLSI design flow, highlighting various methodologies employed to ensure chip functionality and quality. It covers techniques such as simulation, model checking, and physical design verification, as well as the importance of testing for manufacturing defects and yield. The integration of Design for Testability (DFT) principles is emphasized as a means to enhance testability and facilitate efficient fault diagnosis.

Uploaded by

Phoenix Blaze
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Introduction

Verification is an indispensable phase in the VLSI design flow, ensuring the


chip functions as intended. This comprehensive document delves into the
various verification methodologies and testing techniques employed at
different stages of the design process. From the initial RTL design to the final
manufactured chip, verification plays a pivotal role in identifying and
rectifying errors, ultimately enhancing product quality and reliability.

Verification and Testing in VLSI Design Flow

· To ensure the chip functions as intended, rigorous verification and testing


are conducted at every stage of the design cycle. This proactive approach
helps identify and rectify errors early, minimizing costly rework and delays.
VLSI Design Flow: Verification

Verification
Verification is performed to ensure that the design works according to the
specified functionality. It is a critical phase that is carried out multiple times
throughout the VLSI design flow. Verification must be repeated whenever the
design undergoes changes. If verification fails, remedial action can be taken
immediately. A significant portion of the VLSI design effort is spent on
verification.
Functional Verification: Simulation
o Simulation: This technique ensures the functional correctness of the
RTL using test vectors.
▪ Test Vectors: Sequences of zeros/ones with associated timing
information.
▪ The simulator obtains the response for the given RTL.
▪ The expected output is computed using another model (e.g., C, C++,
MATLAB).
▪ The output response is compared with the expected response.
▪ Merits: Fast and versatile.
▪ Demerits: Incompleteness.
Functional Verification: Model Checking
o Model Checking: This technique ensures the functional correctness of
the RTL using formal methods.
▪ Formal Methods: Use formal mathematical tools such as
deductions to prove properties.
▪ Once a property is proven mathematically, it holds for all test
stimuli.
▪ Merits: Completeness.
▪ Demerits: Computationally difficult.
Property Checking/Model Checking
o Define properties that must be satisfied for a given specification.
o Use formal methods to check whether properties are being satisfied in
the implemented design RTL.
Combinational Equivalence Checking (CEC)
o Establishes the functional equivalence of two models using formal
methods.
o Required whenever non-trivial design changes occur.
o Performed multiple times in the design flow.
Static Timing Analysis (STA)
o Synchronicity: Ensures that data launched by a flip-flop gets captured
in the sequentially adjacent flip-flop in the next clock cycle.
o STA: Ensures deterministic synchronous timing behaviour in a circuit.
▪ Considers the worst-case behaviour (may be pessimistic) but
always ensures timing safety.
▪ Performed multiple times in the design flow.
Physical Design Verification
o Physical Verification: Checks a set of rules during physical design
before sending the layout to the foundry.
o Design Rule Check (DRC): Rules defined by the foundries based on
manufacturing technology. All DRC violations must be fixed before
sending the layout to the foundry.
o Electrical Rule Check (ERC): Ensures proper connectivity, such as no
short circuits between distinct signal lines.
o Layout vs. Schematic (LVS) Check: Ensures that the layout is
functionally equivalent to the original netlist.
Rule Checking
o RTL: Ensures that RTL constructs used in the design have no
synthesis/simulation issues down the flow.
o Constraints: Ensures that no conflicting constraints are applied and no
constraints are missing.
o Netlist: Ensures that the connectivity of instances does not cause any
issues down the flow.

Testing
Verification: Ensures that the GDS represents the circuit correctly and meets
the original specifications.

Testing: Ensures that the fabricated chip does not have any manufacturing
defects. Testing is crucial during design to ensure:

▪ Testability: The chip can be easily tested.


▪ Debugging: Any defect can be easily diagnosed and fixed.
Manufacturing Defects: Origin
o Physical imperfections in a fabricated chip that are of permanent
nature.
o Origin of defects includes statistical deviations in material properties,
finite tolerances in process parameters, airborne particles, undesired
chemicals, and deviations in mask features.
o Large Area Defects: Simpler to eliminate.
o Small Area Defects: Random nature, inevitably appearing in chip
fabrication, increasing with die area.
Manifestation of Defects
o Short-Circuit and Open-Circuit: Functional failure.
o Change in Circuit Parameters: Such as delay.
o Faults: Testing focuses on finding defects problematic for circuit
behaviour. Defects are modeled using faults.
o Distortions: Photolithography can produce distorted features on a die
due to optical effects. Testing does not detect these distortions.
o Inconsequential Flaws: Deviations that do not cause measurable
changes, like too small particle sizes. Testing does not detect these
flaws.
Quality of Process: Yield
o Yield: Fraction of dies on a wafer that are good or without fatal
manufacturing defects, usually expressed in percentage.
o Factors Affecting Yield:
i. Die Area: Increase in area reduces yield.
ii. Defect Density: Average number of defects per unit of chip area.
iii. Clustering: Distribution of defects on the chip area.
o Yield Model: Estimates yield and profitability of IC manufacturing using
models like
▪ Y = (1 + Ad/α)−α× 100%
Testing Technique: Automatic Test Equipment (ATE)
o ATE Components: Test head, probe cards with probe needles.
▪ Probe needles contact the test pads on the design under test
(DUT).
o Test Program: Controls all operations.
o Test Patterns: Applied to the manufactured chip. Actual responses are
compared with expected responses.
▪ If comparison fails, the chip has defects.
▪ Failed chips can be diagnosed to find the root cause and take
corrective measures.
Fault Coverage and Defect Level
o Fault Coverage: Measures the ability of the test patterns to detect
faults.
o Defect Level (DL): Ratio of faulty chips among those that passed tests,
measured in parts per million (ppm).
▪ DL is a measure of test effectiveness, with commercial chips aiming
for DL < 500 ppm.
Design For Test (DFT)
o Ensures the chip design facilitates easy testing and debugging during
the RTL to GDS flow.
CONCLUSION
Effective verification, encompassing simulation, formal verification, and
physical verification, is essential for the successful development of
complex VLSI chips. By rigorously testing the design at multiple stages
and implementing robust fault models, engineers can significantly
improve product yield and reliability. The integration of Design for
Testability (DFT) principles further enhances the testability of the chip,
facilitating efficient fault diagnosis and repair. Through a meticulous
verification and testing regimen, the semiconductor industry can deliver
high-quality, reliable products to meet the demands of the evolving
technological landscape.

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