VLSI DESIGN FLOW: RTL TO GDS

• Transforming an idea into a tangible chip is a complex journey.

To effectively manage this intricate process, a 'divide-and-conquer' approach

is essential, breaking down the design into manageable sub-processes for
efficient execution.

• Below is a representation of the entire VLSI design flow, which we will

discuss in detail, step by step.

• From IDEA to GDS we term it as the VLSI Design

• From GDS to Chip we term it as the Fabrication

We will initially focus on the Pre-RTL design phase, which encompasses the
transition from a conceptual idea to Register Transfer Level (RTL) design
 PRE-RTL FLOW
PRE-RTL FLOW : takes a High lever concept of the product and represent
the Hardware portion of the implementation in RTL

below are the crucial steps involved in this phase

• Evaluate idea
o Product requirement
o what would be the demand in the market
o Financial viability
o Technical feasibility
• Specifications
o Functionality of the product
o PPA - (Power , Performance , Area)
▪ PPA is very crucial for analysing the economics of the product .
o TTM - (Time To Market)
• Hardware-Software Partitioning
o Identify Components
o Determine which components to be implemented in HW/SW

Hardware-software partitioning is a critical design phase that involves

judiciously selecting the optimal combination of hardware and software
components to implement a given system functionality. This strategic process
aims to leverage the strengths of both hardware (speed, customizability) and
software (flexibility, cost-effectiveness) to achieve the desired system
performance and cost targets.

• Following a meticulous evaluation of hardware functionalities, the design

is translated into a concrete representation using Hardware Description
Languages (HDLs) such as Verilog or VHDL. This stage marks the transition
from abstract concepts to a detailed hardware description, forming the
foundation for subsequent design phases.
 RTL TO GDS FLOW

Having transformed the conceptual blueprint into a detailed Register Transfer

Level (RTL) representation, the design journey now progresses to the
subsequent phase: RTL to GDS. This critical juncture marks the transition
from the abstract realm of RTL to the tangible domain of physical layout,
paving the way for silicon realization.

• [GDS - Graphical Database System : a binary file format that

represents a chip's layout information.]

• The RTL-to-GDS flow, a pivotal stage in the VLSI design process, is

further subdivided into distinct subprocesses(as shown below) to
facilitate efficient design implementation.

• The initial step in transitioning from RTL to a physical layout

involves generating a netlist through the process of logic
synthesis. This critical stage transforms the high-level RTL
description into a gate-level representation, laying the
groundwork for subsequent design phases.
• Logic Synthesis : the process by which RTL is converted into an
equivalent circuit as an interconnection of Logic Gates(Netlist).

• To derive an optimized netlist, the synthesis tool requires a

combination of inputs:
o RTL : generated RTL design of the hardware
o Library : comprehensive design library encapsulating standard
cell characteristics, and precise timing constraints and other
information about the design.
o Constrains : a meticulously defined constraint set outlining
the design's performance, power, and area objectives
• LOGIC SYNTHESIS TASK:

• RTL Synthesis :
o initial step of logic synthesis , translates an RTL to a netlist of
generic logic gates
• Logic Optimization :
o Optimization on a generic gate list
• Technology Mapping :
o Map a net list containing of generic logic gates to the standard
cells in the given technology library.
• Technology dependent Optimization :
o more optimization done to improve the performance , timing &
reducing the power consumptions.

Once we finish all the steps above, we get a better design called an
Optimized Netlist. hence can proceed to further step which is
Physical design.

• Physical Design(PD): Having successfully generated the netlist,

the design journey progresses to the subsequent phase: physical
design. This critical stage involves transforming the abstract
netlist into a concrete physical layout,
o physical design is the process by which a design in the form of
a Netlist is converted into an equivalent design in the form of
layout or GDS
The physical design phase, a pivotal step in the VLSI design flow, is
further subdivided into distinct subprocesses to facilitate the
meticulous transformation of the abstract netlist into a concrete
physical layout
• Physical Design Major Tasks:
• Chip Planning:
o The initial phase in physical design involves chip planning, where key
components like standard cells, macros, and memory are strategically
placed on the die. This stage also encompasses I/O planning and the
development of the power delivery network (PDN).
• Placement:
o The placement stage focuses on determining the optimal locations for
standard cells within the chip's layout. The primary objectives are to
minimize critical path delay, prevent congestion, and reduce overall
wire length.
• Clock Tree Synthesis (CTS):
o CTS involves designing the clock distribution network to ensure
minimal skew, guaranteeing that clock signals reach all circuit elements
simultaneously.
• Routing:
o The routing process is divided into two primary steps: global routing
and detailed routing. Global routing establishes the overall path for
interconnections, while detailed routing assigns specific physical paths
for each wire.
• Engineering Change Order (ECO):
o Throughout the physical design process, minor design modifications,
known as Engineering Change Orders (ECOs), may be necessary to
address design issues or improve performance.
• GDS Generation:
o The final stage involves generating the GDS file, a comprehensive
representation of the chip's layout, which serves as the blueprint for
photolithography.
• Verification and Optimization:
o Rigorous verification and optimization are conducted at each design
stage to ensure the chip meets performance, power, and area targets.
Any identified issues are addressed through design iterations or ECOs
 POST GDS FLOW

• Mask Fabrication:
o Mask fabrication is a critical precursor to chip manufacturing, involving
the creation of a physical representation of the chip's layout. This
process entails converting the digital design data into a tangible mask,
which will subsequently be used to transfer patterns onto the silicon
wafer during photolithography.

• Key Steps in Mask Fabrication:

o Data Preparation: Translating the complex layout data into a format
compatible with mask writing equipment, often involving data
optimization techniques like fracturing and resolution enhancement.
o Mask Writing: Utilizing advanced lithography techniques (laser or
electron beam) to imprint the design patterns onto a glass substrate
coated with photoresist.
o Quality Control: Rigorous inspection and defect correction processes
to ensure mask integrity and accuracy.
• Resolution Enhancement Techniques (RET):
o To address the challenges posed by diffraction and pattern distortions
at smaller feature sizes, advanced techniques like Optical Proximity
Correction (OPC) and Double/Multi-Patterning are employed to
enhance mask quality and improve pattern fidelity on the silicon wafer.

• Wafer Fabrication:
o Wafer fabrication is a complex process that transforms a silicon wafer
into a semiconductor die. It involves a series of intricate steps,
including:
o Front-End-of-Line (FEOL): Creating the foundational electronic
components such as transistors, resistors, and capacitors.
o Back-End-of-Line (BEOL): Interconnecting the fabricated components
using metal layers to form the complete circuit.

• Die Testing:
o Each individual die on the wafer undergoes rigorous testing to identify
defects and ensure functionality. Defective dies are marked for
subsequent removal.

• Packaging:
o To protect the die and enable external connections, it is encapsulated
within a package. The package design is critical for ensuring optimal
signal integrity, thermal management, and mechanical protection.

• Final Testing and Binning:

o The packaged chips undergo final testing to verify their functionality
and performance. Based on test results, chips are categorized into
different performance bins, determining their final applications and
pricing.
o This comprehensive process, from mask fabrication to final testing,
culminates in the production of functional semiconductor chips ready
for integration into various electronic systems.
From the initial Idea stage to the final chip stage, the product undergoes
through Verification and testing after completion of each step, in order to
maintain that correctness of the functionality of the product

This marks the end of our journey from IDEA TO FINAL PRODUCT(CHIP).

CONCLUSION
This comprehensive overview has traversed the intricate journey of
transforming an abstract concept into a tangible semiconductor chip.
From the initial ideation phase through the rigorous design, verification,
and fabrication processes, we've explored the key milestones and
challenges in the VLSI design flow. By understanding these fundamental
steps, we gain valuable insights into the complexities and intricacies of
chip development.
~*~