Proceedings of the 7th International Conference on Trends in Electronics and Informatics (ICOEI 2023)

IEEE Xplore Part Number: CFP23J32-ART; ISBN: 979-8-3503-9728-4

Design of Advanced Encryption Standard using

Verilog HDL
Busam Swayamprakash Panditi Jeevana Shreshta Chittapu Maheshwar Reddy
ECE,GRIET ECE,GRIET ECE,GRIET
Hyderabad,Telangana,India Hyderabad,Telangana,India Hyderabad,Telangana,India
[email protected] [email protected] [email protected]

K.Jamal* Kiran Mannem M.Suneetha

ECE,GRIET ECE,GRIET ECE,GRIET
Hyderabad,Telangana,India Hyderabad,Telangana,India Hyderabad,Telangana,India
2023 7th International Conference on Trends in Electronics and Informatics (ICOEI) | 979-8-3503-9728-4/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICOEI56765.2023.10125765

kjamal24@g mail.co m kiranmannem14@g mail.co m [email protected]

Abstract—Cryptography deals with the security and integrity converting the original data text to the encrypted cipher text.
of the data. Initially many algorithms were develope d to Whereas, the decryption process converts the generated
encode and decode the data but for securing large and cipher text to the original data. Cryptography is basically 2
confidential data, the existing algorithms are not reliable, so types:
AES was developed as a new standard for encrypting and
decrypting data. Initially it is mainly used to protect highly 1.Symmetric Key:
confidential data, later many applications in networking began
using AES as a standard to protect their data. It is primarily A symmetric key uses the same key for both
used to protect sensitive data, though it is also applied to encryption and decryption.
network backends to enhance data security. AES employs 2.Assymmetric key:
blocks that are 16 bytes long, and its keys can range in size
from 128 bits to 256 bits. The main purpose of using Verilog Different keys are used for the encryption and
instead of standard VHD L is that it provides very less decryption processes in asymmetric key i.e., public, private.
operation time and the propagation delay to encode and decode
the data are comparatively less than other HDL languages. The rules and recommendations for cryptography are created
Before AES , DES was used as the encryption standard. The by the National Institute of Standards and Technology
main drawback of DES is that the fixed key size of 56 bits. This (NIST). When NIST organized an open competition, The
problem is solved by AES by providing the flexibility of using Advanced Encryption Standard (AES), a submission by
required variable key size. Daemen and Rijmen that won the competition, was
subsequently standardized as AES.
Keywords—Advanced Encryption Standard, Input text,
Numerous apps now make use of the AES. It is an
Cipher text, Verilog.
encryption algorithm that uses a hidden key of the same size
to transform plain text into cypher text. There are currently
I. INT RODUCT ION only really two algorith ms that have been defined. The
Data security is a concept of securing the data. It mainly Advanced Encryption Standard and the Triple Data
deals with the protection of data by restricting unauthorized Encryption Standard are the two (TDES).
access. Data science focuses on information security. Nowadays, all the 64-bit desktops, mobile phones have
Modern technology must prioritize data security, one of native instructions for AES. Th is algorithm has become so
the most widely used encryption techniques for protecting popular that it is used almost all data security aspects. It is
data while it is in motion and at rest is Advanced Encryption estimated that the economic impact is more than $250 billion
Standard (AES). Data is encrypted and decrypted using a over the last 20 years in a study by Leech et al. The
block cypher by the symmetric encryption technique AES. It Advanced Encryption Standard is used in various protocols
is the perfect option for many applications, including and many applications like web browsers, Internet Protocol
wireless security, virtual private networks (VPNs), and (IP), Wi-Fi, 4G Long Term Evolution (LTE), Zigbee and
secure file sharing due to its strong security and effective Bluetooth, chip cards.
performance. Data is protected from unwanted access and The Advanced Encryption Standard (AES) algorithm
tampering by AES, which offers confidentiality, integrity, uses a key that is the same size as the incoming plain text to
and authenticity. In this regard, AES is a crucial part of data transform it into an encrypted text. Later, the decryption
security in the contemporary digital era, protecting sensitive procedure, which makes use of the same secret key, produces
data across a variety of apps. Cryptography is a technique the initial p lain text. It is typically 128 bits. In this case, the
used to protect data. By using this, the data can be secured key size is flexible and can range from 128 bits to 192 bites
fro m unauthorized access. The techniques which are used in to 256 bites. The number of cycles that must be run through
the cryptography are called as algorithms. These algorithms the algorithm depends on the key size. Because data
are a set of actions which are required to be performed on the protection is the AES's main purpose. The main required
data. Normally, an input data is given to this algorithm, upon security properties will surely depend on the type of the
processing the data an encrypted is generated. Which, is then application. In order understand the importance if these
communicated to the required user. The orig inal text is security properties some security requirements are
generated after decoding the data. Encryption is done by introduced.

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 Proceedings of the 7th International Conference on Trends in Electronics and Informatics (ICOEI 2023)
IEEE Xplore Part Number: CFP23J32-ART; ISBN: 979-8-3503-9728-4

II. DAT A ENCRYPT ION ST ANDARD frequently used in circu mstances where security is of ut most
DES is a cryptographic method for both encryption importance but where performance is not essential.
and decryption. It was created by IBM at the beginning of
the 1970s and is known as Data Encryption Standard. The In general, Triple DES is a trustworthy and
same private key is used for encryption and decryption in efficient method of preventing unauthorised entry to
symmetric -key cryptography.is the foundation of the sensitive data. Since it has consistently demonstrated
technique. The key used in DES is only 56 bits. Despite this, strength and security, it is a preferred option for businesses
DES was long regarded as safe and frequently employed in that need powerful encryption. Triple DES is still a good
systems like virtual p rivate networks, email encryption, and option for anyone seeking to secure their data with a tried -
electronic payment systems. and-true encryption method, despite the existence of newer
encryption algorithms.
The DES-based encryption was tougher for III. DES VS AES
attackers to crack as processing power grew, though. The
DES encryption could be broken using specialized hardware Two popular symmetric encryption methods are
in a matter of hours, according to studies done in the late AES (Advanced Encryption Standard) and DES (Data
1990s. Due to this, Trip le DES was created, a mo re secure Encryption Standard). While there are some parallels
version of DES that employs mult iple cycles of encryption between the two, there are also many significant differences.
with various keys. The key size of A ES and DES is one of their primary
distinctions. AES supports keys of 128, 192, or 256 bits,
The DES encryption algorith m is still used in so me whereas DES only supports keys of 56 b its. Since the bigger
legacy systems even though Trip le DES and other mo re key size makes it more challenging to crack, A ES is
recent encryption methods are available. Its use is usually therefore more secure than DES.
discouraged, however, because of the relatively lax security
it offers in co mparison to more advanced encryption In reality, AES is preferred over DES for the
techniques. Furthermore, the National Institute of Standards majority of applications, according to the National Institute
and Technology has discouraged the use of DES in of Standards and Technology (NIST).The block capacity of
government applications since 2005. (NIST). DES was once AES and DES also differs fro m one another. AES emp loys a
regarded as a secure encryption algorith m, but more recent 128-b it block size, co mpared to DES's 64-bit b lock size.
encryption techniques have since supplanted it due to its This means that AES can, in some circu mstances, be faster
comparatively short key length and attack vulnerabilities. than DES because it can encrypt bigger volu mes of data in a
For contemporary applications, it is generally advised to use single operation.
stronger encryption techniques like Advanced Encryption
Standard (AES) o r Elliptic Curve Cryptography (ECC), The encryption method used by AES and DES also
though Triple DES can be used in circumstances where differs. A Feistel network, used by DES, splits the input into
compatibility with legacy systems is needed. two halves and processes each independently. A ES, on the
In order to improve upon the init ial DES algorith m, other hand, emp loys a substitution-permutation network that
the Triple DES (Data Encryption Standard) symmetric-key repeatedly substitutes and reorders the inco ming data. A ES
block cypher algorithm was created. Co mparing Trip le DES is typically regarded as more safe than DES in terms of
to the DES algorith m, the main objective was to offer a security. It has been demonstrated that DES is susceptible to
higher degree of security and greater attack resistance. This brute-force attacks, in which an attacker tries each key until
was accomp lished by running the DES encryption algorith m they discover the right one. AES is significantly more
three times in a row, each t ime using a distinct key, yielding resistant to such assaults thanks to its bigger key size and
a key length of 168 bits, which is noticeably longer than more intricate encryption procedure.
usual. The use of three keys in Triple DES is referred to as
keying option 2, and it offers extra defence against brute Overall, AES has replaced DES as the preferred
force attacks, which entail t rying all possible key symmetric encryption method in many applicat ions, despite
combinations until the right one is discovered. the fact that DES was once popular and thought to be safe.
This is because of AES's larger key size, larger b lock size,
Trip le DES has demonstrated to be extremely and imp roved security. However, DES is still used in a few
secure, and there are no docu mented real-world attacks applications, especially in older platforms or when
against it. For companies needing stronger encryption, backward compatibility is necessary.
Trip le DES is also backwards -compatible with DES, making Table. 1
the switch fro m DES to Trip le DES simple. Triple DES is a parameter DES AES
common option for encrypting sensitive data because it is
also fairly simple to set up and use. Key length 56 bits 128 bits
Trip le DES has the major benefit of p roducing
ciphertext that is considerably longer than DES, making it Block length 64 bits 128 bits
much more challenging to decrypt. Triple DES may be
slower than other encryption methods as a result of the Rounds 16 10
longer ciphertext, though. Due to this, Triple DES is

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 Proceedings of the 7th International Conference on Trends in Electronics and Informatics (ICOEI 2023)
IEEE Xplore Part Number: CFP23J32-ART; ISBN: 979-8-3503-9728-4

AES's high degree of security and effectiveness Design and Implementation of the AES Algorithm in
make it a good choice for secure data transmission and Verilog by A. Ku mar and R. Gupta: Using the Xilin x ISE
storage. In order to encode and decrypt data, the symmetric design suite, this article demonstrates the imp lementation of
encryption algorithm A ES emp loys a block cipher. In many AES in Verilog HDL. The key expansion algorithm, the
different uses, including online banking, e -co mmerce, and encryption and decryption circuits, and the testbench are all
secure communication, it is widely used. One of the most covered by the writers in their discussion. They demonstrate
secure encryption algorith ms, the algorith m has been that both high throughput and minimal power consumption
authorized by the National Institute of Standards and can be achieved by the implementation [5].
Technology (NIST). Additionally, Verilog HDL's hardware
implementation of the A ES algorith m offers a practical V. DAT A SECURIT Y IN AES
method for ach ieving high throughput and min imal power AES offers data security by combining
consumption. It is also extensively used in FPGA and ASIC substitution, permutation and diffusion operation to turn
design due to its flexibility and scalability. Software plaintext data into ciphertext that cannot be deciphered
implementation of AES in Verilog has been shown to attain without the right key, AES offers a high degree of security.
high performance and low power consumption. The main Key generation, Encryption, Decryption and Key
reason for selecting Advanced Encryption Standard Management are the main steps which provide data security
algorith m lies in the key length options provided by the in A ES, mo re details regarding this steps will be exp lained
AES algorithm. in the module vi.
By ensuring that the plaintext data cannot be read
The AES algorith m was chosen for the paper without the proper key, these steps allow A ES to achieve a
because of its high degree of security and efficiency as well high degree of data security. The length of the secret and the
as its widespread use in numerous applications. An effective quantity of encryption rounds used determine how secure
method for achieving fast throughput and low power AES is. AES allows keys with lengths of 128, 192, and 256
consumption is the imp lementation of AES in Verilog, bits, and depending on the key length, the nu mber o f rounds
which makes it a great option for hardware design. For can be customized. The larger the key length and the
securing data in numerous uses, the Advanced Encryption number of rounds used, the higher the degree of security
Standard (AES) encryption algorith m is frequently used. provided by AES.
Designing and implementing A ES has emerged as a crucial
component of contemporary cryptography in light of the VI. A DVANCED ENCRYPT ION ST ANDARD A LOGORIT HM
rising demand for secure data storage and transmission. The The input block, output block, and state array all have a
AES code was designed using the Verilog Hardware length of 128 bits in the AES method. 4 32-bit strings
Description Language (HDL), wh ich was chosen for this altogether. which is denoted in the method by Nb=4.
study because of its many benefits. A high-level description
of dig ital circuits is provided by Verilog HDL, making it The amount of 32-bit words in the key used in the
simple to build intricate systems like AES. algorith m is denoted by the symbol Nk. Depending on the
key size being used—128 b its, 192 bits, or 256 bits —Nk
IV. LITERATURE OVERVIEW
accepts numbers of 4, 6, or 8.
A popular encryption algorithm for protecting data is The amount of AES rounds that must be run relies
called the Advanced Encryption Standard (AES). The on the key size that we emp loy in our algorith m. The
creation and use of AES emerged as a key component of symbol Nr, wh ich stands for "number of cycles" in the
contemporary encryption in response to the rising demand algorith m, is primarily determined by the value of "Nk,"
for secure data transmission and storage.
which denotes the number of 32-bit words in the key. The
An out-of-date online privacy standard was DES. There number of cycles is denoted by Nr, with Nr equal to 10 fo r
are 16 round operations and the key and data blocks have Nk = 4; 12 for Nk = 6; and 14 for Nk = 8.
corresponding bit sizes of 56 and 64.
It enumerates the power, area, and throughput trade-offs Table. 2
made in the AES design. Reduced area and power are AES Bits Key Length Block No of
achieved through iterative looping and an extension key (Nk) length Rounds
module. It has the greatest capacity because it employs a (Nb) (Nr)
pipeline register. Low-power ES programmes, for example,
benefit fro m these enhancements for security [2]. With the 128bit 4 4 10
goal of enhancing security, it is built on an 8-bit
microcontroller device [10]. reducing the amount of 192bit 6 4 12
electricity needed for real-time design [11]. 256bit 8 4 14
AES Encryption and Decryption Algorithm Design The AES algorith m has several rounds, with each round
and Imp lementation in FPGA Using Verilog HDL by K.
being further broken down into a number of processes for
Selvaku mar and R. Vijayaku mar. The design and execution
of AES in Verilog HDL using an FPGA are presented in this both encryption and decryption. The amount of Nr has a
paper. The implementation can accomplish high throughput significant impact on the AES round count.
and low latency, according to the writers' evaluation of the Some particu lar steps are dedicated to each round,
effectiveness of various encryption modes and key sizes [15]. these steps are repeated for all rounds , In 128 b its key size,

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Nu mber of rounds is 10, for each round a specific unique The type of kbox wh ich we want to use must be
key is used in all the processes. predefined and included. All the data values present in the
These unique keys are generated in key expansion module kbox are in hexa-decimal format.
of the AES. Where, Nr keys will be generated by using the kbox has a total of 256 values. Lookup tables are used for
original key. More details will be d iscussed in the key substitution process. The purpose of using lookup tables is
expansion section. because it will help reduce the hardware and reduce the
In each round of A ES we, have basically 4 steps sub - computation time required for the process. [X(i,j)] represents
bytes, shift rows, mix colu mns and adding round key. Key the corresponding hexadecimal data in the state matrix.
expansion will generate Nr unique secret key each of which [X’(i,j)] represents the data after the transformation.
will be used in each respective rounds .
Initially the input text is converted into hexadecimal it is
KBOX
converted in to a state matrix of 4x4. All the operations are
X
applied on this matrix. After, all rounds matrix is converted
to a text format.
X 0,0 X 0,1 X 0,2 X 0,3 X’0,0 X X X
’0,1 ’0,2 ’0,3
X 1,0 X 1,1 X 1,2 X 1,3
Adding key X’1,0 X’1,1 X’1,2 X’1,3
X 2,0 X 2,1 X 2,2 X 2,3
X’2,0 X X’2,2 X
X 3,0 X 3,2 X 3,2 X 3,3 ’2,1 ’2,3
Sub-bytes
X’3,0 X’3,2 X’3,2 X
’3,3
Shifting rows Fig. 2 sub-bytes

Shift rows:
Mixing columns
The data in the state matrix are cycled to the left during
Key
this procedure. The number of shifts required to be done are
Expansion decided by the position of the data in the state matrix. It is
Adding key done in rows of the matrix. For row one the data in the last
column of the matrix is shifted cyclically one time. In the
same matrix for row two shifting is done two times . The first
row in this process remains unchanged in all rounds as we
Sub-bytes are using index fro m ‘0’. [Xl,0 ] represents the elements of
the state matrix belong to the same row.

Shifting rows Xl,0 Xl,0 Xl,0 Xl,0 Xl,0 Xl,0 Xl,0 Xl,0

Shift rows
Adding key

Fig. 1 AES Block diagram

Sub-bytes: R1:
Each byte is affected separately by the non-linear byte
substitution. In this case, a new byte of data is substituted for
each existing byte in the state array. KBOX is used to derive R2:
the data that must be used in lieu of the state matrix's original
data.
R3:
It is a record with preset information. Where the specific
number for a given piece of data that needs to be replaced is
located by looking up one byte in the table's column, and the Fig. 3 shift-rows
second byte is used in the row. By choosing the suitable row
and column, the state matrices' old data is replaced with the
freshly downloaded information fro m the kbo x. Up until all Mix Columns:
the information in the state matrix is changed, this procedure
is repeated. In this stage, matrix with shifted data in rows is applied
as input. This matrix is then mult iplied with another matrix
which consists of predefined values, this new matrix is

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derived by using a standard polynomial a(X).The matrix Key expansion:

mu ltiplication is mostly similar to normal matrix
mu ltiplication except in this process instead of doing the AES uses a key expansion algorithm to create a series of
round keys that are used in both the encryption and
addition operation in the matrix mu ltiplication XOR
operation is done, this is done after mult iplying the decryption processes. The initial key is used as input for the
algorithm, wh ich creates the keys. The key expansion
corresponding data in a row with entire column, similar to
algorithm creates a total of (N+1) 128-bit round keys based
matrix mu ltiplication. [X(i,j)] represents the corresponding
on a sequence of transformations applied to the original key,
hexadecimal data in the state matrix. [X’(i,j)] represents the
where N is the number of rounds in the AES algorithm.
data after the transformation.
Co mbinational and sequential logic circuits can be used
to create the key expansion algorithm in Verilog HDL. The
X0,0 X X X 128-bit initial key, kept in a register, serves as the input to
0,1 0,2 0,3
the key expansion algorithm. The round keys are then
produced by the key expansion algorithm by applying a
X X X X X’0,0 X’0,1 X’0,2 X’0,3 number of transformations to the initial key. The stages
1,0 1,1 1,2 1,3 X’1,0 X’1,1 X’1,2 X’1,3 below are typical for the key expansion algorithm in Verilog
HDL:
X X X X X’2,0 X’2,1 X’2,2 X’2,3
2,0 2,1 2,2 2,3 A. Key expansion initialization:
X’3,0 X’3,2 X’3,2 X’3,3
X X X X The first-round key contains a copy of the original key.
3,0 3,2 3,2 3,3
B. Key schedule generation:
When the prior round key is subjected to a series of
transformations, the key expansion algorithm creates new
round keys. The necessary round keys are generated in this
Mix columns manner until all of them have been produced.

C. Key transformation:
Figure. 4 mix-columns The next round key is produced by the key expansion
algorithm by applying a set of transformation functions to the
prior round key. The bitwise, substitution, and permutation
Adding round key: techniques used in these transformations are frequently
combined.
In the stage, the data in the resultant state matrix
fro m previous process is XORed with each of the columns in
D. Key XOR:
the state matrix as the key is also 128bit size. In the
encryption process the initial key is added during round 0. The current round key and a constant number derived
Each round needs a different key, and these unique keys are from the K-box are XORed by the key expansion algorithm.
derived from the initial key used in round 0. This set of keys The keys in AES are produced using a key expansion
is generated in the key expansion module; the number of algorithm that uses the initial key to produce a series of
keys generated will depend on how many rounds are round keys. Comb inational and sequential logic circuitry can
involved in the algorithm. [X(i,j)] represents the be used to create the key expansion algorithm in Verilog
corresponding hexadecimal data in the state matrix. [X’(i,j)] HDL.
represents the data after the transformation.
It is the method by which all of the distinct keys used in
each round are generated. All of the keys generated are
Dl Dl+1 Dl+2 Dl+3
stored in a 44-word array. One key is used initially, and then
several keys are used in different stages. When handling
data, the AES encryption method uses bytes rather than bits.
X0,0 X X X X’0,0 X’0,1 X’0,2 X’0,3 Therefore, the 128-bit block size is regarded as 16 bytes.
during the coding process. These three methods
0,1 0,2 0,3
X’1,0 X’1,1 X’1,2 X’1,3 SUBWORD(), ROTWORD(), and RCON() are the primary
X X X X components of this process and are used for key expansion.
X’2,0 X’2,1 X’2,2 X’2,3
1,0 1,1 1,2 1,3 The SUBWORD () method is comparable to the sub-bytes
X’3,0 X’3,2 X’3,2 X’3,3 procedure, in order to create an output word, it accepts a
X X X X four-byte data input and applies the KBOX to each of the
2,0 2,1 2,2 2,3 four bytes. The ROTWORD() method applies a cyclic
permutation to a word of data when it receives it as input.
X X X X Instead of using KBOX, the process xor action is carried out
3,0 3,2 3,2 3,3 in RCON between the outputs of SUBWORD() and
ROTWORD().

Fig.5 Adding round key Assume a function "f" is produced by carrying out the
aforementioned 3 processes and is used to generate round
keys. The word is rotated cyclically left by one byte in the

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first operation, a byte from KBOX is substituted in the

second operation, and a round constant is used to XOR the
outputs of the first two operations (RCON). The key
extension is slightly different for 256 bits than it is for other
key sizes.
AES Decryption:
The decryption procedure consists of 4 stages.
Decryption is the reverse of encryption. The cypher text was
converted to ordinary text after the last stage of decryption.
Both Processes share a similar key but different steps. As
follows:
i) Inverse replacement bytes that work with every matrix
state. A different option is to use the inverted normal bo x Fig.6 Encryption output
(Inverse K-Box).
Simulation result of decryption:
ii) The second, third, and fourth rows are cyclically moved to Inputs:
the right by 1, 2, and 3 byte in the inv shift rows method. The in=128’h29C3505F571420F6402299B31A02D73A
top section stays the same. clock=1
iii)Inv add round key: Each state of the matrix is subjected to key=128’h5468617473206D79204B756E67204675
an XOR operation. Hence, the round key and curr ent state Output:
matrices acquired fro m the inv shift ro ws are XORed in plain txt=128’h4120452053616c676f726974686d0d 0a
every byte.
iv) Inv mix colu mn operation: Standard matrix fro m
polynomial mu ltiplication and current state matrices from inv
add round key

VII. DESIGN AND IMPLEMENTATION

AES was designed with a 16-byte data block whose main
module is a-AES-Encryption. Key growth, adding a round
key, and fundamental encryption techniques like sub -bytes,
shift-rows, and mix-co lu mns are all included in this
module's sub-modules.

Verilog is used in the decryption process to decode a 16 -

Fig.7 Decryption Output
byte data block. The top module is a2-AES-decryption.
This module includes the key expansion along with round VIII. CONCLUSION AND FUTURE SCOPE
and final operation as sub modules.
Verilog is used to build the proposed AES that uses
the fewest clock cycles and operation time on average for
both data encryption and decription. The results show that
V.RESULTS AND OBSERVATIONS
using Verilog instead of VHDL saves time and clock cycles.
Power consumption is reduced by fewer clock cycles. A ES
Simulation result of encryption:
is more d ifficult to hack or corrupt since it has more round
Input:
operations than DES. DES's key size is only 56 bits smaller
in=128’h54776F204F6E65204E696E652054776F
than AES's. System Verilog can be used to create AES, it
clock=1
provides greater benefits. High speed real-time applications
key=128’h5468617473206D79204B756E67204675
benefit greatly fro m hard ware imp lementation. It increases
Output:
adaptability.
cipher = 128’h29C3505F571420F6402299B31A 02D73A
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 Proceedings of the 7th International Conference on Trends in Electronics and Informatics (ICOEI 2023)
IEEE Xplore Part Number: CFP23J32-ART; ISBN: 979-8-3503-9728-4

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