2023 IEEE International Symposium on Smart Electronic Systems (iSES)

FPGA Implementation of Modified Lightweight

128-Bit AES Algorithm for IoT Applications
Jeyvarshni Vimalkumar* Harshitha Ramesh Babu* Bhaskar M
Department of ECE Department of ECE Department of ECE
NIT-Trichy NIT-Trichy NIT-Trichy
Tiruchirappalli, India Tiruchirappalli, India Tiruchirappalli, India
[email protected] [email protected] [email protected]
2023 IEEE International Symposium on Smart Electronic Systems (iSES) | 979-8-3503-8324-9/23/$31.00 ©2023 IEEE | DOI: 10.1109/ISES58672.2023.00069

*The two authors have contributed equally

Abstract—The rapidly increasing use of IoT devices with respect to gate size and number of clock cycles. Ahmed
necessitates a suitable encryption algorithm for data security. Tariq Sadiq and Faisal Hadi Faisal (2016) [4] introduced a
The widely used Advanced Encryption Standard algorithm modified algorithm in which the step sequence in the Shift
(AES) algorithm is computationally complex, thus unsuitable for
resource-constrained IoT devices. The proposed work implements Row step is dependent on some parts of the key value. In this
optimized alternatives for the 128-bit AES algorithm stages, design, the sequence sub-key is random in the AddRound key
aiming to minimize power and memory usage. A Modified since it is dependent on the key value. This helped to increase
Lightweight variant of AES was developed using Verilog HDL the confusion and diffusion levels.
and implemented on Artix-7 Basys-3 FPGA board. It was found Farah Tawfiq, Abdul Monem Rahma, and Hala Wahab
that the total on-chip power required by the modified variant
has been reduced by 81.92% for encryption and 47.21% for [5], suggested a modified AES algorithm for e-commerce
decryption. There is a significant decrease in the number of LUTs websites by employing techniques like reducing the number of
required with 76.84% for encryption and 53.53% for decryption, rounds, removing SubBytes operation, adding a pre-processing
making it a suitable algorithm for IoT lightweight applications. diffusion step (padding and zigzag) and replacing Shift Rows
Index Terms—AES, Cryptography, Lightweight Encryption, operation with Shift Columns. This resulted in increased
IoT, FPGA, Verilog
randomness degree, efficiency, and CPU usage. However, the
algorithm’s complexity remained the same since no changes
I. I NTRODUCTION
were involved in the MixColumn operation.
The proliferation of IoT devices has raised concerns about A. Illy, T. Yélémou, H. Tall and T. M. Dandjinou
cyber-attack vulnerability, making security a top priority. [6], proposed a lightweight variant called RLAES, which
[1].The Advanced Encryption Standard algorithm (AES) is optimized energy and improved security in comparison to the
the most widely used cryptographic algorithm [2]. It is a LAES proposed in [7]. In RLAES, a double permutation of
symmetric algorithm which uses 128-bit block cipher and a 128 bits each preceded by a 10-bit left shift step, replaces
variable key length of 128, 192 or 256 bits. The algorithm is the MixColumn of conventional AES. The number of rounds
faster since it performs encryption at the byte level. Brute force is reduced by 4, which optimizes energy consumption and
attacks are the only possibility to hack the AES algorithm. reduces the execution time of data blocks. However, the
AES uses 10, 12 and 14 rounds depending on its key lengths. security level is still lower than that of standard AES.
Through each round, various permutation and substitution
methods are applied to the block cipher increasing its III. M ODIFIED L IGHTWEIGHT AES A LGORITHM
confusion and diffusion. However, AES is a computationally The proposed algorithm optimizes the energy-consuming
complex algorithm, thus it is not compatible with IoT steps to make it lightweight, and presents various patterns
networks. Therefore, lightweight algorithms with smaller of permutation and substitution to increase data confusion
hardware and memory footprint can operate more efficiently and diffusion. Figure 1 shows the overall block diagram of
on low-power devices with limited processing capabilities. The the modified lightweight algorithm. Previous research [8] has
objective of this work is to propose a modified lightweight found that the encryption steps that consume the maximum
AES algorithm suitable for IoT connectivity platforms. energy are the SubBytes and MixColumn stages.
The proposed modifications are discussed below:
II. R ELATED W ORK
A. Substitution box
Recent research in lightweight cryptography has mainly
S-box( substitution box) is used to obscure the relationship
focused on designing secure systems for resource-constrained
between the key and the ciphertext. The following function is
devices. Eslam Gamal, Eman Shaaban, and Mohamed Hashem
used in standard AES for generating the S-box.
(2009) [3] proposed a lightweight design for the MixColumns
operation for hardware usage. The complexity was reduced (X 8 + X 4 + X 3 + X + 1)

2832-3602/23/$31.00 ©2023 IEEE 306

DOI 10.1109/iSES58672.2023.00069
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 E. Modified Mix Columns operation
MixColumn is an important source of diffusion but is
a computationally complex step. To reduce the complexity
and the number of multipliers and gates, a compact
architecture is proposed [10]. The equations 1,2,3 and 4,5
are for Conventional MixColumn and Inverse MixColumn
respectively:

⎡  ⎤ ⎡ ⎤⎡ ⎤
so c 02 03 01 01 so c
⎢s1 c ⎥ ⎢01

02 03 01⎥ ⎢ ⎥
⎢  ⎥=⎢ ⎥ ⎢ s1 c ⎥ (1)
⎣s2 c ⎦ ⎣01 01 02 03⎦ ⎣s2 c⎦
Fig. 1. Block diagram of modified lightweight AES algorithm

s3 c 03 01 01 02 s3 c

This paper uses the following higher degree polynomial to get Multiplication is distributive over addition in GF (28 ).
a lookup table with different values for more security [9]. Therefore, the operation of multiplication of two elements in
GF (28 ) can be taken as a linear combination of products of
(X 8 + X 6 + X 5 + X + 1) the first element and a single termed polynomial in GF (28 ).
[10]
B. Substitute bytes operation ⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ ⎤⎡ ⎤
A3 02 02 00 00 B3 00 00 01 01 B3
Substitute Bytes is a time-consuming step repeated in every ⎢A2 ⎥ ⎢00
⎢ ⎥=⎢ 02 02 00⎥ ⎢B2 ⎥ ⎢01
⎥⎢ ⎥ + ⎢ 00 00 01⎥ ⎢B2 ⎥
⎥⎢ ⎥
round. In the proposed design, this step is performed only once ⎣A1 ⎦ ⎣00 00 02 02⎦ ⎣B1 ⎦ ⎣01 01 00 00⎦ ⎣B1 ⎦
at the start of encryption. This operation substitutes the input A0 02 00 00 02 B0 00 01 01 00 B0
data bits with values from the modified S-box. (2)

C. Zig Zag patterning X 3 = B3 + B 2 X1 = B1 + B0 F0 = 2X3 + B2

The Zigzag pattern rearranges the bits inside the input data X2 = B2 + B1 X0 = B 0 + B 3 F1 = 2X1 + B0
to break the correlation among them. This step is carried
⎡ ⎤ ⎡ ⎤
out only once at the beginning of the encryption process to A3 F0 + X 1
compensate for the elimination of SubBytes in each round of ⎢A2 ⎥ ⎢B3 + 2X2 + X1 ⎥
⎢ ⎥=⎢ ⎥ (3)
the algorithm. This is done to add confusion and diffusion ⎣ A1 ⎦ ⎣ F1 + X 3 ⎦
to the input data [5]. The Zig-Zag pattern followed for A0 B1 + 2X0 + X3
pre-processing in this paper is given in Figure 2.
Calculations for Inverse Mix Column:
⎡ ⎤ ⎡ ⎤⎡ ⎤⎡ ⎤
C3 02 03 01 01 05 00 04 01 B3
⎢C2 ⎥ ⎢01 02 03 01⎥ ⎢ 01⎥ ⎢ ⎥
⎢ ⎥=⎢ ⎥ ⎢00 05 00 ⎥ ⎢ B2 ⎥
⎣C1 ⎦ ⎣01 01 02 03⎦ ⎣04 00 02 03⎦ ⎣B1 ⎦
C0 03 01 01 02 00 04 01 02 B0
(4)
Z0 = 4(A3 + A1 ) Z1 = 4(A2 + A0 )
Fig. 2. Zig-Zag pattern followed for Pre-processing
⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ ⎤
C3 A3 05 00 04 01 Z0 + A + 3
⎢C2 ⎥ ⎢A2 ⎥ ⎢00 05 00 01⎥ ⎢ ⎥
D. Shift Row Column operation ⎢ ⎥ = ⎢ ⎥⎢ ⎥ = ⎢ Z1 + A2 ⎥ (5)
⎣C1 ⎦ ⎣A1 ⎦ ⎣04 00 02 03⎦ ⎣ Z0 + A1 ⎦
The Shift Row step is replaced with the Shift Row Column
C0 A0 00 04 01 02 Z + A0
operation, making it difficult for a third party to predict the
operations [5]. This consists of swapping the location of Multipliers from the MixColumn block are used in the
each row and column, providing permutation for the data. computation of Inverse Mix Column operations, thus reducing
The bytes in the Shift Row Column operation are shifted, as the computational complexity of the algorithm.
shown in the following matrix.
⎡ ⎤ ⎡ ⎤ F. Round reduction
A00 A01 A02 A03 A00 A12 A20 A32 In the proposed AES algorithm the number of rounds has
⎢A10 A11 A12 A13 ⎥ ⎢A11 A23 A31 A03 ⎥
⎢ ⎥ ⎢ ⎥ been reduced from ten to six, conserving power and time.
⎣A20 A21 A22 A23 ⎦ → ⎣A22 A30 A02 A10 ⎦
Various studies have indicated that round reduction lowers the
A30 A31 A32 A33 A33 A01 A13 A21 overall time without compromising the security [5].

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 IV. R ESULTS

P̈ercentage of Power Used (%)

Verilog HDL implementation of the proposed algorithm has
100 3 3 5 2
been carried out in Xilinx Vivado. The simulation waveforms
are shown in Fig 3 and Fig 4. 30 40
45 45

A. Behavioral Simulation Results 50 28

Modified AES encryption: 36 6 45
47
Input data : 12345678901234567890123456789012 31 2
12 11
Key : 98765432109876543210980012345600 0 14 4
Encrypted data : 579db4b4f691cd45f3c1dfda6a62dd58

ec

ec
En

En
D

D
d

od
d

od
St

St
Modified AES decryption:

M
Input data : 579db4b4f691cd45f3c1dfda6a62dd58 I/O BRAM Logic Signals Clocks
Key : 98765432109876543210980012345600
Decrypted data : 12345678901234567890123456789012 Fig. 6. Power Summary

C. Hardware Implementation
The Basys3 Artix-7 FPGA board is used for implementing
the algorithms. The encryption and decryption module requires
Fig. 3. Behavioral simulation of modified encryption two 128-bit data for the input data and key value. For this
purpose, a Block Random Access Memory (BRAM) is used.
It is designed using the Xilinx Intellectual Property core (IP
core). The first 16 MSB bits of the output were mapped to
the LED pins of the FPGA board to verify the working of the
algorithms. Figures 7 and 8 shows the FPGA output obtained
for the modified AES algorithm.
Fig. 4. Behavioral simulation of modified decryption

B. Power and Utilization Summary

Figure 5 depicts the comparison of utilization summary
between standard and modified algorithms for FPGA
implementation. Figure 6 provides a summary of static and
dynamic power consumption.

Fig. 7. FPGA implementation of modified encryption algorithm

60 57

38
Ütilization(%)

40
32

20 16 16 16 15 16
13
8 9 9
4 3 55
0 Fig. 8. FPGA implementation of modified decryption algorithm

Std Enc Mod Enc Std Dec Mod Dec V. O BSERVATIONS AND I NTERPRETATIONS
A. Implementation Results
LUT FF BRAM IO The implementation results of standard and modified
algorithms in Vivado are as shown in Table I. It can be
Fig. 5. Utilization Summary concluded that the modified algorithm is better in terms of
processing time and hardware parameters.

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 TABLE I VI. C ONCLUSION AND F UTURE S COPE
C OMPARISON OF S TANDARD AND M ODIFIED A LGORITHMS
The results show that the total on-chip power required
Parameter Std. Std. Mod. Mod. has been reduced by 81.92% for encryption and 47.21% for
Encryp. Decryp. Encryp. Decryp, decryption. Further, the proposed algorithm is faster than
Processing 290 380 190 310 standard AES in terms of encryption and decryption time
time (us)
Total On Chip 1.234 1.021 0.223 0.539
by 34.48% and 18.42% respectively. The number of LUTs
Power (W) required has reduced by 76.84% for encryption and 53.53%
Slice LUTs 7954 6594 1842 3064 for decryption. The number of FF required has gone down by
FF 3487 3591 1447 1943 58.5% for encryption and 45.8% for decryption. The BRAM
BRAM 2 28.5 6.5 2.5
utilisation has reduced by 91.22% for decryption. Further, the
algorithm has an average Avalanche effect of 51.291% for
B. Evaluation of Confusion and Diffusion levels key bit flip and 53.585% for data bit flip when tested over 3
sets of data for each test, thus providing a good level of data
Confusion and diffusion are properties that define a secure security.The algorithm is thus suitable for IoT applications.
cipher, evaluated using Avalanche effect - a property wherein
a small change in either the key or plaintext results in a The proposed algorithm can be integrated with an
significant change in the ciphertext [7]. A good encryption IoT connectivity platform such as Bluetooth, Wi-Fi etc.
algorithm should have an avalanche effect of > 50%. To Suitable architectures for the communication protocols can
calculate the degree of security, 10 sets of data were used in be developed and interfaced with the modified AES and its
each case on both the standard and modified algorithms. Table performance can be analysed.
II and Table III show the results of 10 such sets of data for the
modified algorithm. Table IV shows the comparison between R EFERENCES
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