Cadence Digital
Cadence Digital
1. Switch on the computer and enter to Red Hat Enterprise Linux (RHEL), a
Linux-based operating system environment.
2. Select the User- “Other” and enter user name and password as follows.
User Name- root
Password- root123
3. In Desktop Create a folder to do the digital design flow: Right click in the
Desktop and select Create Folder. It will create a new folder. Give folder
name without any space.
4. Inside the created folder paste the HDL files (Digital circuit and testbench) or
Right click in the desktop and select create document -> empty file. It will
create an empty text file. File name should be with HDL Extension (.v).
5. Double click the created .v text file. Inside this text file type the Verilog HDL
Coding for the circuit. Module name must be the same as the name of .v file.
6. Do the same for the test bench.
7. Save and close both the files.
8. Additional files needed to copy to the created folder are ‘LEF’ and ‘LIB’
folders and ‘CONSTRAINTS.SDC’ and ‘RUN.TCL’ files.
9. Right click in the same folder and select open in terminal.
10. To invoke the cadence environment, enter the below commands one by one in
the terminal window.
csh
Source /home/cad/cshrc (mention the path of the tools)
11. “Welcome to Cadence Tools Suit” message will display in terminal window.
FUNCTIONAL SIMULATION:
14. The simulation can be done using the Incisive simulator. For that create the
cds.lib and hdl.var files for to Compile, elaborate and simulate the design and
test bench.
15. Click the cds.lib file.
16. Save the file.
17. Choose any of the option listed in new cds.lib file window.
18. After that give ok. The NCLaunch window will appear after giving ok.
NCLaunch Window- Left side the HDL files can be seen. Right side of the
window has worklib and snapshots directories listed.
Worklib is the directory where all the compiled codes are stored while Snapshot
will have output of elaboration which in turn goes for simulation.
Compilation:
Simulation:
SYNTHESIS:
32. Synthesis will be done using RTL Compiler. It is a script language called Tool
Command Language( TCL)
33. The run.tcl Script file is explained below
- Give the path of the library w.r.t to the directory you are in using the command:
set_attribute lib_search_path
- Give the path of the RTL files with respect to the directory you are in using the
below command: set_attribute hdl_search_path
- Read the library from the directory specified in giving the path for the library
files in First line using the command: set_attribute library (slow.lib) is the
name of the library file in the directory --library.
- Read the RTL files from the directory specified in the second line. The RTL
files are in the directory name: read_hdl file.v
34. Inside the run.tcl file make the necessary changes as per the design name and
paths (path, HDL file name, Report names).
35. Invoke RTL Compiler by typing below command in the terminal window.
rc -f run.tcl -gui
36. The GUI - Graphical User Interface window will appear
37. It will generate the Area, Power, gate and Timing Reports for the designed
circuit and the reports can be viewed in the created folder.
38. GUI: Double click the file from left side of the window and the RTL view of
the design appears.
39. Drag the RTL Structure to view the standard cells.