ON-CHIP PERIPHERALS clock by multiplying the clock source by a specific factor; thus,

All the C54X devices have the same CPU, but different on-chip a clock source with a lower frequency than that of the CPU
peripherals are connected to their CPUs. should be used.
The C54X devices have these on-chip peripheral options: 10.12.7 Serial Ports
 General-purpose I/O Pins (BIO and XF) The serial ports on the C54X vary by device, but four types of
 Software-programmable Wait-State Generator serial ports are represented: synchronous, buffered,
 Programmable Bank-switching Logic multichannel buffer (McBSP) and time-division multiplexed
 Host Port Interface (HPI) (TDM). Table 10.7 gives the number of each type of serial
 Hardware Timer ports on the various C54X devices.
 Clock Generator
 Serial Ports C54 C54 C54
 Synchronous Serial Ports Serial C5 2, 5, 8/ C54 C54 C54
 Buffered Serial Ports ports 41 C54 C54 C54 02 10 20
 Time-division Multiplexed (TDM) Serial Ports 3 0 9
Synchron
10.12.1 General-Purpose I/O Pins 2 0 1 0 0 0 0
ous
Each C54X device has two general-purpose I/O pins: BIO and Buffered 0 1 1 2 0 0 0
XF. BIO is an input pin that can be used to monitor the status of McBSP 0 0 0 0 2 3 6
external devices. XF is a software-controlled output pin that TDM 0 1 0 0 0 0 0
allows you to signal external devices.
10.12.2 Software-Programmable Wait-State Generator Synchronous Serial I/O Ports The synchronous serial ports
The software-programmable wait-state generator extends are high-speed, full-duplexed serial ports that provide direct
external bus cycles upto seven machine cycles to interface with communication with serial devices such as codecs, analog-to-
slower off-chip memory and I/O devices. The software wait- digital (A/D) converters and other serial systems. When more
state generator is incorporated without any external hardware. than one synchronous serial port resides on a C54X, these ports
For off-chip memory accesses, from zero to seven wait states are identical but independent. Each synchronous serial port can
can be specified within the software wait-state register operate at upto one-fourth the machine cycle rate (CLKOUT).
(SWWSR) for each 32K-word block of program and data The synchronous serial port transmitter and receiver are double
memory, and for the 64K-word block of I/O space. buffered and individually controlled by maskable external
10.12.3 Programmable Bank-Switching Logic interrupt signals. Data is framed either as bytes or as words.
The programmable bank-switching logic can automatically 10.12.8 Buffered Serial Ports
insert one cycle when an access crosses memory bank A buffered serial port (BSP) is a synchronous serial port that is
boundaries inside program memory or data memory. One cycle enhanced with an autobuffering unit and is clocked at the full
can also be inserted when an access crosses from program CLKOUT rate. It is full-duplexed and double-buffered to offer
memory to data memory. This extra cycle prevents bus fl exible data stream length. The autobuffering unit supports
contention by allowing memory devices to release the bus high-speed transfers and reduces the overhead of servicing
before other devices start driving the bus. The size of a memory interrupts.
bank for bank switching is defined by the bank switching 10.12.9 TDM Serial Ports
control register (BSCR). A time-division multiplexed (TDM) serial port is a
10.12.4 Host Port Interface synchronous serial port that is enhanced to allow time-division
The host port interface (HPI) is an 8-bit parallel port that multiplexing of the data. It can be configured for either
provides an interface to a host processor. synchronous operations or for TDM operations and is
Information is exchanged between the ¢54X and the host commonly used in multiprocessor applications.
processor through ¢54X on-chip memory that is accessible to
both the host processor and the C54X.
10.12.5 Hardware Timer
The C54X features a 16-bit timing circuit with a 4-bit prescaler.
The timer counter is decremented by 1 at every CLKOUT
cycle. Each time the counter decrements to 0, a timer interrupt
is generated. The timer can be stopped, restarted, reset or
disabled by specific status bits.
10.12.6 Clock Generator
The clock generator consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator can be
driven internally by a crystal resonator circuit or externally by a
clock source. The PLL circuit can generate an internal CPU