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Computer Organization Notes

COmputer Organization (Visvesvaraya Technological University)

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2.1 Accessing Input/output Devices

A single bus-structure can be used for connecting I/O devices to a computer. The bus enables
all the devices connected to it exchange information.
Each I/O devices is assigned a unique set of address. Typically, the bus consists of three sets
of lines used to carry address, data and control signals.
When the processor places an address on address lines, the intended-device responds to
command. The processor requests either a read or write operation. The requested data are
transferred over the data-lines.

Figure : A signal-bus structure

There are 2 ways to deal with I/O devices

i. Memory Mapped I/O
ii. I/O- mapped I/O
Memory Mapped I/O:
 Memory and I/O devices address-space are different.
 A special instruction named IN and OUT is used for data transfer.
 Advantage of separate I/O spaces: I/O devices deal with fewer address lines.
 I/O transfer for an input device.

Figure: Input/ Output interface for an input device

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Address Decoder: enables the device to recognize its address when this address appears
on the address lines.
Status Register: Contains information relevant to operation of I/O device.
Data Register: Holds data being transferred to or from processor. There are two types
1. DATAIN: Input buffer associated with keyboard.
2. DATAOUT: Output data buffer of a display/printer.

 The address decoder decodes the address sent by the CPU and enables the device to
recognize its address. The data register holds the data being transferred to or from the
processor.
 The status register contains information relevant to the operation of the I/O device. Both
status and data are connected to the data bus and assigned unique address.
 The address decoder, the data and status register and control circuitry required to
coordinate I/O transfer constitute device interface circuit.
 The speed of operation of the I/O device varies from that of the processor. An instruction
that reads a character from the keyboard should be executed only when a character is
available in the I/p buffer of keyboard interface. Also, it has to be made sure that a
character is read only once.
 For an input device such as keyboard, a status flag is included in the interface circuit as a
part of status register. This flag is set to 1 when a character is entered at the keyboard and
cleared to 0 once the character is read by the processor.
 Hence by checking the SIN flag, software can ensure that CPU is reading valid data. This
is done in a program loop that repeatedly reads the ststus register and checks the status of
SIN. When SIN becomes equal to 1, the program reads the input data register. The
register that are used for i/o operations are shown below

Figure: Registers used in I/O operations

The status register consists of 2 flags SIN and SOUT that are used to check the status of
keyboard and display respectively. The flags KIRQ and DIRQ are used to control the devices.
The data from the keyboard are made available in the DATAIN register and the data sent to the
display are stored n DATAOUT register.
For example consider COMPUTE and PRINT routines. The routine is executed in response to
an interrupt request is called interrupt service routine. Transfer of control through the use of
interrupt happens.

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The processor must inform the device that its request has been recognized by sending interrupt
acknowledge signal. One must therefore know the difference between interrupt versus
subroutine.
Interrupt latency is concerned with saving information in register will increase the delay
between the time an interrupt request is received and the start of execution of the interrupt
service routine.

Fig: Transfer of control through the use of interrupts

The method has the drawback that, the processor wastes its time in checking the status of the
device before the actual data transfer takes places. A program that reads, one lines form the
keyboard stores it in a memory buffer, and echoes it back to the display.

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2.2 Interrupts
To avoid the processor being not responding any useful computation, a hardware signal s
called an interrupt to the processor can do it. At least one of the bus control lines, called an
interrupt request line, usually dedicated for this purpose. An interrupt service routine (program)
usually is needed and is executed when an interrupt request is issued.

2.2.1 Interrupt Hardware:

An I/O device requests can interrupt by activating a bus line called interrupt-request. A signal
interrupts –request line may be used to serve n devices as shown in figure.

Figure: An equivalent circuit for an Open-drain bus used to implement a Common

Interrupt Request line
All devices are connected to the line via switches to ground. To request an interrupt, a device
closes its associated switch. Thus if all interrupt request signals INTR1 to INTRn are inactive
i.e., if all switches are open the voltage on the interrupt request line will be equal to V dd . This is
inactive state of the line.
When a device requests a interrupt by closing is switch, the voltage on the line drops to 0,
causing the interrupt request signal, INTR received by the processor to go to 1.
Since the closing of one or more switches will cause the line voltage to drop to 0, the value of
INTR is the logical OR of the requests from individual devices i.e.,
INTR = INTR1 + … + INTRn

2.2.2 Enabling and Disabling Interrupts

The computers must provide the facilities to the program to control the event that takes place
during program execution. The arrival of an interrupt request from an external devices cause the
CPU to suspend the execution of another. As interrupts can arrive at any time, they may alter the
user programs. Hence the interruption of programs must be carefully controlled.

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When device activities the interrupt request signal it keeps this signal activated until it learns
that CPU has accepted the requested. This means that interrupt request signal will be active
during the execution of the interrupt service routine (ISR).
It is essential to ensure that it active request signal does not lead to successive interruptions,
causing the system to enter an infinite loop from which it cannot recover.

The following are the techniques that can be used to solve the problem
Technique-I
The processor hardware ignores the interrupt request line until the execution of the first
instruction of ISR has been completed. The 1 st Instruction in ISR would be interrupt disable
instruction. These instructions interrupts will be disabled until the execution of interrupt enable
instruction.
The last instruction in the ISR would be interrupt enable instruction i.e., before return from
interrupt instruction. The CPU must guarantee that execution of return from interrupt instruction
is completed before further interruption can occur.

Technique –II
One bit in the Process status (PS) is called interrupt enable, indicates whether interrupts are
disabled or not. An interrupt is arrived while this bit is equal to 1 will be accepted. To disable
interrupts, the CPU does the following
 Save the contents of PS on stack
 Disable the Interrupt Enable bit in PS disabling further interrupts
 When a return from interrupt instruction is executed. The contents of PS are restored
from the stack, setting IE bit back to 1.

Technique-III
The processor has a special interrupt request line for which the interrupt handling circuit
responds only to the leading edge of the signal. Such a line is said to be edge triggered. In this
case the processor will receive only one request regardless of how long the line is activated.
Summarizing sequence of events involved in handling interrupts
i. The device raises an interrupt request
ii. The processor interrupts the program currently being executed
iii. Interrupts are disabled by changing the control bits in the PS {expect in the case of
edge triggered}
iv. The device is informed that its request has been recognized by ISR.
v. Interrupts are enabled and execution of the interrupted program is resumed.

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2.3 Handling Multiple Devices
There can be situation where a number of devices can interrupt simultaneously or device may
request an interrupt caused by device Y is being serviced. This gives to a number of questions
1. How can the processor recognize the device requesting an interrupt?
2. How can processor obtain the starting address of ISR?
3. Should device be allowed to interrupt the processor while another interrupt I being
serviced?
4. How should two or more simultaneous interrupt requests be handled?

Whenever a device request an interrupt, its information available in the status register with its
one of the bit set to 1, which we call it has IRQ bit. If multiple device request the interrupt
request in case of request from keyboard and display with bits known as KIRQ and DIRQ,
respectively.
The simplest way to identify the interrupting device is to have the interrupt- service routine
pool the entire I/O device connected to bus.
The first device encountered with its IRQ bit set is the device that should be serviced. An
appropriate subroutine is called to provide the requested service. The polling scheme is easy to
implement. Its main disadvantage is the time spent in interrogating the IRQ bits of the entire
device that may not be requesting any service.

2.3.1 Vectored Interrupts:

The term vectored interrupts refers to all interrupt handling schemes. Where a device
requesting an interrupt may directly identify by processor and the processor can immediately
start executing the corresponding ISR.
A device requesting an interrupt can indentify itself by sending a special code to the processor
over a bus. The code supplied by the device may represent the starting address of the ISR for that
device and its length ranges from 4 to 8 bits. The remainder of the address is provided by the
processor based on the area in its memory where the address for ISR is located.
The location pointed to by the interrupting device is used to store the starting address of the
ISR. The processor reads this address, called the interrupts vector, and loads it into the PC. The
interrupt vector may also include a new value for the processor status register.
When a device sends an interrupt request, the processor his busy in serving another interrupt
request. Than it must first complete the execution of earliest request, which may require the use
of the bus.
There may other which causes further delays if interrupts happen to be disabled at the time the
request is raised. The interrupting device must wait to put data on the bus only when the
processor is ready to receive it, When an processor is ready to receive the interrupt-vector code,
it activates the interrupt-acknowledge line, INTA. The I/O device responds by sending its
interrupts vector code and turning off the INTR signal.
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2.3.2 Interrupt Nesting

The I/O device should be organized in a priority structure so that if a high priority device
request an interrupt service while CPU is executing an ISR. The high priority device has to be
serviced. To implement the scheme, we can assign a priority level to the processor that can be
changed under program control (the priority of the device can be change using the program). The
processor accepts interrupt only from the device that has priority higher than its own. At the time
of execution of the ISR. The priority of the CPU is raised to the priority of the device.

INTR 1 I NTR p
P rocessor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration
circuit

Figure 4.7. Implementation of interrupt priority using individual

interrupt-request and acknowledge lines.

The action disables interrupts from device at the same level of priority or lower. Interrupt
request from higher priority devices will be continue to be accepted. The processor priority is
usually encoded in a few bits of the processor status word (ps). It can be changed by program
instruction that write into the PS.
These are privileged instructions, which can be executed only when the processor is running in
the SUPERVISOR mode. The CPU is in supervisor mode only when it is executing OS routines.
It switches to user mode before beginning to execute application program. A user program
cannot accidently change priority of CPU. An attempt to execute a privileged instruction in user
mode raises a PRIVELEGED exception.

2.3.3 Simultaneous Requests:

If processor receives simultaneous requests, it must have some means of deciding which
request to service first. The processor simply accepts the request having the highest priority. If
devices share same interrupt request line some other mechanism is needed.
Polling the status register of the I/O devices is one of the simplest mechanisms. In this case,
the priority is determined by the order in which devices are polled. When vectored interrupt are
used, we must ensure only one device is selected to send the interrupt vector code. A daisy chain
is used for this purpose.

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The interrupt request INTR is common to all devices. The INTA connected in a daisy chain
fashion such that it propagates serially through the devices. When several devices raises
interrupt, the CPU responds by setting INTA to1.
The signal is received by device 1 and is passed onto device 2 only if it does not require. If
any device is having a pending request it blocks the INTA signal and proceeds to place its
identifying code on the data lines.
P ro c e s s o r

I NTR

Device 1 Device 2 Device n

INTA

(a) Daisy chain

I NTR 1
P ro c e sso r

Device Device
INTA1

INTR p

Device Device
INTA p
Priority arbitration
circuit

(b) Arrangement of priority groups

Figure 4.8. Interrupt priority schemes.

Therefore in daisy chain, the device that is electrically closest to processor has the highest
priority. Using this technique devices are organized into groups, and each group is connected at a
different priority level.

2.4 Controlling Device Requests

It is important to ensure that interrupt are generated by those devices which are not idle.
There must be mechanism in the interface circuit of individual devices to control whether a
device is allowed to generate interrupt request or not. This control is usually provided in the form
of an interrupt enable bit in the device interface circuit. The keyboard interrupt enable, KEN and
display interrupt enable.
DEN flags in CONTROL register perform this function. If either of these flags is set. The
interface circuit generates an interrupt request whenever the corresponding status flag register is

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set. At the same time, the interface circuit sets bits KIRQ or DIRQ to indicate that the keyboard
or display unit respectively, in requesting an interrupt.
If am interrupt enable bit is equal to 0, the interface circuit will not generate interrupt request,
regardless of the state of the status flag.
To Summarize
 An interrupt enable bit in a control register determines whether the device is allowed to
generate an interrupt request.
 At the processor end, either an IE bit in PS register or a priority structure determines
whether a given interrupt register will be accepted.

To perform the operation of interrupt, we need to initialize the interrupt process. This may be
accomplished as follows
i. Load the starting address of the interrupt service routine in location INTVEC
ii. Load the address LINE in a memory location PNTR. The ISR will use this location as a
pointer to store the input characters in the memory.
iii. Enable keyboard interrupts by setting bit 2 in register CONTROL to 1.
iv. Enable interrupts in the processor by setting to 1 the IE bit in the processor status register,
PS.
Once the initialization is completed, typing a character on the keyboard will cause an interrupt
request to be generated by the keyboard interface. The program being executed at that time will
be interrupted and the ISR will be executed. This routine has to perform the following tasks.
i. Read the input character from the keyboard input data register. This will cause the
interface circuit to remove its interrupt request.
ii. Store the character in the memory location pointed to by PNTR, and increment PNTR.
iii. When the end of the line is reached, disable keyboard interrupts and inform program
main.
iv. Return form interrupt.

2.5 Exceptions
An interrupt is an event that causes the execution of one program to be suspended and execution
of another program to begin. So, for we have dealt only with interrupts caused by requests
received during I/O data transfer.
The term exception is often used to refer to any event that causes an interruption. Hence,
I/O interrupts are one example of an exception. There are few other kinds of exceptions are
i. Recovery from errors
ii. Debugging
iii. Privilege Exception

i. Recovery from errors:

Computers use a verity of techniques to ensure that all hardware components are operating
properly. For ex, many computers include an error checking code in the main memory, which
allows detection of errors in the stored data. If an error occurs, the control hardware detects it
and informs the processor by raising an interrupt.

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The processor my also interrupt a program if it detects an error or an unusual condition
while executing instruction of the program. For example, the op-code field of an instruction or an
arithmetic instruction may attempt a division by zero.
When exception processing is initiated as a result of such errors, the processor proceeds in
exactly the same manner as in case of an I/O interrupt request. It suspends the program being
executed and starts am exception service routine. This routine takes appropriate action to recover
from error, if possible or to inform the user about it.

ii. Debugging:
System software usually includes a program called a debugger, which helps programmer to
find errors in a program. The debugger uses exceptions to provide 2 important facilities called
trace and breakpoints.
When the processor is operating in the trace mode, an exception occurs after execution of
every instruction, using the debugging program as the exception service routine. It examines the
contents of register, memory locations and so on. On return, the next instruction in the program
is activated again; the trace exception is disabled during the execution of the debugging program.
Breakpoints provide a similar facility, except that the program being debugged is interrupted
only at specific points selected by the user. An instruction called trap or software interrupt is
usually provided for this purpose. When the program is executed and reaches that point, it is
interrupted and the debugging routine is activated. This gives the user a chance to examine
memory and register contents.

iii. Privilege Exception

To protect the OS of a computer from being corrupted by user programs, certain
instructions can be executed only while the processor is in the supervisor mode. These are called
privileged instructions. For ex: when the processor running in the user mode, it will not execute
an instruction that changes the priority level of the processor or that enables the user program to
access areas in the computer memory that have been allocated to other users.
An attempt to execute such an instructions will produce a privilege exception, causing the
processor to switch to the supervisor mode and begin executing an appropriate routine in the OS.

2.6 Direct Memory Access

To transfer large blocks of data at high speed, an alternative approach is used. A special
control unit may be provided to allow transfer of a block of data directly between an external
device and main memory, without continue intervention by the processor. This approach is
called direct memory access, or DMA.
DMA transfers are performed by a control circuit that is part of the I/O device interface. We
refer to this circuit has a DMA controller. Its function his to increment the memory address for
successive words and keep track of the number of transfers.
Although a DMA controller can transfer data without intervention by the processor, its
operation must be under the control of a program executed by the processor.
While a DMA transfer is taking place, the program that requested the transfer cannot
continue, and the processor can be used to execute another program. After the DMA transfer is

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completed, the processor can return to the program that requested the transfer. Figure shows an
example of the DMA controller registers that are accessed by the processor to initiate transfer
operations
R / W’

Figure: Registers in DMA interface

Two registers are used for storing the starting address and the word count. Third register
continue status and control flags. The R/W bit determines the direction of the transfer. When this
bit is set to 1 by a program instruction, the controller performs a read operation i.e., it transfer
data from the memory to the I/O device. Otherwise it performs the write operation.
When the controller has completed transferring a block of data and is ready to receive
anther commend, it sets the DONE flag to1. Bit-30 is the interrupt enable flag, IE.

Disk/DMA
Controller

Figure: Use of DMA controllers in a computer system

A DMA controller connects a high speed network to the computer bus. The disk controller,
which controls two disks, also has DMA capability and provides 2 DMA channels. It can
perform 2 independent DMA operations, as if each disk has its own DMA controller. To start a
DMA transfer of a block of data from the main memory to one of the disks, a program writes the
address and word count information into the registers of the corresponding channel of the disk
controller.
When the DMA transfer is completed, this fact is recorded in the status and control register of
the DMA channel by setting the “done” bit. At the same time, if bit is set, the controller sends an
interrupt request to the processor and set the IRQ bit. The status register can also used to record
information such as whether the transfer took place correctly or error occurred. Top priority is
given to high-speed peripherals such as disk, a high speed network interface, or a graphics
display device.
The DMA controller can be said to “steal” memory cycles from the processor. Hence, this
interweaving technique is usually called cycle stealing. DMA controller may be given exclusive
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access to main memory to transfer a block of data without interruption. This is known as block
or burst mode.

Bus Arbitration
The device that is allowed to initiate data transfers on the bus at any given time is called the
bus master. Bus arbitration is the process by which the next device to become the bus master is
selected and bus mastership is transferred to it.
There are 2 approaches to bus arbitration: Centralized and Distributed
In centralized arbitration, a single bus arbiter performs the required arbitration.
In distributed arbitration, all devices participate in the selection of the next bus master.

i. Centralized Arbitration
The bus arbiter may be the processor or a separate unit connected to the bus. Figure shows the
basic arrangement in which the processor contains the bus arbitration circuitry. In this case, the
processor is normally the bus master unless it grants bus mastership to one of the DMA
controller.

BBSY
BR
Processor
DMA DMA
controller controller
BG1 1 BG2 2
Figure: A simple arrangement for bus arbitration using a daisy chain

DMA controller 2 requests and acquires bus mastership and later releases the bus. During its
tenure as the bus master, it may perform one or more data transfer operations, depending on
whether it is operating in the cycle stealing or block mode. After it releases the bus, the processor
resumes bus mastership.
The timing diagram in figure 2 shows the sequence of events for the device in the figure.

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DMA controller 2
Time
BR
asserts the BR signal. Processor asserts
BG1
the BG1 signal
BG1 signal propagates
BG2 to DMA#2.
BBSY
Bus
master Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.
Figure: Sequence of signals during transfer of a bus mastership for the devices

ii. Distributed Arbitration

This means all devices waiting to use the bus have equal responsibility in carrying out the
arbitration process, without using a central arbiter. Each device on the bus is assigned a 4bit
identification number when one or more device requests the bits; they assert the start arbitration
signal and place their 4 bit ID numbers on four open collector lines, ARB0 through ARB3.
The DMA controller indicates that it needs to become the bus master by activating the Bus-
Request line BR. This is an open-drain line for the same reasons that the interrupt request line in
figure is an open drain line.

Figure: A distributed arbitration Scheme

The signal on the Bus-Request line is the logical OR of the bus requests from all the devices
connected to it. When Bus-Request is activated, the processor activates, the Bus-Request signal,
BGI, indicating to the DMA controller that they may use the bus when it becomes free.

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If DMA controller 1 is requesting the bus, it blocks the propagation of the grant signal to
other devices. Otherwise, it passes the grant downstream by asserting BG2. The current bus
master indicates to all devices that it is using the bus by activating another open-collector line
called BUS-Busy, BBSY. Hence, after receiving the bus grant signal, a DMA controller waits
for Bus-Busy to become inactive, and then assumes mastership of the bus. At this time, it
activates Bus-Busy to prevent other devices from using the bus at a same time.
The net outcome is that the code on the fur lines represents the request that has the highest ID
number. The drivers are of the open-controller type. Hence, if the input to one driver is equal to
one and the input to another driver connected to the same bus line is equal to 0 the bus will be in
the low voltage state. In other words, the connection performs an OR function in which logic 1
wins.
Assume that 2 devices, A and B having ID numbers 5 and 6 respectively, are requesting the
use of the bus. Device A transmits the pattern 0101, and device B transmits the pattern 0110. The
code seen by both devices is 0111. Each device compares the pattern on the arbitration lines to
its own ID, starting from most significant bit if it detects a difference at any position; it disables
its drivers at that bit position and for all lower order bits. It does so by placing at the input of
these drivers.

2.7 Buses
 Processor, main memory, and I/O devices are interconnected by means of a bus.
 Bus provides a communication path for the transfer of data.
 Bus also includes lines to support interrupts and arbitration.
 A bus protocol is the set of rules that govern the behavior of various devices connected to
the bus, as to when to place information on the bus, when to assert control signals, etc.
Bus lines may be grouped into three types:
 Data
 Address
 Control
Control signals specify: Whether it is a read or a write operation. Required size of the data, when
several operand sizes (byte, word, long word) are possible. Timing information to indicate when
the processor and I/O devices may place data or receive data from the bus. Schemes for timing of
data transfers over a bus can be classified into:
i. Synchronous,
ii. Asynchronous.

i. Synchronous Bus
• In case of a Write operation, the master places the data on the bus along with the address
and commands at time t0.
• The slave strobes the data into its input buffer at time t2.
• Once the master places the device address and command on the bus, it takes time for this
information to propagate to the devices:
• This time depends on the physical and electrical characteristics of the bus.

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Figure: Timing of an input transfer on a synchronous bus

• Also, all the devices have to be given enough time to decode the address and control
signals, so that the addressed slave can place data on the bus.
• Width of the pulse t1 - t0 depends on:
i. Maximum propagation delay between two devices connected to the bus.
ii. Time taken by all the devices to decode the address and control signals, so that the
addressed slave can respond at time t1.
iii. At the end of the clock cycle, at time t2, the master strobes the data on the data
lines into its input buffer if it’s a Read operation.
iv. “Strobe” means to capture the values of the data and store them into a buffer.

Figure: A detailed timing diagram for the input transfer

v. When data are to be loaded into a storage buffer register, the data should be available
for a period longer than the setup time of the device.
vi. Width of the pulse t2 - t1 should be longer than:
vii. Maximum propagation time of the bus plus
viii. Set up time of the input buffer register of the master.

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• Signals do not appear on the bus as soon as they are placed on the bus, due to the
propagation delay in the interface circuits.
• Signals reach the devices after a propagation delay which depends on the characteristics
of the bus.
• Data must remain on the bus for some time after t2 equal to the hold time of the buffer.
• Data transfer has to be completed within one clock cycle.
• Clock period t2 - t0 must be such that the longest propagation delay on the bus
and the slowest device interface must be accommodated.
• Forces all the devices to operate at the speed of the slowest device.
• Processor just assumes that the data are available at t2 in case of a Read operation, or are
read by the device in case of a Write operation.
What if the device is actually failed, and never really responded?
• Most buses have control signals to represent a response from the slave.
• Control signals serve two purposes:
• Inform the master that the slave has recognized the address, and is ready to participate in
a data transfer operation.
• Enable to adjust the duration of the data transfer operation based on the speed of the
participating slaves.
• High-frequency bus clock is used: Data transfer spans several clock cycles instead of just
one clock cycle as in the earlier case.
Multiple Cycle Transfer

Figure: An input transfer using multiple clock cycles

Transfer has to be completed within one clock cycle, the clock period t 2-t0, must be chosen to
accommodate the longest delays on the bus and the slowest device interface. This forces all
devices to operate at the speed of the slowest device.

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The processor has no way of determining whether the addressed device has actually
responded. It simply assumes that at t2, the output data have been received by the I/O device or
the input data are available on the data lines. If, because of a malfunction, the device does not
respond, the error will not be detected.
To overcome these limitations, most buses incorporate control signals that represent a response
from the device. These signals inform the master that the slave has recognized its address and
that it is ready to participate in a data-transfer operation.
During clock cycle 1, the master sends address and command information on the bus,
requesting a read operation. The slave receives this information and decodes it. On the following
active edge of the clock, ie., at the beginning of clock cycle 2, it makes a decision to respond and
begins to access the requested data.

ii. Asynchronous Bus

• Data transfers on the bus are controlled by a handshake between the master and the slave.
• Common clock in the synchronous bus case is replaced by two timing control lines:
 Master-ready,
 Slave-ready.
• Master-ready signal is asserted by the master to indicate to the slave that it is ready to
participate in a data transfer.
• Slave-ready signal is asserted by the slave in response to the master-ready from the
master, and it indicates to the master that the slave is ready to participate in a data
transfer.
• Data transfer using the handshake protocol:
 Master places the address and command information on the bus.

T ime

Figure: Handshake control of data transfer during an input operation

 Asserts the Master-ready signal to indicate to the slaves that the address and
command information has been placed on the bus.
 All devices on the bus decode the address.

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 Address slave performs the required operation, and informs the processor it has done
so by asserting the Slave-ready signal.
 Master removes all the signals from the bus, once Slave-ready is asserted.
 If the operation is a Read operation, Master also strobes the data into its input buffer.

t0 - Master places the address and command information on the bus.

t1 - Master asserts the Master-ready signal. Master-ready signal is asserted at t1 instead of t0
t2 - Addressed slave places the data on the bus and asserts the Slave-ready signal.
t3 - Slave-ready signal arrives at the master.
t4 - Master removes the address and command information.
t5 - Slave receives the transition of the Master-ready signal from 1 to 0. It removes the data and
the Slave-ready signal from the bus.

 Advantages of asynchronous bus:

• Eliminates the need for synchronization between the sender and the receiver.
• Can accommodate varying delays automatically, using the Slave-ready signal.
 Disadvantages of asynchronous bus:
• Data transfer rate with full handshake is limited by two-round trip delays.
• A data transfer using a synchronous bus involves only one round trip delay, and
hence a synchronous bus can achieve faster rates.

2.8 Interface Circuits

 I/O interface consists of the circuitry required to connect an I/O device to a computer bus.
 Side of the interface which connects to the computer has bus signals for:
• Address,
• Data
• Control
 Side of the interface which connects to the I/O device has: Datapath and associated controls
to transfer data between the interface and the I/O device. This side is called as a “port”.
 Ports can be classified into two:
• Parallel port,
• Serial port.
 Parallel port transfers data in the form of a number of bits, normally 8 or 16 to or from the
device.
 Serial port transfers and receives data one bit at a time.
 Processor communicates with the bus in the same way, whether it is a parallel port or a serial
port.
• Conversion from the parallel to serial and vice versa takes place inside the interface
circuit.
Parallel port
• Keyboard is connected to a processor using a parallel port.

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• Processor is 32-bits and uses memory-mapped I/O and the asynchronous bus protocol.
• On the processor side of the interface we have:
 Data lines.
 Address lines

Data
Address DATAIN Data
Encoder
R/W SIN and Keyboard
Processor debouncing switches
Master
-ready circuit
Input Valid
Slave-ready interface
Figure: Keyboard to processor connection

 Control or R/W line.

 Master-ready signal and
 Slave-ready signal.
• On the keyboard side of the interface:
o Encoder circuit which generates a code for the key pressed.
o Debouncing circuit which eliminates the effect of a key bounce (a single key
stroke may appear as multiple events to a processor).
o Data lines contain the code for the key.
o Valid line changes from 0 to 1 when the key is pressed. This causes the code to be
loaded into DATAIN and SIN to be set to 1.

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Figure: Input interface circuit

• Output lines of DATAIN are connected to the data lines of the bus by means of 3 state
drivers
• Drivers are turned on when the processor issues a read signal and the address selects this
register.
• SIN signal is generated using a status flag circuit.
• It is connected to line D0 of the processor bus using a three-state driver.
• Address decoder selects the input interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when Master-ready is
active.
• In response, the processor activates the Slave-ready signal, when either the Read-status or
Read-data is equal to 1, which depends on line A0.
Data
Address DATAOUT Data
Processor
CPU R/W SOUT Valid Printer
Master-ready
Output Idle
Slave-ready interface
Figure: Printer to processor connection

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• Printer is connected to a processor using a parallel port.
• Processor is 32 bits, uses memory-mapped I/O and asynchronous bus protocol.
• The printer operates under the control of the handshake signals Valid and Idle in a
manner similar to the handshake used on the bus with the Master-ready and Slave-ready
signals.
• When it is ready accept character, the printer asserts its idle signal. The interface circuit
can then place a new character on the data lines and activate the valid signal.
• The interface contains a data register, DATAOUT, and a status flag, SOUT.
• The SOUT flag is set to 1 when the printer is ready to accept another character, and it is
cleared to 0 when a new character is loaded into DATAOUT by the processor.

Figure: Output interface circuit

• Data lines of the processor bus are connected to the DATAOUT register of the interface.
• The status flag SOUT is connected to the data line D1 using a three-state driver.
• The three-state driver is turned on, when the control Read-status line is 1.
• Address decoder selects the output interface using address lines A1 through A31.
• Address line A0 determines whether the data is to be loaded into the DATAOUT register
or status flag is to be read.

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• If the Load-data line is 1, then the Valid line is set to 1.
• If the Idle line is 1, then the status flag SOUT is set to 1.

Bus
D7 PA7

DATAIN
D1
D0 PA0
SIN
Input CA
status

PB7

DATAOUT

PB0
SOUT
Handshake CB1
control CB2
Slave- 1
Ready

Master-
Ready
R/ W
A31
Address My-address
decoder
A2
RS1
A1

RS0
A0

Figure: Combined input/output interface circuit

• Combined I/O interface circuit. Address bits A2 through A31 that is 30 bits are used to
select the overall interface.
• Address bits A1 through A0, that is, 2 bits select one of the three registers, namely,
DATAIN, DATAOUT, and the status register.
• Status register contains the flags SIN and SOUT in bits 0 and 1.
• Data lines PA0 through PA7 connect the input device to the DATAIN register.
• DATAOUT register connects the data lines on the processor bus to lines PB0 through
PB7 which connect to the output device.
• Separate input and output data lines for connection to an I/O device.

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Figure: A general 8-bit parallel interface

• Data lines to I/O device are bidirectional.
• Data lines P7 through P0 can be used for both input, and output.
• In fact, some lines can be used for input & some for output depending on the pattern in
the Data Direction Register (DDR).
• Processor places an 8-bit pattern into a DDR.
• If a given bit position in the DDR is 1, the corresponding data line acts as an output line,
and otherwise it acts as an input line.
• C1 and C2 control the interaction between the interface circuit and the I/O devices.
• Ready and Accept lines are the handshake control lines on the processor bus side, and are
connected to Master-ready & Slave-ready.
• Input signal My-address is connected to the output of an address decoder.
• Three register select lines that allow up to 8 registers to be selected.

Serial port
• Input shift register accepts input one bit at a time from the I/O device.
• Once all the 8 bits are received, the contents of the input shift register are loaded in
parallel into DATAIN register.
• Output data in the DATAOUT register are loaded into the output shift register.
Bits are shifted out of the o/p shift register and sent out to the I/O device one bit at a time.

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Figure: A serial interface

• As soon as data from the input shift register are loaded into DATAIN, it can start
accepting another 8 bits of data.
• Input shift register and DATAIN registers are both used at input so that the input shift
register can start receiving another set of 8 bits from the input device after loading the
contents to DATAIN, before the processor reads the contents of DATAIN. This is called
as double-buffering.
• Serial interfaces require fewer wires, and hence serial transmission is convenient for
connecting devices that are physically distant from the computer.
• Speed of transmission of the data over a serial interface is known as the “bit rate”.
 Bit rate depends on the nature of the devices connected.
• In order to accommodate devices with a range of speeds, a serial interface must be able to
use a range of clock speeds.
• Several standard serial interfaces have been developed:
 Universal Asynchronous Receiver Transmitter (UART) for low-speed serial
devices.
 RS-232-C for connection to communication links.

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2.9 Standard I/O Interface

• I/O device is connected to a computer using an interface circuit.
• We require different interface for every combination of an I/O device and a computer.
• A practical approach is to develop standard interfaces and protocols.
• A personal computer has: A motherboard which houses the processor chip, main
memory and some I/O interfaces. A few connectors into which additional interfaces can
be plugged.
• Processor bus is defined by the signals on the processor chip. Devices which require
high-speed connection to the processor are connected directly to this bus.
• Because of electrical reasons only a few devices can be connected directly to the
processor bus. Motherboard usually provides another bus that can support more devices.
o Processor bus and the other bus are interconnected by a circuit called “bridge”.
o Devices connected to the expansion bus experience a small delay in data transfers.
• Design of a processor bus is closely tied to the architecture of the processor.
o No uniform standard can be defined.
• Expansion bus however can have uniform standard defined.
• A number of standards have been developed for the expansion bus.
o Some have evolved by default.
o For example, IBM’s Industry Standard Architecture.
• Three widely used bus standards:
i. PCI (Peripheral Component Interconnect)
ii. SCSI (Small Computer System Interface)
iii. USB (Universal Serial Bus)

Interface
Figure: An example computer system using different interface standards
2.9.1 Peripheral Component Interconnect (PCI) Bus
The PCI (Peripheral Component Interconnect) bus was developed as a low-cost, processor-
independent bus. It is housed on the motherboard of a computer and used to connect I/O
interfaces for a wide variety of devices. A device connected to the PCI bus appears to the
processor as if it is connected directly to the processor bus. Its interface registers are assigned
addresses in the address space of the processor. We will start by describing how the PCI bus
operates, then discuss some of its features.

Bus Structure
The use of the PCI bus in a computer system is illustrated in figure. The PCI bus is connected to
the processor bus via a controller called a bridge. The bridge has a special port for connecting the
computer’s main memory. It may also have another special high speed port for connecting
graphics devices. The bridge translates and relays commands and responses from one bus to the
other and transfers data between them.

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Figure: Use of PCI bus in a Computer System

When the processor sends a Read request to an I/O device, the bridge forwards the command
and address to the PCI bus. When the bridge receives the device’s response, it forwards the data
to the processor using the processor bus. I/O devices are connected to the PCI bus, possibly
through ports that use standards such as Ethernet, USB, SATA, SCSI, or SAS.
The PCI bus supports three independent address spaces:
• Memory,
• I/O, And
• Configuration.
The system designer may choose to use memory-mapped I/O even with a processor that has a
separate I/O address space. In fact, this is the approach recommended by the PCI standard for
wider compatibility. The configuration space is intended to give the PCI its plug-and-play
capability, as we will explain shortly. A 4-bit command that accompanies the address identifies
which of the three spaces is being used in a given data transfer operation.
Data transfers on a computer bus often involve bursts of data rather than individual words.
Words stored in successive memory locations are transferred directly between the memory and
an I/O device such as a disk or an Ethernet connection.
Data transfers are initiated by the interface of the I/O device, which acts as a bus master. This
way of transferring data directly between the memory and I/O devices wıll be discussed later.
The PCI bus is designed primarily to support multiple-word transfers. A Read or a Write
operation involving a single word is simply treated as a burst of length one.

Table: Data transfer signals on the PCI bus

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We will examine a typical bus transaction. The bus master, which is the device that initiates
data transfers by issuing Read and Write commands, is called the initiator in PCI terminology.
The addressed device that responds to these commands is called a target. The main bus signals
used for transferring data are listed in Table.
There are 32 or 64 lines that carry address and data using a synchronous signaling scheme.
The target-ready, TRDY#, signal is equivalent to the Slave-ready signal. In addition, PCI uses an
initiator-ready signal, IRDY#, to support burst transfers. A complete transfer operation on the
PCI bus, involving an address and a burst of data, is called a transaction. Individual word
transfers within a transaction are called phases.

The read operation of PCI bus

Consider a bus transaction in which an initiator reads four consecutive 32-bit words from the
memory. A clock signal provides the timing reference used to coordinate difference phases of a
transaction. All signal transactions are triggered by the rising edge of the clock.
In clock cycle 1,
 the processor asserts FRAME# to indicate the beginning of a transaction.
 sends the address on the AD lines and a command on the C/BE# lines.
Clock cycle 2 is used to turn the AD bus lines around.
The processor removes the address and disconnects its drivers from the AD lines.
Selected target: enables its drivers on the AD lines and
Fetches the requested data to be placed on bus.
Selected target: asserts DEVSEL# and
Maintains it in asserted state until the end of the transaction.
C/BE# is: Used to send a bus command and it is
Used for different purpose during the rest of the transaction.

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Figure: Read Operation on the PCI bus

During Clock cycle-3
The initiator asserts IRDY# to indicate that it is ready to receive data.
If the target has data ready to send then it asserts TRDY#. In our eg. The target sends 3 more
words of data in clock cycle 4 to 6.
During clock cycle-5
The indicator uses FRAME# to indicate the duration of the burst, since it read 4 words, the
initator negates FRAME# during clock cycle 5.
During clock cycle-7 After sending 4th word, the target
Disconnects its drivers and negates DEVSEL# during clock cycle 7.

Device Configuration of PCI

The PCI has a configuration ROM that stores information about that device.
• The configuration ROM’s of all devices are accessible in the configuration address-space.
• The initialization software read these ROM’s whenever the system is powered up or reset.
• In each case, it determines whether the device is a printer, keyboard or disk controller.
• Devices are assigned address during initialization process.
• Each device has an input signal called IDSEL# (Initialization device select) which has 21
address- lines (AD11 to AD31).
• During configuration operation,
 The address is applied to AD input of the device and
The corresponding AD line is set to 1 and all other lines are set to 0.
AD11 - AD31 Upper address-line
A0 - A10 Lower address-line:
Specify the type of the operation and to access the content of device configuration ROM.

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• The configuration software scans all 21 locations. PCI bus has interrupt-request lines.
• Each device may requests an address in the I/O space or memory space

2.9.2 SCSI Bus (Small Computer System Interface)

• SCSI refers to the standard bus which is defined by ANSI (American National Standard
Institute).
• SCSI bus the several options. It may be,
Narrow bus It has 8 data-lines & transfers 1 byte at a time.
Wide bus It has 16 data-lines & transfer 2 byte at a time.
Single-Ended Transmission Single-Ended Transmission Each signal uses separate wire.
HVD(High Voltage Differential) It was 5v (TTL cells)
LVD (Low Voltage Differential) It uses 3.3v

• Because of these various options, SCSI connector may have 50, 68 or 80 pins. The data transfer
rate ranges from 5MB/s to 160MB/s 320Mb/s, 640MB/s. The transfer rate depends on,
 Length of the cable
 Number of devices connected.
• To achieve high transfer rate, the bus length should be 1.6m for SE signaling and 12m for LVD
signaling.
• The SCSI bus us connected to the processor-bus through the SCSI controller. The data are
stored on a disk in blocks called sectors. Each sector contains several hundreds of bytes. These
data will not be stored in contiguous memory-location.
• SCSI protocol is designed to retrieve the data in the first sector or any other selected sectors. •
Using SCSI protocol, the burst of data are transferred at high speed.
• The controller connected to SCSI bus is of 2 types. They are Initiator &Target
1) Initiator: It has the ability to select a particular target & to send commands specifying the
operation to be performed. They are the controllers on the processor side.
2) Target : The disk controller operates as a target. It carries out the commands it receive from
the initiator. The initiator establishes a logical connection with the intended target.
Steps for Read-operation
i. The SCSI controller contends for control of the bus (initiator).
ii. When the initiator wins the arbitration-process, the initiator
→ selects the target controller and hands over control of the bus to it.
iii. The target starts an output operation. The initiator sends a command specifying the
required read- operation.
iv. The target ends a message to initiator indicating that it will temporarily suspend
connection b/w them and then releases the bus.
v. The target controller sends a command to the disk drive to move the read head to the first
sector involved in the requested read-operation.
vi. The target → transfers the contents of the data buffer to the initiator and → then
suspends the connection again.
vii. The target controller sends a command to the disk drive to perform another seek
operation.

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viii. As the initiator controller receives the data, it stores them into the main-memory using
the DMA approach.
ix. The SCSI controller sends an interrupt to the processor indicating that the data are now
available.

BUS Signals of SCSI

• The bus has no address-lines. Instead, it has data-lines to identify the bus-controllers involved
in the selection/reselection/arbitration-process.
• For narrow bus, there are 8 possible controllers numbered from 0 to 7. For a wide bus, there are
16 controllers.
• Once a connection is established b/w two controllers, there is no further need for addressing &
the data-lines are used to carry the data.

Table: The SCSI Bus signal

Category Name Function
Data -DB(0) to –DB(7) Data lines: Carry one byte of informtion during the
-DB(P) information trnsfer phase & identify device during
arbitration, selection & reselection phase.
Parity bit: for the data bus.
Phase -BSY Busy: Asserted when he bus is not free
-SEL Selection: Asserted during selection & reselection.
Information -C/D Control/Data: Asserted during transfer of control
type -MSG information.
Message: Indiactes that the information being
transferred is a message
Handshake -REQ Request: Asserted by a target to represent a data
-ACK transfer cycle.
Acknowledge: Asserted by the initiator when it has
completed a data transfer operation
Direction of -I/O Input/Output: Asserted to indicate an input
transfer operation
Other -ATN Attention: Asserted by an initiator when it wishes to
-RST send a message to a target.
Reset: Causes all device controls to disconnect from
the bus & assume their start-up state
• All signal names are postponed bu minus sign.
• This indicates that the signals are active or that the data line is equal to 1, when they are
low voltage state.

PHASES IN SCSI BUS

• The phases in SCSI bus operation are:
1) Arbitration

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2) Selection
3) Information transfer
4) Reselection
1) Arbitration
• When the –BSY signal is in inactive state,
→ the bus will be free &
→ any controller can request the use of bus.
• SCSI uses distributed arbitration scheme because each controller may generate requests at the
same time.
• Each controller on the bus is assigned a fixed priority.
• When –BSY becomes active, all controllers that are requesting the bus
→ examines the data-lines &
→ determine whether highest priority device is requesting bus at the same time.
• The controller using the highest numbered line realizes that it has won the arbitration-process.
• At that time, all other controllers disconnect from the bus & wait for –BSY to become inactive
again.

Targets examine ID

DB2

DB5

DB6

BSY

SEL

Free Arbitration Selection

Figure: Arbitration and Selection on the SCSI bus. Device 6 wins arbitration and selects device 2.

2) Information Transfer
The information transferred between two controllerss may consists of
• Commands from the initiator to the target
• Status responses from the target to the initiator or
• Data transferred to/from the I/O device.
Handshake signalling is used to control information transfers, with the target controller taking
the role of the bus-master.

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3) Selection:
Here, device wins arbitration and
Asserts –BSY & -DB6 signals
The select Target controller responds by asserting –BSY.
This information that the connection that it requested is established.
4) Reselection
The Connection between the two controllers has been reestalished, with the target in control of
the bus are required for data transfer to proceed.

2.9.3 USB (Universal Serial Bus)

USB supports 3 speed of operation. They are,
i. Low speed (1.5 Mbps)
ii. Full speed (12Mbps) &
iii. High speed (480Mbps).

The USB has been designed to meet the key objectives. They are
1) Provide a simple, low-cost and easy to use interconnection system.
This overcomes difficulties due to the limited number of I/O ports available on a computer.
2) Accommodate a wide range of data transfer characteristics for I/O devices.
For e.g. telephone and Internet connections
3) Enhance user convenience through a “plug-and-play” mode of operation.
• Advantage: USB helps to add many devices to a computer system at any time without opening
the computer-box.
Port Limitation
 Normally, the system has a few limited ports.
 To add new ports, the user must open the computer-box to gain access to the internal
expansion bus & install a new interface card.
 The user may also need to know to configure the device & the s/w.

Plug & Play
The main objective: USB provides a plug & play capability.
The plug & play feature enhances the connection of new device at any time, while the system is
operation. The system should
→ Detect the existence of the new device automatically.
→ Identify the appropriate device driver s/w.
→ Establish the appropriate addresses.
→ Establish the logical connection for communication.

DEVICE CHARACTERISTICS OF USB

• The kinds of devices that may be connected to a computer cover a wide range of functionality.

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• The speed, volume & timing constrains associated with data transfer to & from devices varies
significantly.
Eg: 1 Keyboard
 Since the event of pressing a key is not synchronized to any other event in a computer
system, the data generated by keyboard are called asynchronous.
 The data generated from keyboard depends upon the speed of the human operator which
is about 100 bytes/sec.
Eg: 2 Microphone attached in a computer system internally/externally
 The sound picked up by the microphone produces an analog electric signal, which must
be converted into digital form before it can be handled by the computer.
 This is accomplished by sampling the analog signal periodically.
 The sampling process yields a continuous stream of digitized samples that arrive at
regular intervals, synchronized with the sampling clock. Such a stream is called
isochronous (i.e.) successive events are separated by equal period of time.
 If the sampling rate in „S‟ samples/sec then the maximum frequency captured by
sampling process is s/2. A standard rate for digital sound is 44.1 KHz.

USB Architecture
• To accommodate a large number of devices that can be added or removed at any time, the USB
has the tree structure as shown in the figure 7.17.
• Each node of the tree has a device called a Hub.
• A hub acts as an intermediate control point between the host and the I/O devices.
• At the root of the tree, a Root Hub connects the entire tree to the host computer.
• The leaves of the tree are the I/O devices being served (for example, keyboard or speaker).
• A hub copies a message that it receives from its upstream connection to all its downstream
ports.
• As a result, a message sent by the host computer is broadcast to all I/O devices, but only the
addressed-device will respond to that message.

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uter
Host comp
Rhouobt

Hub
Hub
dIev/O
ice
dIev/O
ice
dIev/O
ice
dIev/O
ice
Hub

dIev/O
ice
dIev/O
ice

Figure: Universal Serial Bus tree Structure

USB ADDRESSING
• Each device may be a hub or an I/O device.
• Each device on the USB is assigned a 7‐bit address.
• This address → is local to the USB tree and
→ is not related in any way to the addresses used on the processor-bus.
• A hub may have any number of devices or other hubs connected to it, and addresses are
assigned arbitrarily.
• When a device is first connected to a hub, or when it is powered-on, it has the address 0.
• The hardware of the hub detects the device that has been connected, and it records this fact as
part of its own status information.
• Periodically, the host polls each hub to collect status information and learn about new devices
that may have been added or disconnected.
• When the host is informed that a new device has been connected, it uses sequence of
commands to
 Send a reset signal on the corresponding hub port.
 Read information from the device about its capabilities.
 Send configuration information to the device, and
 Assign the device a unique USB address.
• Once this sequence is completed, the device
→ begins normal operation and
→ responds only to the new address.

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Computer Organization Notes (15CS34) 2017

USB PROTOCOLS
• All information transferred over the USB is organized in packets.
• A packet consists of one or more bytes of information.
• There are many types of packets that perform a variety of control functions.
• The information transferred on USB is divided into 2 broad categories: 1) Control and 2) Data.

Control packets used for controlling data transfer operations are called token
packets.
Figure : USB Packet format
• Control packets perform tasks such as
→ addressing a device to initiate data transfer.
→ acknowledging that data have been received correctly or
→ indicating an error.
• Data-packets carry information that is delivered to a device.
• A packet consists of one or more fields containing different kinds of information.
• The first field of any packet is called the Packet Identifier (PID) which identifies type of that
packet.
• They are transmitted twice.
1) The first time they are sent with their true values and
2) The second time with each bit complemented.
• The four PID bits identify one of 16 different packet types.
• Some control packets, such as ACK (Acknowledge), consist only of the PID byte.
• Control packets used for controlling data transfer operations are called Token Packets.

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