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Unit : Microprocessor 8086 and Modern Microprocessor

Microprocessor Year of Word Memory Pins Clock Remarks

Invention Length addressing
Capacity

4004 1971 4-bit 1 KB 16 750 First Microprocessor

KHz

8085 1976 8-bit 64 KB 40 3-6 Popular 8-

MHz bit Microprocessor

8086 1978 16-bit 1MB 40 5-8 Widely used in PC/XT

MHz

80286 1982 16-bit 16MB real, 4 GB 68 6-12.5 Widely used in

virtual MHz PC/AT

80386 1985 32-bit 4GB real, 64TB 132 20-33 Contains MMU on
virtual 14X14 MHz chip
PGA

80486 1989 32-bit 4GB real, 64TB 168 25-100 Contains MMU,
virtual 17X17 MHz cache and FPU, 1.2
PGA million transistors

Pentium 1993 32-bit 4GB real,32-bit 237 60-200 Contains 2 ALUs,2

address,64-bit PGA Caches, FPU,
data bus 3.3 Million
transistors,
3.3 V, 7.5 million
transistors

Pentium Pro 1995 32-bit 64GB real, 36- 387 150- It is a data flow
bit address bus PGA 200 processor. It contains
MHz second level cache
also,3.3 V

Pentium II 1997 32-bit - - 233- All features Pentium

400 pro plus MMX
MHz technology,3.3 V, 7.5
million transistors
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Pentium III 1999 32-bit 64GB 370 600-1.3 Improved version of

PGA MHz Pentium II; 70 new
SIMD instructions

Pentium 4 2000 32-bit 64GB 423 600-1.3 Improved version of

PGA GHz Pentium III

Itanium 2001 64-bit 64 address 423 733 64-bit EPIC Processor

lines PGA MHz-
1.3 GHz

Evolution of Microprocessors

First Generation (4 - bit Microprocessors)

Intel 4004

Second Generation (8 - bit Microprocessor)

Intel 8008

Third Generation (16 - bit Microprocessor)

Intel's 8086, Zilog Z800 and 80286,

Fourth Generation (32 - bit Microprocessors)

Intel 80386.
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Working of a Microprocessor
There are three steps that a microprocessor follows –

1. Fetch – The instructions are in storage from where the processor fetches them.
2. Decode – It then decodes the instruction to assign the task further.
3. Execute – The assigned tasks undergo execution and reach the output port
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8086

The third generation microprocessors,

Introduced in 1978
16 - Bit processors with a performance like minicomputers.

FEATURES OF 8086
It requires +5v power supply.

It has 20 bit address bus, can access 220 =1MB memory location.

16 bit data bus.

It is a 16 bit processor having 16 bit ALU, 16 bit registers.

It has instruction queue which is capable of storing 6 instruction bytes from the
memory for faster processing.

It has pipelining, fetch and executes stage for improving performance..

Clock range is 5-10 MHz

CONCEPT OF PIPELINING
▪ Fetching the next instruction while the current instruction executes is known as pipelining
▪ it means When first instruction is getting executed, second one is decoded and third instruction code is
fetched from memory.
▪ It improves speed of operation to great extent.
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▪ The Bus Interface Unit(BIU) fetches as many as 6 instruction bytes ahead of time from the memory and
these are held for execution unit in the (FIFO) group of registers called QUEUE.

▪ When the EU is ready for the next instruction, it simply reads the instruction from the QUEUE in the BIU.

PHYSICAL ADDRESS GENERATION IN 8086

Logical address of 2 types :

● Segment address: It indicates start of Segment.

● Offset address / Effective address : It indicates size of Segment.

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To get total physical address, put the lower nibble 0H to segment address and add offset address

Physical address = Segment address *10H + Offset address

Calculate the physical address for the given CS=3420H, IP=689AH

.
CS=3420H
IP=689AH
Zero is inserted
34200
+ 689A
-----------------------------------------------------------
=3AA9A
Architecture of
8086
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Draw 8086 architecture block diagram and state the functions of EU and BIU
 Main components of BIU ( Bus interface Unit )
1) Address generation Unit :
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Physical address = Segment address *10H + Offset address
2) Segment Registers :

1 CS Register Hold the segment address of Code Segment

2 DS Register Hold the segment address of Data Segment
3 SS Register Hold the segment address of Stack Segment
4 ES Register Hold the segment address of Extra Segment

3) 6 Byte Pre-Fetch Queue:

Woks on the principle of Frist in Frist out

Function s of BIU:

• It provides interface of 8086 to external memory and input output devices

• Fetches instructions from memory

• It generates the 20 bit physical address.

Main components of EU:(Execution Unit )

1) General purpose Register:

8086 has 4 16-bit genral purpose register

AX, BX, CX, DX

2) ALU :

It has 16 bit ALU

It performs 8 and 16 bit arithmetic and logical operations

3) Flag Registers

Status flags e.g. Carry Flag

Controls Flags eg.Trap flag

 Function s of EU:

• ` It fetches Instructions from Queue in BIU

• Decodes instructions

• Executes instructions

• It performs arithmetic, logic operations.

FLAG REGISTER

Microprocessor 8086 has 16 bit flag register among which 9 bitsare active.

The purpose of flag register is to indicate the status of the processor Depending upon the value of result after any arithmetic and logical operation the flag

bits become set (1) or reset (0).

STATUS FLAG

1. Carry Flag (CF): Set 1 if there is carry out of MSB position.

2. Auxiliary Flag (AF): Set 1 if carry from lower nibble to upper nibble.

3. Parity Flag (PF): Set 1 if operation contains even number.

4. Zero Flag (ZF): Set 1 if result of arithmetic or logical operation is zero.

5. Sign Flag (SF): Set 1 if result of operation is negative.

6. Overflow Flag (OF): Set 1 if result is too large to fit in the numbers bits available to

accommodate it.
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CONTROL FLAGS
Trap flag:
When it is set Single steeping mode is enabled.

Interrupt Enable Flag:

When IF is set INTR interrupt is enabled.

Direction Flag:
When it is set, Pointer is in auto decrementing mode in string operations otherwise it is auto incrementing

Difference between RISC AND CISC

RISC : Reduced instruction set computer
CISC: Complex instruction set computer

RISC CISC
1 Uses simple instruction Uses Complex instruction
2 Uses simple addressing mode Uses complex addressing mode
3 Uses instruction of same size Uses instruction of variable size
4 Execution time is almost same for all instruction Execution time is variable as per instruction size
5 Compiler design is simple Compiler design is complex
6 More register-oriented instruction More memory-oriented instruction
7 Total size of program is large Total size of program is small

Compare 8086 and 80586 (Pentium)

SR. NO 80586 Pentium II Pentium III

PARAMETER 8086
(Pentium I)
 1. Data Bus 16 bit 64 bit 64 bit 64 bit
2 Address Bus 20 bit 32 bit 36 bit 36 bit
` 3 Physical memory 1 MB 4 GB 64 GB 64 GB
4 Processor size 16 bit 32 bit 32 bit 32 bit
5 Voltage required 5V 3.3 V 3.3 V 3.3 V
6 Pipelining Yes Yes Yes Yes
7 Year of Realse 1978 1993 1997 1999

Define the following terms –

Physical Address The address given by BIU is 20 bit called as physical address. It is the actual address of the memory location accessed by the microprocessor.

Effective Address:

Effective address or the offset address is the offset for a memory operand. It is an unassigned 16 bit number that gives the operand's distance in bytes from the
beginning of the segment.

PIN DIAGRAM OF 8086

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AD0-AD15: Address/Data bus:

Carry Address and Data but not simultaneously

when ALE =1 carries A15-A0 : Address (These are low order address bus)
when ALE =0 carries D15 -D0: DATA

A16-A19 / S3 - S6
High order address bus.
These are multiplexed with status signals.
when ALE =1 carries A16-A19 : Address
when ALE =0 carries S3-S6 : Status signals

S4 S3 Function

Extra segment
0 0
access

Stack segment
0 1
access

Code segment
1 0
access
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Data segment
1 1
access

ALE : Address latch Enables

ALE is high : It indicates A15 -A 0 and A16 -A19

ALE is low : It indicates D15- D0 and S3-S6

RD’ :
This is used for read operation.
It is active when low

READY :
This is the acknowledgement from the memory or slow device that they have completed the data
transfer.
when it is high it indicates that devices are ready for data transfer
when it is low it indicates that devices are not ready for data transfer

INTR : Interrupt Request.

If any interrupt request is found pending, the processor enters the interrupt acknowledge cycle. .
This signal is active high(1)

MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.

when it is high ,8086 enters in Minimum mode

when it is low ,8086 enters in Maximum mode

CLK :
This is clock input line
8086 does not have on chip clock generator so that external clock is provided
Clock Frequency for different version of 8086 is from 5MHz to 10 MHz.

RESET:
IT is active high
When it goes high ,microprocessor resets and it clears the flag registers and instruction QUEUE .
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Vcc and GND :

Used for power supply .
Two grounds are due to two internal layers of microprocessor .