2023 IEEE International Conference on Sensors and Nanotechnology (SENNANO)

A Low Power Nonvolatile DRAM Cell based on

ReRAMs
Hock Leong Chee Wei Leong Wong T. Nandha Kumar
University of Nottingham Malaysia University of Nottingham Malaysia University of Nottingham Malaysia
Selangor, Malaysia Selangor, Malaysia Selangor, Malaysia
2023 IEEE International Conference on Sensors and Nanotechnology (SENNANO) | 979-8-3503-3331-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/SENNANO57767.2023.10352569

[email protected] [email protected] [email protected]

Haider A.F. Almurib

University of Nottingham Malaysia
Selangor, Malaysia
[email protected]

Abstract—A one transistor, one resistor, and one resistive makes the DRAM cell volatile and requires energy-
random-access-memory (ReRAM) (2T1R) nonvolatile-DRAM consuming refresh cycles during operation.
(nvDRAM) is presented in this work. By using the ReRAM as
the storage component, the 2T1R cell overcomes the problem Replacing the capacitor with a nonvolatile memory (NVM)
with capacitor scaling limitations, eliminates the need for device would provide a solution to the challenges above. The
periodic refresh, and achieves passive nonvolatility, negating the resistive-random-access-memory (ReRAM) is a next-
requirements for additional STORE/RESTORE operations generational NVM device that is two-terminal, consists of
after power disruption or when the DRAM is powered on. The three layers (metal-metal oxide-metal), and is backend-of-line
READ voltage scheme utilizes two pulses; a Read pulse followed (BeoL) fabrication compatible [3], [4]. As a memory device
by a Restore pulse to prevent resistance drift of the ReRAM. by itself, the ReRAM is capable of reaching or even bettering
The design is evaluated over simulations; successfully DRAM and Flash performances in terms of power
demonstrating nonvolatility and stored data stability during bit- consumption [5], endurance [6], and latency [7]. The ReRAM
flip operations. Standard performance metrics such as the is also able to scale beyond the expected limitations of
WRITE and READ delay, energy dissipation and EDP are then transistors [8] which capacitors are already lacking behind.
assessed over 22nm, 32nm, and 45nm transistor technology The nonvolatile DRAM (nvDRAM) should provide a next-
nodes. These measurements are then compared with existing generation version of the DRAM cell, providing nonvolatility
DRAM designs; the 2T1R cell has an average lower READ delay
together with RAM caching functionality to work together
by 4.6ps and an average higher WRITE delay by 8.78x103ps
with next-generational nvSRAMs that provide lower latency
which is limited by the ReRAM switching speed. The average
READ and WRITE energy dissipations of the 2T1R cell are
at the cost of increased cell footprint [9].
however lower by 1.19x103nJ and 1181.8nJ respectively. This is This paper therefore introduces a two transistor and one
attributed to the reduction in transistor counts in the 2T1R ReRAM (2T1R) nvDRAM cell architecture that offers a
design. The 2T1R cell also demonstrates an improvement in solution to conventional 1T1C DRAM scaling whilst
EDP over the compared DRAM designs. eliminating the need for energy-consuming refresh cycles by
making use of the ReRAM’s nonvolatility. The nvDRAM cell
Keywords—Dynamic-random-access-memory (DRAM), shows average WRITE and READ delays of 12.253ns and
electrical modelling, memory, nonvolatile memory, random- 0.2ns and average WRITE and READ energy dissipation of
access-memory (RAM), resistive-random-access-memory 5.65x104nJ and 1.91 x104 nJ respectively.
(ReRAM)
II. PRELIMINARIES
I. INTRODUCTION A. ReRAM
The advent of massive-scale data-intensive applications The ReRAM is a next-generation two-terminal NVM
from Internet-of-Things (IoT), Artificial Intelligence (AI), device [10], [11], [12] that functions through a physical
neural networks, cloud computing and its services, machine mechanism called resistive switching (RS), first described in
learning, and 21st century modern technology adoption [13]. To induce RS, voltage is applied across the ReRAM to
coupled with the increasing environmental awareness of switch its resistance between a High Resistance State (HRS)
modern society has led to the demand for more devices with and a Low Resistance State (LRS) [14], [15], [16]. In bipolar
higher computing power and increased energy consumption ReRAMs, this is achieved by changing the applied voltage’s
efficiency. polarity [17]. The ReRAM is scalable as the current
conduction mechanisms are localized in the TMO layer and
One of the limiting computing components in this regard are not affected by ReRAM thickness [18], [19]. This work
is the dynamic-random-access-memory (DRAM). The utilizes the ReRAM model from [20] with a LRS and HRS
DRAM which consists of an access transistor and a charge- resistance of 10kΩ and 1MΩ respectively.
storing capacitor (1T1C) in its most basic form is facing
massive scaling challenges with current feature sizes at B. Existing Nonvolatile DRAM Cells
>10nm, lagging behind processor fabrication processes [1]. A The nvDRAM cell has been previously proposed in [21],
major limiting factor is in the scaling of the capacitor; the [22], [23], [24]. In [21], a novel metal-ferroelectric-metal
capacitor’s aspect ratio is delicate and must be considered at (MFM) capacitor was proposed but ferroelectric materials
every reduction in size. Downsizing the capacitor also reduces experienced severe limitations in scaling. This was then
the cell capacitance, increasing charge leakage and variable improved on in [22] by using anti-ferroelectric materials. In
retention time (VRT) [2]. The capacitor’s charge leakage also [23] the capacitor is replaced by a nonvolatile phase-change
memory (PCM). The performance metrics of the proposed

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 DRAM storage components however lag behind ReRAMs
[23], [24], [25].
III. PROPOSED DESIGN
This section discusses the proposed nvDRAM design and
its electrical characteristics.
A. The ReRAM-based nvDRAM Fig. 1. 2T1R nvDRAM cell storing logical ‘1’ and ‘0’.
Fig. 1 shows the schematics of the proposed 2T1R cell
consisting of two access transistors and one ReRAM which is
the storage component.
The transistor, TW is the write access transistor and is
connected to the bitline, wordline, and node N. TW is switched
on during the WRITE sequence by the wordline voltage, WL
at its gate to form a path between the WRITE bitline voltage,
BL and node N. At the same time, the READ segment is left
floating and the voltage at N is the voltage flowing through Fig. 2. 2T1R nvDRAM READ1 and READ0 operation.
the ReRAM: TABLE I. READ VOLTAGES AND CYCLES TO FAILURE WITHOUT
RESTORE
(1) Read Read cycles to failure VOUT1
VOUT0F (mV)
Voltage (V) without Restore (mV)
The READ sequence is handled by the READ transistor, 0.4 66 267.619 313.747
TR which provides a dividing resistance and is connected to 0.6 56 401.102 471.162
the READ voltage line, RL and node N. This forms a simple 0.8 35 531.150 628.056
1 30 669.370 783.594
voltage divider at N and the value of TR has to be adjusted 1.2 26 805.339 937.015
depending on the ReRAM’s highest resistance to provide
accurate Boolean outputs during READ. Taking the voltage at For READ0, the ReRAM is in LRS (RLRS =10kΩ) and has
N and the output, VOUT during READ is given as: a much lower resistance than TR, therefore establishing a
current path from N to ground and VOUT levels drop to low
(2) (Fig. 2(b)).
In this work, a positive polarity VREAD is used to minimize
When the ReRAM is in HRS, RRERAM should be much external circuitry and wiring. This however, produces a
larger than TR (RRERAM >> TR) so that and positive current flow through the LRS-configured ReRAM
stored DATA1 is fed to the output. Alternatively, when the (DATA0) similar to the current flow during WRITE 1 (Fig.
ReRAM is in LRS, (TR >RRERAM) so that VOUT2 is a 1(a) and Fig. 2(b)), causing the ReRAM’s resistance to begin
fraction of VREAD and much lower than VOUT1 which is drifting to HRS. This eventually leads to a catastrophic
then read as stored DATA0 is at the output. resistance flip after multiple READ0 sequences.
The WRITE and READ operations of the nvDRAM are This is shown in Table I where simulation is carried out
shown in Fig. 1 and Fig. 2 and are described as follows: using repeated READ pulses without the Restore segment.
The ReRAM is switched to LRS (DATA0) then fed with 400
1) WRITE Operation READ pulses of differing READ voltage amplitudes. The
As shown in Fig. 1, the VREAD line is left floating during higher amplitudes lead to lower READ cycles-after-write
WRITE to remove the path from N through TR. The wordline before the ReRAM’s state variable drifts from its LRS state to
is set to high to turn on TW. This enables the bitline voltage to HRS. The nvDRAM cell’s output voltage at the point of
be driven to node N which will correspondingly determine the failure, VOUT0F is included and shows that it does not
resistance of the ReRAM. significantly differ from the output voltage of DATA1,
As the ReRAM is bipolar, the bitline voltage is positive VOUT1. Additionally, the VOUT1 in the table shows that the
polarity for WRITE 1 and switches the ReRAM from LRS to 1.2V READ voltage is desirable to maintain a high output
HRS (Fig. 1(a)). Alternatively WRITE 0 requires a negative voltage during READ1.
polarity Bitline voltage which switches the ReRAM from It is thus necessary to include a negative polarity Restore
HRS to LRS (Fig. 1(b)). The ReRAM’s resistance does not pulse after the Read pulse to recover the ReRAM’s resistance
change if it is already in HRS during WRITE 1 and LRS drift during READ0. This is incorporated into the design with
during WRITE 0. the READ operation pulse consisting of a 100ps, +1.2V Read
2) READ Operation pulse followed immediately by a 100ps, -1.2V Restore pulse.
For the READ operation, the wordline voltage is kept at 0 The reverse scenario for the HRS-configured ReRAM
to turn off TW and remove the connection between N and the (DATA1) during the negative Restore pulse is not a concern
bitline. VREAD is supplied and subsequently divided by both TR as the HRS resistance is large (in ~MΩ range) and the short
and the ReRAM’s resistance at N. If the ReRAM is in HRS duration of the Restore pulse is not sufficient to affect the
(stored DATA1), the ReRAM resistance is much higher than ReRAM. The WRITE and READ operations of the proposed
R1 (HRS resistance=1MΩ, TR = 275kΩ) and blocks the design happen passively and the high retention time of
current path to ground (Fig. 2(a)). The output voltage, VOUT is ReRAMs (~107 seconds [26]) provides a passive nonvolatile
around VREAD levels and is therefore high (1).

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 solution that eliminates the periodic refresh requirements and measurements for WRITE and READ delays, energy
endemic in conventional DRAMs. dissipation, and EDP parameters of the nvDRAM cell. The
results are then compared with existing DRAM cell
B. Electrical Characteristics architectures. The transistors used in the simulations are
Fig. 3 shows the simulated WRITE1 (dotted blue line) and predictive technology models (PTM) from [27].
WRITE0 (solid red line) operation waveforms for the 2T1R
cell. For WRITE1, a pulse-width of 10ns length and 1V Fig. 5 shows the simulation results for 0-to-1 and Fig. 6
amplitude is supplied to the bitline. The wordline is raised to shows the simulation for 1-to-0 tests. The ReRAM state
1V for the same duration to activate access transistor, TW. It variable in both simulations begin at an initial state and are
can be seen in Fig. 3 that the ReRAM state variable, which completely switched to either HRS or LRS before being
represents the ReRAM resistance switches accordingly from switched again to opposing states. For the 0-to-1 test, the
1 (LRS) to 0 (HRS). ReRAM completes a full switch from LRS to HRS and the
ReRAM completes a full switch from HRS to LRS for the 1-
A negative polarity pulse-width of 25ns length and -0.3V to-0 test. The length and amplitude of the WRITE pulse are
amplitude is supplied for WRITE0 operation (Fig. 3). In this properties. ReRAM switching speeds differ according to the
case the state variable of the ReRAM switches from 0 to 1 and material it is fabricated from and the nvDRAM operation
the ReRAM is in LRS. should be tuned appropriately.
The READ operation is demonstrated in Fig. 4. The output The nvDRAM WRITE and READ delays, energy
of the cell to the sense amplifiers, VOUT is provided during dissipation, and EDP for transistor technology nodes of 22nm,
the positive-polarity READ pulse. VOUT high is represented 32nm, and 45nm are then measured for the nvDRAM and
by the blue-dotted line while VOUT low is represented by the listed in Table II. Also included in the table are the parameters
solid red line. VOUT high (VOUT1) is around 1V and VOUT for existing DRAM architectures; namely, a three transistor,
low (VOUT2) is around 0V during the READ pulse. one gated diode (3T1D) cell [28], a boosted 3T1D (B3T) cell
The following negative polarity pulse-width is the Restore [29], a four transistor, one gated diode, one ReRAM
pulse to recover any resistance drift in the ReRAM during (4T1D1R) cell [24], and a four PMOS transistor, one gated
READ. All values at VOUT at this time should be diode, one ReRAM (4T1RP) cell [24]. The 2T1R cell has
disregarded. larger WRITE delays compared to the other designs due to the
switching timings of the ReRAM. This is a limitation of the
This way, the READ operation pulse is the same for both ReRAM used in this work and can be improved by using faster
READ0 and READ1 and both READs can be controlled by switching ReRAMs (ie. picoseconds switching ReRAM [30]).
the same singular external source circuit. The ReRAM state
variable shows that the ReRAM resistances are not affected However, the average WRITE energy dissipation is
by this READ scheme. calculated by taking each design’s average WRITE0 and
WRITE1 energy dissipation for every technology node and
shows that the 2T1R cell has an average of 1.19x103nJ lower
energy consumption than the compared DRAM cells. This
reduction in energy dissipation is a result of the use of a single
WRITE transistor in the 2T1R. The 2T1R cell is also
nonvolatile and forgoes the retention time criteria of the
compared designs. The 3T1D cell for example has a retention
time of 319.4ns for the 22nm technology node and has to be

Fig. 3. WRITE1 and WRITE0 operations of the 2T1R nvDRAM cell.

Fig. 5. Bit-flip 0-to-1 test of the 2T1R nvDRAM cell.

Fig. 4. READ1 and READ0 operations of the 2T1R nvDRAM cell.

IV. 2T1R NVDRAM ASSESSMENT

The proposed 2T1R cell is then tested for typical DRAM
performances as well as its nonvolatile characteristics with
simulations using LTSpice. The tests carried out are as
follows: Bit-flipping by using sequentially alternative WRITE Fig. 6. Bit-flip 1-to-0 test of the 2T1R nvDRAM cell.
operations to confirm complete ReRAM resistance switching

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 TABLE II. WRITE AND READ DELAY, ENERGY DISSIPATION, RETENTION TIME, AND EDP
Cell
Transistor 3T1D [28] B3T [29] 4T1D1R [24] 4T1RP [24] 2T1R [this work]
Node Operation Delay Energy EDP Retention Delay Energy EDP Retention Delay Energy EDP Retention Delay Energy EDP Retention Delay Energy EDP Retention
(nm) (ps) dissipation (ps∙nJ) Time (ps) dissipation (ps∙nJ) Time (ps) dissipation (ps∙nJ) Time (ps) dissipation (ps∙nJ) Time (ps) dissipation (ps∙nJ) Time
(nJ) (ns) (nJ) (ns) (nJ) (ns) (nJ) (ns) (nJ)
WRITE0 89.43 7.25e4 136.4 1.39e5 123.8 1.05e5 188.9 2.00e5 16637 6.53e-4 10.86
810.9 1016 845.9 1059
WRITE1 158.0 1.28e5 235.6 2.39e5 218.7 1.85e5 326.2 3.45e5 7633 3.54 e-4 2.704
319.4 362.7
READ0 172.1 1.51e5 165.3 1.57e5 175.7 1.61e5 169.3 1.67e5 200 1.66 e-4 3.3e-2
22 879.2 946.9 916.4 235.9 987.1 267.9 inf
READ1 213.9 1.88e5 162.4 1.54e5 224.7 2.06e5 164.0 1.62e5 200 2.10 e-4 4.2e-2
RESTORE0 - - - - - - - - 99.25 6.86e4 117.1 9.90e4 - - -
691.3 845.5
RESTORE1 - - - - - - - - 125.3 8.66e4 147.8 1.25e5 - - -
WRITE0 103.1 1.03e5 157.3 1.99e5 141.5 1.49e5 215.9 2.87e5 16640 7.17 e-4 11.92
1002 1265 1054 1331
WRITE1 171.6 1.72e5 255.9 3.24e5 235.5 2.48e5 351.2 4.67e5 7797 4.43 e-4 3.452
613.7 697.3
READ0 187.3 2.05e5 180.4 2.13e5 191.2 2.18e5 184.2 2.26e5 200 1.66 e-4 3.3e-2
32 1095 1179 1140 428.7 1227 486.9 inf
READ1 229.1 2.51e5 175.6 2.07e5 235.9 2.69e5 175.6 2.16e5 200 2.17 e-4 4.3e-2
RESTORE0 - - - - - - - - 99.25 8.64e4 136.3 1.45e5 - - -
870.1 1063
RESTORE1 - - - - - - - - 125.3 1.09e5 171.4 1.82e5 - - -
WRITE0 120.5 1.50e5 183.9 2.89e5 159.9 2.21e5 224.0 3.92e5 16651 7.78 e-4 12.96
1245 1573 1384 1748
WRITE1 189.1 2.35e5 282.0 4.44e5 250.9 3.47e5 374.2 6.54e5 8161 4.45 e-4 3.632
1112 1263
READ0 211.2 2.91e5 203.5 3.02e5 215.6 3.07e5 207.5 3.18e5 200 1.66 e-4 3.3e-2
45 1376 1482 1422 749.5 1531 851.2 inf
READ1 253.0 3.48e5 188.3 2.79e5 264.6 3.76e5 193.7 2.97e5 200 2.19 e-4 4.4e-2
RESTORE0 - - - - - - - - 117.6 1.20e5 156.0 1.95e5 - - -
1022 1249
RESTORE1 - - - - - - - - 148.4 1.52e5 196.9 2.46e5 - - -
‘-‘ indicates unused operations.

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