1382 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO.

4, APRIL 2020

1T-1C Dynamic Random Access Memory

Status, Challenges, and Prospects
Alessio Spessot and Hyungrock Oh
(Invited Paper)

Abstract — This article reviews the status, the challenges,

and the perspective of 1T-1C dynamic random access mem-
ory (DRAM) chip. The basic principles of the DRAM are
presented, introducing the key functional aspects and the
structure of modern devices. We present the most relevant
historical trends for different modules of the memory chip,
such as access device and storage element, reviewing some
of the technological challenges faced by industry to guaran-
tee the device shrinking imposed by the economic law. The
most recent solutions introduced by the industry in mod-
ern DRAM devices for the critical elements are presented.
Finally, a survey of the most critical bottleneck for future
development is presented, reviewing some of the potential
trends and perspectives of DRAM development.
Index Terms — 1T-1C, access device, dynamic random
access memory (DRAM) chips, DRAM, vertical transistor.
I. I NTRODUCTION

T HE concept of a one-transistor dynamic random access

memory (DRAM) obtained combining a simple tran-
sistor and a small capacitor was envisioned in 1966 by Fig. 1. (a) DRAM chip. array area, column decoder, and row decoder are
Dr. Robert Dennard, a Fellow at the IBM Thomas J. Watson visible. (b) Sketch of a memory array (MAT). WLs and BLs are connected
to SWDs and sense amplifier (S/A), respectively. (c) Basic schematic of
Research Center, Yorktown Heights, NY, USA [1]. Dennard the 1T-1C circuit. Gate of the access device is connected to the WL, while
and his team were working on early field-effect transistors and the source and drain terminals are connected to BL and capacitor. The
integrated circuits, and his attention to memory chips came most relevant bias is shown in blue. Adapted from [5] and [9].
from seeing another team’s research on thin-film magnetic
to its intrinsic simple nature, DRAM is particularly suitable
memory. Dennard claims he went home and started working
for scaling, and its excellent scalability contributed to its
on a simplified version of the memory, and in 1968, a patent
widespread success.
for DRAM was granted to Dennard and IBM [2].
Today, technological efforts are focusing on enabling further
In 1970, a newly formed company called Intel Corp, Moun-
cell area scaling. As the DRAM cell is reduced, innovations in
tain View, CA, USA, in 1968 (now headquartered in Santa
many technological aspects are getting more crucial than ever
Clara, CA, USA) publicly released 1103, the first DRAM chip
since we need to overcome the limits raising with the 10-nm
based on a 1-kb pMOS DRAM [3]. By 1972, it was the best
technology nodes and beyond [8].
selling semiconductor memory chip in the world, defeating the
An example of a modern DRAM chip is shown in Fig. 1(a),
magnetic core-type memory [4].
where the key functional elements of the memory are visible.
Nowadays, DRAM chips are widely used in electronic
This article is organized as follows. In Section II, we review
devices, thanks to high-speed operations, large integration
the key functional aspects of a DRAM cell. Section III reviews
density, and excellent reliability [5], [6]. In the past decades,
some of the most relevant historical trends and latest innova-
we have assisted in an exponential growth of the number of
tions, which serve as a basis to understand the key technical
memory cells per chip used. The major strategy to realize such
challenges that modern research has to tackle. In Section IV,
growth is the perpetual memory area cell scaling [7]. Due
we discuss some of such critical technical aspects, reviewing
Manuscript received December 19, 2019; accepted December 23, the proposed solutions mentioned in the literature and dis-
2019. Date of publication January 30, 2020; date of current version cussing their different levels of maturity.
March 24, 2020. The review of this article was arranged by Editor T. Kim.
(Corresponding author: Alessio Spessot.) II. DRAM K EY F UNCTIONAL A SPECTS
The authors are with imec, 3001 Leuven, Belgium (e-mail:
[email protected]; [email protected]). A. DRAM Chip Architecture
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. A DRAM cell is conceptually a very simple structure, based
Digital Object Identifier 10.1109/TED.2020.2963911 on a 1 selector transistor and 1 capacitor (1T-1C), which
0018-9383 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 SPESSOT AND OH: 1T-1C DRAM STATUS, CHALLENGES, AND PROSPECTS 1383

acts as a storage memory element [Fig. 1(c)]. The transistor,

also called access transistor or access device, has the gate
terminal connected to the word line (WL). The drain terminal
is connected to the bit line (BL) by a BL contact (BLC), and
the other terminal is connected to the capacitor by a storage
node contact (SNC). The access device acts as a switch,
and the capacitor can store the bit as a positive or negative
electrical charge. The memory state can be read by sensing
the stored charge on the capacitor via the BL, which is set
to an operating bias when the transistor is closed. When the
transistor is then switched on, the stored charge flows into the
BL, generating a potential change that can be detected and
amplified by a sense amplifier connected to the BL [9]. Fig. 2. Bias levels used in the modern DRAM, with an example of values
This basic structure is very simple and small, contributing for a DDR3. Adapted from [5].
to the ubiquitous diffusion of this memory device, but has
some disadvantages. The charge cannot remain in the small generator circuits. All these voltages are crucial for DRAM
capacitor forever, due to the leakage current from or to the device performance, so they should be precisely generated
access devices, making it lose its well-defined charge state from VDD with different trimming methods and applied to
over time [10]. To overcome this problem, DRAM memories the relevant chip area. VINTA and VINT are the key dc
are periodically refreshed, reading the content of the memory levels, which are provided to the core area and peripheral area,
and writing it back. This is where the name “Dynamic” means respectively. VINTA, which is the core area dedicated voltage,
in the DRAM context. drives the BL during read/write operations. More precisely,
As shown in Fig. 1(a), the DRAM chip can be divided into data transfer during the read/write operation occurs through
three major parts, which are identified as cell array, core part, the BL, where the swing level is driven from the ground
and peripheral part. In a modern mobile DRAM chip, the array voltage (VSS) (low level, corresponding to data “0”) to VINTA
area is composed of a memory cell array to store the data (high level, corresponding to data “1”). In addition, VINTA
and is the more significant area contributor since its portion is strongly related to the sensing margin, so higher VINTA
amounts to 50%–55% of the full-chip area [9]. The second increases the sensing margin at the expense of power increase.
one is the core area, which is composed of a row and column DRAM operation starts with the WL enablement, which is
decoder, a section WL driver (SWD), a BL sense amplifier driven by the word line voltage (VPP) level. VPP is the bias
(BLSA), and the conjunction (CJT) area formed in the cross applied to the gate voltage of the access transistor. This bias
region of BLSA and SWD to generate or pass through the is ∼3.0 V [5], which is higher than the external VDD and is
control signals for BLSA and data delivery on the I/O lines then positively boosted by the pump circuitry to ensure the
[Fig. 1(b)]. This section of the chip manages the read and ON -current required meeting the write-speed specifications.
write, decoding, and data restoring and typically occupies The leakage of the cell transistor is another crucial para-
25%–30% of the chip area. The last one is the peripheral part, meter since it affects the refresh time. To reduce the OFF-
which is formed by the control logic, I/O interface, and dc current of cell transistor, a negative-boosted WL voltage
circuits that account for the remaining ∼20% of the area [9]. (called VBBW) is applied. Typically, VBBW is lower than
In general, a DRAM chip is hierarchically composed of VSS and depends on the performance of the cell transistor.
rank, bank, and cell array also called MAT [Fig. 1(b)]. The Consequently, the WL swing level ranges from VBBW to VPP,
smallest element is the DRAM cell array. Each vertical column which ensures the high current by VPP and lower OFF-current
of the cells is connected to a BLSA, and each horizontal row of by VBBW. As in the case of VBBW, the cell transistor’s body
the cells is connected to an SWD. In typical modern devices, voltage (VBB) is applied to the bulk of the access transistor to
cell array consists of 1024 columns × 512–1024 rows. A larger decrease the OFF-current. By applying the VBB level, the cell
number of cells per MAT are beneficial to reduce the chip size transistor’s threshold voltage can be increased and the leakage
and to enhance the cell efficiency, and therefore, larger MATs current is limited. As shown in the bit cell configuration, one
are preferred from a cost perspective. However, for a fixed node of the cell capacitor is connected to the drain (source)
MAT density, the number of cells in BL and WL determines of the cell transistor, and the other node is connected to the
the parasitic loadings, which strongly affects the core per- cell plate which is a common node in the cell array.
formance (speed and power consumption). Therefore, special The plate voltage is commonly called VCP (cell plate
attention needs to be reserved for the tradeoff between the voltage), and its static level is fixed as half of the VINTA
sensing margin and performance due to the increase in loading. to reduce the cell capacitor stress and improve its reliability.
Typical values are VINTA ∼ 1.0 V and VCP ∼ 0.5 V [5].
It is relevant to mention that the internal reference level is
B. Voltages in DRAM Cell designed to compensate for the process–voltage–temperature
Fig. 2 shows the various operating voltages required in a (PVT) variation to guarantee the reliability of the device
DRAM device. Only VDD is applied to the DRAM as external operations. Examples of circuital solutions to accounting for
inputs, while all the others are generated by internal voltage the PVT variations are reported in [11].

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 1384 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

imum required time for precharging is determined by tRP.

Consequently, the read cycle (tRC) can be determined with
tRAS and tRP. All these parameters should be met to ensure
reliable DRAM operations.

D. Write
Write operation is initiated from the WL activation process,
as in the case of the read operation. Fig. 3 illustrates the
biasing condition during the write operation. At this time,
the boosted VPP voltage is applied to the WL to transfer the
data into the cell from the BL. Such VPP level, that as was
mention is the highest applied to the cell, can be defined as
Fig. 3. Basic DRAM cell operations. ACT, write and read, and precharge follows:
phases are visible. Signal pulses for WL, precharging (PEQ), sense
amplifier (LA/LAB), BLs, and column select line are visible. Adapted VPP ≥ VINTA + Vt + VINTA × γ (1)
from [9].
where VINTA is the array-dedicated voltage, and Vt and γ
are the threshold voltage and body-effect coefficient of the
C. Basic Cell Operation
cell transistor. Once WL is driven to VPP by the activation
Before going into the details of the operations, there are command, a high level (VINTA) or low level (VSS) is applied
a few crucial time parameters that define the internal core to the BL through the BLSA. After that, the storage node of
operation such as tRAS, tRP, tRC, tRCD, and tRDL, which the selected cell can preserve the written data through the cell
are shown in Fig. 3. transistor. As illustrated in Fig. 4(a), the write path includes
A typical DRAM cell operation is triggered by WL enable- the BL, the access transistor channel, and the storage node.
ment, which is also called activation (ACT) command. Obvi- Therefore, the total resistance that affects the write operation
ously, prior to WL activation, the DRAM cell remained in the includes the BL resistance (RBL ), the BLC resistance (RBLC ),
precharged state fixed by the precharging circuitry. As shown the access transistor channel resistance (Rch), and the SNC
in Fig. 3, once the ACT command is introduced, the precharge resistance (RSNC ). In particular, the channel resistance (Rch)
circuit disables the precharging signal [equalizing pulse signal depends on the boosted WL voltage (VPP), the gate oxide
(PEQ)] for core operation, and also, the WL selected by thickness, and the mobility of access transistor. On the other
the address decoding is enabled with the boosted voltage hand, contact dimension and plug materials influence RSNC
(VPP) that is applied to the gate of access device transistor. and RBLC . The time period required to write data to overdrive
As mentioned before, the VPP level is the highest dc level the sense amplifiers and written through into the DRAM cells
applied to the cell transistor during the operation and should is defined as write recovery time (tWR). It is clear that all
be enabled until the end of internal operation. The timing of the above-mentioned resistances should be controlled to avoid
this operation is determined by the tRAS parameter. During that the tWR is exceeded. tWR is the maximum time allowed
the WL activation, charge sharing takes place between the to complete the writing of the selected cell, and a precharge
BL and the storage node. This shared level can be enlarged command can be released only after the correct data values
by the sense amplifier’s enablement that is controlled by have been restored to the DRAM cells.
LA and LAB signals, which supply the power to the sense
amplifier, followed by the column select line (CSL) signal
(LA and LAB denote one of the SA enabling signals used E. Retention
to enable nMOS sense amplifier (NSA) and pMOS sense We have mentioned that the DRAM bit cell is composed
amplifier (PSA) located in the BLSA, respectively). This CSL of 1T-1C and the SNC located between cell transistor and cell
signal triggers that data transfers between BLs and I/O lines capacitor [Fig. 1(c)]. DRAM capacitor cannot retain the data
controlled by the column address. When a read command is permanently due to multiple leakage current paths [Fig. 4(c)],
given, the data are transferred from the memory cell array. and therefore, periodical refresh is needed (typical refresh time
In the case of the write operation, the written data are delivered is 64 ms according to JEDEC specifications). As shown in
from the I/O lines to the memory array, which forces the Fig. 4(b), retention time is widely distributed across different
BL to have a full swing from VSS (data “0”) to VINTA cells of a DRAM chip, and only a few cells are approaching
(data “1”). The time tRDL is allowed to complete the write the refresh limit. However, these weak cells are the real
operation, ensuring that the full swing of BL during the limiting factor for the refresh time. Proper screening of the
write operation can take place. On the contrary, read oper- weak cells and fabrication of redundant cells is needed to
ation should be controlled by the critical timing parameters enable the device functionality.
such as tRC and tRCD, as will be detailed in the read The main leakage current contributors, as shown in
section. Fig. 4(c), are as follows: 1) junction leakage from the SNC; 2)
After finishing the read/write operation, a precharging oper- gate-induced drain leakage (GIDL) current generated by the
ation is required to restore the BL precharge state; the min- access device; and 3) OFF-current leakage between SNC and

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 SPESSOT AND OH: 1T-1C DRAM STATUS, CHALLENGES, AND PROSPECTS 1385

Fig. 4. (a) Write path in the DRAM cell. Current flows from BLs into the access device channel till the capacitor plate. (b) Retention time distribution
inside a DRAM chip [5]. Only a few cells are typically exceeding the JEDEC specifications [9]. (c) Major leakage paths listed (d) as separate items.
(e) Total leakage contribution to retention time. Adapted from [5].

BLC. Additional leakage contributors are as follows: 1) leak- (VINTA or VSS) are destroyed, requiring a mandatory restore
age current under the field oxide from SNC and 2) leakage of operation at the end of sensing operation. At this moment,
the cell capacitor [Fig 4(d)]. charge-sharing time (tCS in Fig. 3) is critical for the following
The equation reported in Fig. 4(e) shows the relation among sensing operation, which strongly depends on not only the
the most crucial factors, which can be grouped into three main ratio of BL capacitance (CBL ) and cell capacitance but also
categories: stored charge, total leakage, and sensing ability VINTA. The charge-sharing time can be defined as the time
which determine the retention time. More specifically, higher required to achieve enough voltage difference (also called
storage node voltage (VINTA), higher cell capacitance (Cs ), sensing margin) between BL and BL bar (BLB) (see Fig. 3),
and lower leakage are helpful to increase the retention time. in other words, data “1” and data “0.” After tCS, when the
At the same time, higher sensing ability is desired, and this can source voltage is applied to the paired pMOS and nMOS
be obtained by reducing the ratio of BL capacitance (CBL ) to through the LA and LAB signals (Fig. 3), the sensing operation
Cs and reducing the sense amplifier offset voltage (Voffset ). gets started. At this moment, the source voltages are array-
Practically, higher VINTA is limited by the maximum oper- dedicated voltage (VINTA) and VSS, respectively. Due to
ating voltage within the circuitry and the consequent power the sensing operation, the signal difference can be enlarged
loss and reliability. The lower ration of CBL -to-Cs is required and stable sensing operation can be achieved. Based on the
to increase the retention time: Cs needs to be enlarged, despite enlarged BL developing, BLSA can be ready to take read/write
the dimensional scaling trend that tends to constantly reduce it, command triggered by CSL enablement. At the same time,
and reduced CBL coupling is desired. Another way to improve destructed data during the charge sharing can be restored.
the retention time is to minimize the leakage current below After the restore operation, enabled WL should be turned off,
critical value or to boost the sensing ability that needs to and at the same time, BL and BLB should go back to the
supervise the offset voltage of S/A. In Section III, we will precharge level though the precharging operation takes a time
describe the technological solutions adopted so far, and in window named tRP. Fig. 3 shows the waveform during data
Section IV, we will review some of the challenges for future “1” sensing operation. As mentioned above, after activating the
technology nodes. selected WL with ACTIVE command (ACT in Fig. 3), BLB
from unselected MAT maintains VBLP as a reference voltage,
F. Read/Sensing while the BL is connected to the accessed cell capacitor with
VINTA. Thus, the charge-sharing operation occurs, and due
The basic design of the voltage latch-typed BLSA is based
to the charge conservation, the voltage difference on BL can
on two cross-coupled CMOS inverters with strong positive
be calculated as follows:
feedback. Two NSAs and two PSAs constitute the cross-
coupled CMOS. Each S/A is connected with two BLs, and (Vcell − VBLP )
VBL =   (2)
one selected BL compared with an unselected BL which plays 1 + CCBL
s
the role of reference voltage with a precharged level.
The first step of the sensing is the precharge to the equal- where Vcell can be VINTA for data “1” or VSS for data “0,”
ized voltage [Bit line precharge voltage (VBLP)] before the Cs is the cell capacitance, CBL is the capacitance of the BL,
activation by the enablement of the BL equalizing signal (PEQ and VBLP is a precharged BL level. After charge sharing,
in Fig. 3). The applied equalized voltage is approximately half LA and LAB are changed to VINTA/VSS, respectively. This
of the VINTA, which biases the BLs at the same level. signaling provokes the sensing operation, and thereafter, data
The stored voltage at the cell capacitor is VINTA for data “1” sensing on BL is amplified to VINTA by the ON-state of
“1” and VSS for data “0” by writing operation. LAB and BLB as a reference is amplified to VSS by the ON-
When the WL is enabled (ACT in Fig. 3), charge sharing state of LA. Once the read command arrives after the specific
takes place between SNC and selected BL. The stored data time, the amplified output of BL and BLB are delivered to the

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 1386 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

perspective, the desired specifications are different from high-

performance logic devices because a higher ION /IOFF ratio
(∼108) is required [8], [14]. The low leakage is required
to prevent the discharging of the capacitor, and the high
ON -current is expected to write the data in a short time.
With the shrinking dimensions of the DRAM cell, the OFF -
current is increasing due to the degraded short-channel effect,
and the ON-current is limited by the reduced effective width
[5]. Also, the channel doping concentration increases with
the dimensional scaling, increasing the electric field and the
junction leakage current, which lowers the retention time.
A simple and effective way to overcome the short channel
effect is to increase the channel length (Leff). To achieve
this scope, the historical trend moved away from a planar
architecture to a more complex 3-D type of access device.
As final evolution, a possible full vertical integration can be
envisioned for future technology nodes, as will be presented
in Section IV. In the following, we will review the major
historical evolution of the access device, which is also shown
in Fig. 6.
1) Planar Asymmetric Junction: One of the key innovations
introduced with the 120-nm technology node was the asym-
metric junctions [15]. At that time, the access device was still
planar type, and the source and drain junction profiles were
Fig. 5. (a) Forecast of different DRAM technology nodes introduction independently optimized. The junction profile at the storage
[12]. EUV is expected to enter HVM in 1Z generation. (b) Cost of node was graded to reduce the electric field, which minimizes
ownership of immersion and EUV patterning relative to the cost and the
resolution limit [13].
the junction leakage current and thereby improves the data
retention time. On the contrary, the junction profile at the BL
direct contact node, which acts as a drain, was designed to
data path. This critical time is defined as tRCD with respect be shallower and suppress the short-channel effects of a cell
to the column access signal (CAS). Eventually, the precharge transistor.
command is followed by a tRP timing, which equalizes the 2) Stepped Gate STAR: In the evolution toward longer
amplified BL and BLB levels. channels by using the 3-D structure, in 2005, a novel step-
gated asymmetric (STAR) cell transistors device has been
proposed [16], where the channel length increase is obtained
III. H ISTORICAL E VOLUTION by recessing half of the channel and creating an asymmetric
In this section, we review some of the most relevant junction. This approach was proposed for the 100-nm tech-
historical trends and the latest innovation that is being already nology node and was compatible with the lower dimension.
introduced by industry in the most recent technology nodes. Although it does not require the fabrication of deep recess
At present, the 20-nm technology node is an industry mature channel, it suffers from poor scalability due to the large Vth
node, commercially available via multiple companies. Prod- variations, caused by the misalign effect between the gate and
ucts based on the technology nodes 1X and 1Y are in active area [5].
production across the major DRAM makers [11]. As shown in 3) Recess Gate RCAT: The ultimate extension of the chan-
Fig. 5(a) [11], the technology node 1Z is under development, nel length comes with 3-D structures. Recess channel gate
and nodes 1A (or 1α) and 1B (or 1β) are explored in the transistor (RCAT) has been introduced by Samsung in the 88-
research and development as future nodes. At present, some nm technology to increase the effective channel length without
DRAM companies had already announced the architectural compromising the lateral footprint [17]. The recessed channel
pathfinding of 1-γ generation [13]. Section III reviews all is obtained by growing the oxide on an etched Si surface,
the solutions adopted till nodes 1X and 1Y. The technology reducing the S/D resistance at the same time, and enhancing
innovation that might be introduced with the node 1Z and the carrier mobility, which can compensate for increased Leff.
beyond will be discussed in Section IV. Lower substrate doping concentration and smaller electric
field on the storage node junction can be achieved [17]. The
lower electrical field generates a significant improvement of
A. Cell Access Device History Review data retention time [5], while at the same time, electrical
As we have seen in the previous section, the access cell characteristics such as DIBL, break down, junction leakage,
transistor is the transistor that connects the BL data path to and cell channel resistance are improved. Thanks to RCAT,
the cell capacitor that stores the charge [Fig. 1(c)], and its gate significant improvements in both static and dynamic retention
bias is controlled by the WL bias (VWL ). From an electrical times were achieved. A natural extension of the concept was

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 SPESSOT AND OH: 1T-1C DRAM STATUS, CHALLENGES, AND PROSPECTS 1387

Fig. 6. Review of the historical evolution trend for the cell access device. Various cell access device options are shown. The 4F2 is enabled by the
vertical channel. Corresponding technology nodes are included. Adapted from [5], [9], [15]–[18], [20], [22], and [23].

the fabrication of deeper recess, needed to extend DRAM

technology down to 80 nm and beyond [9].
4) Sphere S-RCAT: A further extension of the Leff was
achieved by introducing the sphere-shaped-recess-channel-
array transistor (S-RCAT) (see Fig. 6) [18]. A simple scaling-
down of RCAT would induce worse gate controllability due
to the curvature effect. Increasing the curvature radius Rs
(with a sphere-shaped channel) helps to maintain the gate
controllability and long-channel length when scaling [9].
Thanks to an even enlarged curvature, the S-RCAT can
decrease DIBL, body effect, and Vth , resulting in the increased
retention time [18].
Fig. 7. (a) 8F2 , (b) 6F2 , and (c) 4F2 design architecture. (d) Folded BL
5) Saddle Fin: FinFET was proposed as access devices (e.g., sensing scheme is used in the 8F2 . (e) Open BL architecture sensing is
used in 6F2 . The 4F2 will likely adopt an open BL sensing. Adapted from
a so-called Omega-FET) to reduce the leakage, thanks to the [5] and [9].
improved electrostatics [19]. However, the required narrow
body width (∼2/3 Lg) creates some limitations to the practical
utilization in high-volume manufacturing (HVM) [20]. fabrication using the etching process [22], making it still the
The saddle fin cell transistors have been introduced with reference access device for modern DRAM.
the 50-nm technology node, and it is still the device used for
the 20-nm technology and beyond. This type of access device
combines the recess channel of the RCAT in the channel B. Cell Architecture
length direction with the FinFET structure in the channel width In the traditional DRAM technology, the cell design archi-
direction, and it is fabricated by etching both the field oxide tecture was based on an 8F2 geometry, where F is the
and the active silicon. The combined electrical benefit of both minimum feature size for a given technology node. As shown
structures is obtained, such an improved short-channel effect, in Fig. 7(a), this design is based on a folded sensing scheme
DIBL, and active current due to the partial triple gate [22], [Fig. 7(d)], where two physically adjacent BLs are connected
which all increases the retention time [20]. In one of the first to the same S/A. Two memory bit cells are connected to the
articles showing this concept, a fin height of about ∼40 nm same BL, sharing the drain node of the cell transistor. The
was shown [23] for a sub-50-nm technology. required BL pitch is 2F, while the WL pitch is 4F, resulting
In terms of achievable specifications, Lee et al. [22] showed in an 8F2 bit cell area.
DIBL ∼6 mV/V and subthreshold swing ∼85 mV/dec in a 44- The reliability of the operations is one of the major advan-
nm technology, respectively, thanks to the longer Leff. tages of the 8F2 , since it offers large noise immunity [5]. Since
Other improvements, such as superior gate controllability the paired BLs are connected to the same S/A, they show a
with a gate-shielded channel region, lead to the improvement similar noise susceptibility and, therefore, higher immunity to
of neighbor-gate effects [23]. It is relevant to also observe external noise. On top of that, all the adjacent BLs to the
that the cell-VT in a fully inverted channel region is mainly activated BL are precharged to a reference fixed level, which
controlled by the recess channel single-gate structure. Due to shields the activated BL itself. Therefore, the impact of the
the nature of saddle fin cell transistor, the sensitivity of the VT S/A mismatch is reduced.
versus fin width (WFin ) and fin height (HFin ) is opposite, and it Since the 80–90-nm technology node [6], [9], the demand
is also more sensitive to WFin variations than HFin. These two for further scaling forced the conversion from an 8F2 to a
combined effects enable larger process margins on saddle-fin 6F2 design architecture [Fig. 7(b)]. The 6F2 is based on an

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 1388 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

Fig. 9. Material options for capacitor [9] (left). Alternatives of capacitor

shape used in the industry (right). Adapted from [9] and [24].

Fig. 8. Different innovations currently used by the state-of-the-art

DRAM industry are shown. Scaling enablers like (a) buried WL [14] [Fig. 8(e)]. Interestingly, it has been shown that the voltage
and (b) honeycomb structures [24] are shown. (c) Supporters enhance breakdown of an air-gap-based spacer increases by reducing
mechanical stability [24]. Capacitance reduction can be achieved by
(d) air gap [24] with (e) example of integration flow [24], showing: 1)
the air volume, since the number of molecules that can be
the sacrificial material formation; 2) removal; and 3) capping Si3 N4 involved in the avalanche is reduced. Experimental results
deposition to form air spacer. show that an improvement of ∼30% in the breakdown is
achieved by air-gap spacers with respect to the Si3 N4 spacers,
accompanied by a capacitance reduction of ∼34%.
open BL architecture [Fig. 7(e)], with one BL fabricated on
the left side of the S/A and another BL on the right side.
The S/A pitch can be reduced from 4BL pitch to 2BL pitch C. Cell Capacitor Technology Innovations/Trends
[5]. In general, the open BL architecture offers a high degree We have seen that preventing a drastic Cs reduction with
of regularity, resulting in closer packing of memory bit cells the technology shrinking is one of the biggest challenges for
and consequent area reduction. Such area benefit needs to be modern DRAM. In the following, we will review some of the
balanced by higher integration difficulties [6] and larger noise solutions used in the industry to mitigate such Cs reduction
than the 8F2 . and present in a class 20-nm technology [24].
Another disadvantage of the 6F2 is that it requires a dummy 1) Material Selection: It is important to realize that the
array at the edges of the DRAM array to ensure the BL requirements for a capacitor dielectric in DRAM are signif-
loading matching. Also, since the coupled BLs are coming icantly different from those for logic gate dielectrics [25].
from different array segments (MAT), they can suffer from the In fact: 1) they are not in contact with Si; 2) the capacitor
following: 1) noise induced by the adjacent BLs in the selected electrodes are metals, so the band offset requirement is easier;
MAT, which is operating at the same time with different data 3) the capacitor is a back-end component so that it only
and 2) process-induced variability, which is expected to be needs to withstand lower temperature processing [25]; and
higher in two different MATs with respect to BL located in 4) it should be resistant to hydrogen-induced degradation,
the same MAT. and usually this requires forming a hydrogen diffusion barrier
To mitigate the noise vulnerability, a buried WL placed around it.
below the Si surface is currently used since the ∼40-nm Till the 45-nm technology node, HfO2 was the election
technology [14]. By using a Ti/W-buried WL [Fig. 8(a)], a low material for the DRAM capacitor technology. After it, ZrO2
resistive interconnect and the metal gate of the array transistor dielectric material has been the basis for a decade of DRAM
are formed. The buried WL cell can offer two times smaller capacitor technology, down to a 25-nm node [6] (Fig. 9,
BL capacitance and three times smaller WL capacitance per left). In particular, the trilayer structure made of tetragonal
cell compared to the conventional cell structure because of (or cubic) ZrO2 (k ∼ 40), amorphous Al2 O3 (k ∼ 9), and
the inherently smaller BL to WL coupling [14]. The smaller tetragonal (or cubic) ZrO2 again, which is also called ZAZ,
parasitic capacitances result in faster cell access, less power combined with TiN-based electrodes has been widely used
consumption, and improved signal margin. The drawback of in the industry [26]. It should be noted that further scaling
this architecture is the increased gate work function (WF), the ZAZ nanolaminate for sub-20 nm is challenging from
which might induce a GIDL leakage [5]. a leakage perspective, due to the reduced physical thickness
A significant component of the BL capacitance is linked to of the dielectric. We will discuss further material options in
the BL to storage node cell [5], which might account for about Section IV.
half of the entire BL capacitance. To reduce such a coupling 2) Deposition Technique: ALD: One of the requirements for
between the BL and the storage node cell, an air gap has been the dielectric layer utilized in the fabrication of the capacitor
proposed since the 20-nm technology [24]. The fabrication is its conformality in the entire covered surface. Even a tiny
of this module is based on a sacrificial material, which is difference in the layer thickness can generate a significant
located between the silicon nitride spacers [see Fig. 8(d)]. The E field difference, which is detrimental to leakage control.
sacrificial material is removed by isotropic etching, and the air The most suitable technique to achieve these expectations
gap generated is sealed by a capping layer of silicon nitride is represented by atomic layer deposition (ALD), which can

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 SPESSOT AND OH: 1T-1C DRAM STATUS, CHALLENGES, AND PROSPECTS 1389

grow a high-quality dielectric layer in a 3-D structure like a

capacitor and at relatively low temperature [6].
3) Capacitor Shape: Historically, different shapes of the
storage element have been considered to maximize the effec-
tive area. Examples of different solutions proposed are shown
in Fig. 9 (right).
For the technology nodes beyond 40 nm, the lateral size of
the capacitor is significantly larger than the physical thickness
of the layers, allowing the usage of a cylindrical capacitor to
maximize the effective area [6]. Fig. 10. Expected cell capacitance (Cs ) reduction versus technology
4) Honeycomb Structure (HCS): A honeycomb structure nodes down to 1Y, with the estimation of the node capacitance (left).
(HCS) has been proposed as a solution to maximize Cs for Adapted from [8]. Cs and data sensing signal (ΔV) margin (a.u.) versus
technology nodes, down to the 1Z [28] (right).
a given cell size [Fig. 8(b)]. Thanks to different packing
patterns, a relative increase of 7.5% of the pitch between two
adjacent cell capacitors is reached in the HCS with respect to
a square structure (SS) [24]. This corresponds to a potential capacitors need to be utilized to leverage their smaller feature
storage node diameter increase of +11% in the HCS with size. Consequently, a significant increase in the aspect ratio
respect to the SS, which directly translates in higher Cs for of the pillar height is required even higher than the cylinder
a certain capacitor height without increasing the high aspect case to mitigate the reduction of Cs . Some projections have
ratio etching capability [see Fig. 8(b)]. With the same dielectric been shown concerning the expected capacitance required for
material, the Cs of the HCS is 21% larger than that of the SS. future DRAM technology nodes, projecting aspect ratio (A/R)
5) Supporters to Enable Tall Cylinder: Another way to > 2.5 times worse than the cylinder [24].
increase the cell capacitance is to increase the height of the If we want to quantify some numbers, according to [29],
container. One of the problems of this approach is linked for the 1Y node, we can assume a hexagonal pitch of 50 nm
to the mechanical stability of the capacitor itself, which can and a capacitance target of 8 fF. To respect this target,
suffer from bending. This is mitigated by introducing a silicon a cylindrical capacitor requires a hole CD of 32 nm, while
nitride net, which enhanced the mechanical stability [27]. the pillar imposes a maximum pillar etch CD of 26 nm. This
More recently, two supporters have been introduced, one translates into an aspect ratio >30 for a capacitor and >60 for
positioned close to the top of the capacitor and the other a pillar, by using a conventional ZAZ material (k∼40) [29].
located approximately in the middle of the DRAM capacitor Clearly, such high A/R values impose critical concern on the
fabrication [Fig. 8(c)]. Such a solution can allow a significant mechanical stability and uniformity of the step coverage of a
height increase [24]. deposited film [28]. Even if multiple supporters can mitigate
the mechanical stability concern, as shown in the previous
IV. K EY T ECHNICAL A SPECTS AND F UTURE O UTLOOK section, the uniformity of the coverage remains a challenge.
ON THE C HALLENGES Partial mitigation can arrive by using double-pillar stacked [9].
A/R ∼ 100 has been mentioned as the maximum sustainable
It was shown that to be economically viable, the expected bit
level [6], and such value will be approached soon going down
growth should be >50% generation by generation considering
to 1Z and 1A technology nodes without material innovation.
the amortization of the required investment to keep pace
2) Material Innovation for Enhanced Dielectric Performance:
with the expected cost reduction trend year by year [5]. This
expectation is also coming with a constant pressure to decrease Material innovation can help in increasing the dielectric con-
the memory size, which is accompanied by a continuous stant and generating a larger bandgap [5]. Even in a pillar
complexity increase in the modern technology nodes. We will structure, the physical thickness of the dielectric needs to
illustrate the major technical challenges that are expected in be limited to 5 nm and below [6]. In terms of required
the coming years for future DRAM technologies going toward specifications, a new high-k material for the future DRAM
node 10 nm and below in the following section. capacitor should enable a low equivalent oxide thickness
(EOT) (<0.5 nm) for a physical thickness of <5 nm and
ultralow Jg (∼10–7 A/cm2 at an operating voltage) [6].
A. Low Capacitance Research has been conducted to reduce the thickness of the
Fig. 10 shows the expected trend of cell capacitance Cs dielectric material in the capacitor by using a material with
reduction [9], [28]. The dramatic capacitance reduction asso- the higher dielectric constant. Two of the material that are
ciated with scaling represents one of the fundamental problems considered very promising are TiO2 [30] and SrTiO3 [31],
for further extends the scaling potential. grown by ALD. It has been shown that [25] the k of the
1) Pillar, Mechanical Stability, and Coverage Uniformity: We oxide is inversely proportional to its bandgap, and in fact, both
have shown that cylindrical capacitors have been used to materials show high-k combined with narrow bandgap (3.2–
maximize the effective area of the storage node, and all 3.3 eV). In particular, the high k value of SrTiO3 (k > 100) has
the state-of-the-art devices are currently based on this tech- been shown in combination with capped Jg by controlling the
nology. On the contrary, for technology nodes beyond 20 grain size [32] and the stoichiometry with Sr enrichment [33].
nm, the cylindrical structure cannot fit anymore, and pillar Recently, a combination of SrTiO3 deposited on the top of

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 1390 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

ALD-Ru has reached a high dielectric constant (k ∼ 118) higher than the Ru itself [40]. The structural coherency showed
and low leakage, which makes this one of the candidates for by, e.g., rutile TiO2 /RuO2 [41] and SrTiO3 /SrRuO3 [42]
the future capacitor material [29]. There are, however, some provides EOT and Jg reduction. However, these conducting
challenges also in this solution. The demonstrated thickness oxides have not yet used in commercial DRAM capacitors
of the layer was ∼11 nm, which is promising but still due to practical implementation problems. Since the bonding
higher than what needs to be achieved in future technologies. between Ruthenium and oxygen is quite weak, these Ru oxides
Also, the dielectric properties were shown only in the planar are easily reduced during the back-end process.
capacitor structure, and the challenge is to demonstrate that Another candidate proposed as an oxide electrode with high
the interesting characteristics are kept in a 3-D integration with WF and thermal reduction resistant is Ta-doped SnO2 [43],
high A/R. which has shown promising dielectric properties, high WF
Another potentially interesting candidate is TiO2 , which can comparable to the RuO2 , and thermal stability. In fact, it has
crystallize in two phases, anatase (k ∼ 40) or rutile (k ∼ 80). been shown that structural and chemical stabilities have been
Even if the rutile phase was considered in the past, a high- preserved till annealing at 400 ◦ C [43].
temperature phase not compatible with the thermal budget
of the DRAM fabrication, EOT, and Jg reduction have been B. Access Device Dual WF
shown by growing rutile TiO2 on the top of RuO2 conductive
It has been shown that high-effective WF generates high
oxide at a deposition temperature lower than 300 ◦ C [6],
band-to-band generation on the drain side, which causes a
[30]. However, the scalability of the physical thickness seems
significant increase in the GIDL that dominates the leakage
limited to be 10–12 nm, which reduced the hopes to introduce
in the OFF-region [44].
it as a material for future technology nodes.
In fact, WF of gate metal has a huge effect on GIDL current.
3) Doping Dielectric: A reduction of the physical thickness
Using a material with a lower WF along all the channel of the
can be obtained by material doping [6]. Thickness down to
access device metal gate causes an unacceptable IOFF increase
7 nm with controlled Jg has been demonstrated by using the
due to lower Vth . However, if higher eWF material is used
Al-doped TiO2 dielectric [34].
only on the top part of the recess channel of the access
A doping approach has also been considered for other
device, the GIDL current is limited and the drive current
materials, in particular for HfO2 or ZrO2 dielectrics [6].
remains practically unaltered. As shown in [44], by using a
Dopants with larger ionic radius and lower electronegativity
combination of TiN with lower (4.5 eV) WF on the top of
than the corresponding host oxide generate higher k and Jg
the recess channel and higher WF (4.66 eV) at the bottom,
reduction for HfO2 . Rare Earth doping, such as Gd, Er, and
ION remains practically unaltered, while IOFF is significantly
Dy, has been proposed as a dopant to reduce the HfO2 leakage
reduced (e.g., ∼1/400 in Vg = −0.5 V at Vd = 1.5 V [44]).
compared with pure HfO2 [35]. The explanation of the reduced
Several methods of WF shifting were reported in the
leakage current and equivalent oxide thickness is linked to
literature, and different fabrication techniques based on the
the stabilization of the higher permittivity tetragonal phase.
combination of metal and poly gate for dual WF can be found
For ZrO2 dielectrics, La has been used as a dopant element
[45], [46]. Also, ion implantation of WF species by using a
to achieve k > 40 [36]. To the authors’ knowledge, these
tilted angle has been proposed as a localized way to achieve
approaches have not been integrated with DRAM capacitors,
desired WF in a cost-effective way [44].
due to difficulties in implanting species in high A/R 3-D
devices [37].
4) Electrodes in DRAM Capacitor: Electrode engineering is C. Device Structure: 4F2 and Vertical Transistor
another parameter to be leveraged in order to reduce Jg. In fact, Considering the cell structure, the 4F2 is the most compact
better dielectric performance can be achieved in a DRAM cell architecture that can allow an area reduction of 33%
capacitor by electrodes that have high WF and a sharp interface with respect to a 6F2 architecture. Vertical gate (VG) cell
between the electrode and the dielectric [6]. Currently, TiN (Fig. 6) is considered a promising candidate to enable the 4F2
grown by ALD is used as the electrode in the DRAM capacitor. transition. In the literature, there are demonstrations of 4F2
However, TiN WF is insufficient to suppress Jg at thin cell architecture to further scale down the DRAM cell [44],
dielectric thickness required for 1Z-nm technology nodes and by using a 30-nm process technology and a VG transistor,
beyond. New electrodes such as noble metals and conducting which offers superior driving capability than a conventional
oxide have been investigated. Ruthenium (Ru) is considered saddle transistor (Fig. 6).
one of the most promising candidates for DRAM capacitor In a 4F2 design, at each intersection of the WL and
electrodes [6]. Thanks to its relatively high WF (4.8 eV), Ru BL, there is one transistor and one capacitor [Fig. 7(c)].
can suppress Jg [38], and the compatibility with dry etch is an The vertical pillar is placed on the buried BL and under-
advantage for the electrode patterning. One of the drawbacks neath the storage node. This cell design has two advantages
of Ru is its high surface energy, which makes it difficult since it is highly favorable to lower the BL capacitance,
to fabricate a continuous and smooth Ru layer of <5-nm due to the distinct arrangement of the buried BL, and can
thickness. Also, morphological issues (e.g., blisters), which are offer a large on/off signal ratio [44]. One of the major
often occurring on ALD Ru on oxides, need to be addressed drawbacks of this architecture is the floating body effect,
to allow the HVM application of Ru as electrode [39]. which remains a significant obstacle even if the body of the
Considering material with high WF to reduce the leakage, VG transistor can be connected to the well in a buried BL
conducting oxides such as RuO2 and SrRuO3 have WF even structure [48].
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 SPESSOT AND OH: 1T-1C DRAM STATUS, CHALLENGES, AND PROSPECTS 1391

In fact, at the floating state, GIDL holes accumulated Different gate-stack integration proposals have been shown in
between the storage node and gate increase the body potential, the literature as compatible with a DRAM, since it induces
which in turn reduce the Vth of a transistor and result in the off- fermi-level pinning and potential gate leakage issue [55]. This
leakage failure and dynamic retention time degradation [48]. makes the gate first integration scheme more suitable for
Therefore, various approaches need to be considered to memory application. Both HfO2 [54] and HfSiON [56] have
reduce the floating body effect in the VG cell scheme. Among been proposed as HVM compatible. HfO2 is expected to be
the proposed device solutions, we can find the following more scalable for future technology nodes, and HfSiON is
in [48]: 1) the minimization of the GIDL by using storage mentioned to be more thermally stable [57].
node junction engineering [44] or buried body engineering To achieve a wider eWF separation gap between nMOS and
method [49]; 2) BL junction leakage increase by BL junction pMOS, doping material is desired into the HKMG stack. La
engineering; 3) hole barrier height reduction between the body and Mg have been proposed as the most promising doping
and the BL using SiGe layer; and 4) parasitic bipolar gain dielectric material for the nMOS devices. La offers a higher
reduction using the dimension control [50]. Concerning the achievable Vth shift, while Mg in a sandwich of TiN/Mg/TiN
design solutions to improve the floating body effect biases offers a more robust thermal stability [54]. Al2 O3 [58] and
operation optimization and purging hole charges within the SiGe channel [56] have been proposed for the pMOS device
body for a specified time interval are mentioned in [48]. DRAM compatible. There are RMG gate-stack proposals
which are compatible with the memory flow [55], with TiAl
and Ta/Ti used as dipole sources for nMOS and pMOS, respec-
D. Peripheral Transistor Performance tively. However, the implementation of the RMG scheme has
Peripheral devices needed in DRAM memory need to be: been limited to the capacitor flow.
1) low-leakage; 2) cost-effective; and 3) thermally resistant More recently, a diffusion and replacement metal gate
to the high thermal budget that are required by the front- (D&GR) scheme has been proposed [59] to reduce the gate
end-of-line (FEOL) and back-end-of-line (BEOL) steps. The asymmetry between the two device polarities and enhance
combination of all these specifications makes in practice the the thermal stability of the overall flow [60]. The reliability
direct copy of the technological solutions found in logic of the HKMG devices has been shown to N/P-BTI, HCD,
impossible [51]. Today, the state-of-the-art DRAM technology TDDB, and OFF-state stress [61], [62] for different integration
is still using the planar transistor based on silicon oxynitride schemes.
(SiON), but to keep pace with the expected system speed On top of the gate stack, all the other modules need to
improvement, more advanced solutions need to be found [52]. be thermally stable and optimized for memory applications.
In the following, we will review all the solutions that have been Contact resistance is one of the bottlenecks when the high
proposed in the literature but have not been implemented yet thermal budget is considered. A reduced access resistance can
by the industry. be achieved by replacing the silicidation through contact holes
It is interesting to note that there are three fundamental types by a complete silicidation of the source and drain areas [63].
of transistors used in a DRAM chip, which have different However, Ni(Pt) silicide typically used in logic devices suffers
requirements, as we have seen in Section II, and that can from too limited thermal stability, imposing the optimization
be grouped under the following categories: 1) regular logic, of a dedicated thermally stable silicide (TSS) module [64].
requiring good short-channel control; 2) sense amplifier (S/A), In fact, the thermal stability of a silicide increases with
which ideally shows low mismatch and low Vth ; and 3) thicker the C incorporation, but this improvement often comes at the
oxide to sustain higher bias, where reliability needs to be expenses of enhanced nMOS Vth -Lgate roll-off and pMOS
addressed [5], [9]. Clearly, the needs for the three categories device performance degradation [65]. TSS based on opti-
are different, but all have to be accounted for while designing mized NiPt concentration and combined with preamorphiza-
a single periphery platform, which has to remain cost-effective tion implant and anneal silicide stabilization steps have been
at the same time. It is important to note that the S/A mismatch integrated with a DRAM flow without electrical detrimental
represents a significant contributor in the overall sensing mar- impact [64].
gin, which is reducing node to node (Fig. 10, right). Nowadays, As a device candidate, FinFET has been proposed as
there are design solutions which have been proposed, at the advanced peripheral transistors [52]. In fact, these devices can
expense of area and power [28], or process solutions to reduce the area due to the higher effective width per footprint
minimize the random dopant fluctuation, thanks to the reduced and, at the same time, provide a benefit in terms of mismatch
dose of halo implant and new implantation schemes which that will benefit the S/A. Significant power-performance bene-
reduced the transient enhanced diffusion (TED) [8]. fit with respect to the planar conventional and HKMG devices
One of the obvious candidates to improve the electrostatic has been shown for FinFET, keeping the overall cost under
and, therefore, the electrical characteristics of the logic type is control and translating into system benefit [52].
to replace the SiON by high-k/metal gate (HKMG) dielectrics.
In 2007, Intel introduced the first high-k-based device, which E. Chip Cost Issue and EUV Lithography
was fabricated by using a replacement metal gate (RMG) The cost of a DRAM chip is mainly determined by the
scheme [53]. This specific approach cannot be directly coupled wafer process cost and the total number of bits per wafer [28].
with the thermal budget required by the DRAM, making it gate To enable the tremendous geometrical scaling expected from
first integration more suitable for memory applications [54]. the devices, an expensive 193i lithography process, such as

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 1392 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 67, NO. 4, APRIL 2020

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