Module 2

Verilog Models for Multiplexers

• A multiplexer is a combinational circuit and can be modeled using
concurrent statements only or using always statements. A conditional
operator with assign statement can be used to model a multiplexer
without always statements. A case statement or if-else statement can
also be used to make a model for a multiplexer within an always
statement.
Using Conditional Operator
Nested Conditional assignment
Modeling Registers and Counters Using
Verilog Always Statements

The three statements execute in sequence in zero time, and then the Qs values
change after a delta delay. In both cases, the old values of Q1 , Q2 , and Q3 are
used to compute the new values.
• Ans:3-bit shift register
Explanation: The list of statements executes from top to bottom in order. Note that
the blocking operator is used. Therefore, the first statement finishes update before
the second statement is executed. Synthesis results in a 3-bit shift register with serial
input A, and outputs Q1, Q2, and Q3.
• Answer: A single flip-flop
Explanation: The list of statements executes from top to bottom in order. Note that the
blocking operator is used. So the first statement finishes update before the second statement
is executed. Q1 gets the value of the serial input A when statement 1 finishes. In statement 2,
the same value propagates to Q2. In statement 3, the same value propagates to Q3. In effect,
the input A has reached Q3. Modern synthesis tools will generate a single flip-flop with input
A when this code is synthesized. The outputs Q1, Q2, and Q3 can all be connected to the
output of the same flip-flop. If the synthesizer does not have good optimization algorithms,
it might generate three parallel flip-flops, each with the same input A but with outputs Q1,
Q2, and Q3, respectively. As mentioned in the Note to Example 1, it is not a good practice
to use the blocking operator “5” in always blocks intended to create sequential logic. If one
were to use non-blocking statements, the order of the statements would not have mattered.
If else and for loop
$display,$write,$strobe,$monitor
Loops in Verilog
Multivalued Logic and Signal Resolution
Tristate module with always and assign
statements
Tristate module with assign statements
Built in Primitives
• There are 14 predefined logic gate primitives
• 12 predefined switch primitives to provide the gateand switch-level
modeling facility.
• Modeling at the gate and switch level has several advantages:
(i) Synthesis tools can easily map it to the desired circuitry since gates
provide a very close one-to-one mapping between the intended circuit
and the model.
(ii) There are primitives such as the bidirectional transfer gate that
cannot be otherwise modeled using continuous assignments.
User-Defined Primitives

The predefined gate primitives in Verilog can be augmented with new primitive elements called user-
defined primitives (UDPs).
UDPs define the functionality of the primitive in truth table or state table form. Once these primitives
are specified by the user, instances of these new UDPs can be created in exactly the same manner as
built-in gate primitives are instantiated.
While the built-in primitives are only combinational, UDPs can be combinational or sequential.
A combinational UDP uses the value of its inputs to determine the next value of its output.
A sequential UDP uses the value of its inputs and the current value of its output to determine the
value of its output.
Sequential UDPs provide a way to model sequential circuits such as flip-flops and latches. A
sequential UDP can model both level-sensitive and edge-sensitive behaviour.
• A UDP can have multiple input ports but has exactly one output port.
• Bidirectional inout ports are not permitted on UDPs.
• All ports of a UDP must be scalar—that is, vector ports are not permitted.
• Each UDP port can be in one of three states: 0, 1, or X.
• The tristate or high-impedance state value Z is not supported.
• If Z values are passed to UDP inputs, they shall be treated the same as X values. In sequential UDPs,
the output always has the same value as the internal state.
A UDP begins with the keyword primitive, followed by the name of the UDP. The functionality of the
primitive is defined with a truth table or state table, starting with the keyword table and ending with the
keyword endtable. The UDP definition then ends with the keyword endprimitive.
The truth table for a UDP consists of a section of columns, one for each input followed by a colon and finally
the output column.
Generate When an iterative array of identical operations or module instance is required, the generate
statement provides an easy way of instantiating these components.
Design the circuit diagram at gate level module

module Q3(A,B,C,F,Clk,E);

input A,B,C,F,Clk;
output reg E;
reg D,G;
initial begin
E = 1'b0;
D = 1'b0;
G = 1'b0;
end
always @(posedge Clk)
begin
D <= A & B & C;
G <= ~A & ~B;
E <= D | G | F;
end
endmodule
a) Analyze and write the output of the following code?

always (@ A or B)
begin
A = 5;
B=3;
#10;
A <= B;
B<=A;
end
module Unknown (y, a, b, r);
output y;
input a,b,r;
assign y = (r )? a : b;
endmodule
Before the execution of this code if abr = 111, after the execution of the code,
Analyze and write the value of y.
1. Given
• wire a = 1'b0;
• wire [1:0] b = 2'b10; wire [2:0] c =
3'b101;
• Evaluate
• i. { 4{a} }
• ii. { 4{a}, 2{b} }
• iii. { 4{a}, c}
1. Given
•

• reg [7:0] C;
• reg signed [7:0] D;
• reg signed [7:0] A = 8'hD5;
•
evaluate
i. C = A >> 4
ii. C = A >>> 4
iii. C = A << 4
iv. C = A <<< 4
v. D = A >> 4
vi. D = A >>> 4
vii. D = A << 4

viii. D = A <<< 4

•
1. For the following Verilog code segment:
• reg a;
•• reg
reg [2:0]
[10:0]b,x;c;
• a = 3’b100; b = 1’b1; c = 3’b101; x =
{{2{b}}, a,{2{c}}};
• What will be the value of x?
Program on shift operator
Verilog program on bitwise operator