Logic gates are an important concept in the study of electronics.

These digital
logic gates form the basis for all implemented computing machines. That is,
Logic gates are the basic building blocks of any digital system. It is an
electronic circuit having one or more than one input and only one output.
The relationship between the input and the output is based on certain
logic.

Logic gates are used to carry out logical operations based on the Boolean
Functions on a single or multiple binary inputs and give one binary output

Based on this, the basic logic gates are named as AND gate, OR gate,
NOT gate etc.

AND Gate -
A circuit which performs an AND operation and has n
input (n >= 2) and one output. The output of the AND gate is high(1)
when both the inputs are high(1) otherwise it is low(0).

OR Gate - A circuit which performs an OR operation and has n input (n

>= 2) and one output. The output of the OR gate is high(1) when either of
the inputs are high(1) otherwise it is low(0).

NOT Gate - NOT gate is also known as Inverter. It has one input and
one output. The output is high(1) when the input is low(0) and vice versa.

NAND Gate - A NOT-AND operation i,e inversion of AND operation is

known as NAND operation. It has n input (n >= 2) and one output. The
output of the NAND gate is high(1) when either of the inputs are low(0)
otherwise it is low(0).

NOR Gate - A NOT-OR operation i,e inversion of OR operation is known

as NOR operation. It has n input (n >= 2) and one output. The output of
the NOR gate is high(1) when both the inputs are low(0) otherwise it is
low(0).

XOR Gate - XOR or Ex-OR gate is a special type of gate. The exclusive-
OR gate is abbreviated as EX-OR gate or sometime as X-OR gate. It has n
input (n >= 2) and one output. This gate is used in the construction of
arithmetic circuits. The output of the XOR gate is high(1) when the inputs
are different otherwise it is low(0) when the inputs are same.

XNOR Gate - XNOR gate is a special type of gate. The exclusive-NOR

gate is abbreviated as EX-NOR gate or sometime as X-NOR gate. It has n
input (n >= 2) and one output. The output of the XNOR gate is high(1)
when the inputs are same otherwise it is low(0) when the inputs are
different.
Universal Gates

A universal gate is a gate which can implement any Boolean function

without using any other gate type. The NAND and NOR gates are
universal gates. In practice, this is advantageous since NAND and NOR
gates are economical and easier to fabricate and are the basic gates used
in all IC digital logic families.

The NAND and NOR gates are universal gates. To prove that, any
Boolean function can be implemented using only NAND or NOR gates. We
will show that the AND, OR, and NOT operations can be performed using
only these gates.

NAND Gate as a Universal Gate

Implementing an Inverter (NOT) using NAND Gate only
The following figure shows two ways in which a NAND gate can be used
as an inverter (NOT gate).

1. All NAND input pins connect to the input signal A gives an output A’.

2. One NAND input pin is connected to the input signal A while all
other input pins are connected to logic 1. The output will be A’.

Implementing AND using NAND Gates only

An AND gate can be replaced by two NAND gates as shown in the figure.
Two NAND gates are connected in sequential to get the AND gate. The
output of NAND gate1 is (AB)’. This will be an input for the NAND gate2.
The final output from the NAND gate2 is ((AB)’)’ which is equivalent to

1 2
AB.

Implementing OR using NAND Gates only

An OR gate can be replaced by three NAND gates as shown in the figure.
The output of NAND gate1 is (A)’ and NAND gate2 is (B)’. A’ and B’ will
be an input for the NAND gate3. The final output from the NAND gate3 is
(A’B’)’. By applying De-Morgan’s theorem (A’B’)’ is equivalent to A+B.

Thus, the NAND gate is a universal gate since it can implement the
AND, OR and NOT functions.

NOR Gate as a Universal Gate

Implementing an Inverter (NOT) using NAND Gate only
The following figure shows two ways in which a NOR gate can be used
as an inverter (NOT gate).

1. All NOR input pins connect to the input signal A gives an output A’.

2. One NOR input pin is connected to the input signal A while all other
input pins are connected to logic 0. The output will be A’.
Implementing OR Using NOR Gates only
An OR gate can be replaced by two NOR gates as shown in the figure.
Two NOR gates are connected in sequential to get the OR gate. The
output of NOR gate1 is (A+B)’. This will be an input for the NOR gate2.
The final output from the NOR gate2 is ((A+B)’)’ which is equivalent to
A+B.

1 2

Implementing AND Using NOR Gates only

An AND gate can be replaced by three NOR gates as shown in the figure.
The output of NOR gate1 is (A)’ and NOR gate2 is (B)’. A’ and B’ will be
an input for the NAND gate3. The final output from the NOR gate3 is
(A’+B’)’. By applying De-Morgan’s theorem (A’+B’)’ is equivalent to AB.

Thus, the NOR gate is a universal gate since it can implement the AND,
OR and NOT functions.

Applications of Logic Gates

Logic gates have a lot of applications but they are mainly based upon
their mode of operations. Basic logic gates are often found in circuits such
as safety thermostat, push-button lock, automatic watering system, light-
activated burglar alarm and many other electronic devices.
One of the primary benefits is that basic logic gates can be used in a
mixture of different combinations if the operations are advanced. Besides,
there is no limit to the number of gates that can be used in a single
device. However, it can be restricted due to the given physical space in
the device. In digital integrated circuits (ICs) we will find an array of the
logic gates.

Combinational circuit

Combinational Logic Circuits are made up from different gates that are
“combined” or connected together to produce switching circuits. These
logic gates are the building blocks of combinational logic circuits.

Some of the characteristics of combinational circuits are as follows:

 The output of combinational circuit at any instant of time depends
only on the levels present at input terminals.
 The combinational circuit does not use any memory. The previous
state of input does not have any effect on the present state of the
circuit.
 A combinational circuit can have an n number of inputs and m
number of outputs.

Block diagram

There are three main ways of specifying the function of a combinational

logic circuit -
 1. Boolean Algebra – it specifies the algebraic expression which
shows the operation of the logic circuit for each input variable.

 2. Truth Table – A truth table defines the function of a logic gate

by providing a list that shows all the output states in tabular form for
each possible combination of input variable.
 3. Logic Diagram – This is a graphical representation of a logic
circuit that shows the wiring and connections of each individual logic
gate, represented by a specific graphical symbol that implements
the logic circuit.

Adder
An adder is a digital circuit that performs addition of numbers. The adder
adds two or three binary digits called augend , addend or carry and
produces two outputs as sum and carry.

Half Adder
Half adder is a combinational logic circuit with two inputs and two
outputs. The half adder circuit is designed to add two binary input
number A and B and produces two outputs sum (S) and carry ( C ).

Block diagram

Truth Table Algebraic Expression

=A⊕B
S = AB’ + A’B
 C = AB

Circuit Diagram

Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. Half adder
cannot able to handle the carry from previous output. Therefore full adder adds two
one-bit numbers A and B and carry from the previous output C in and produces sum (S)
and carry (Co). That is, the full adder is a three input and two output combinational
circuit.

Block diagram

Truth Table
Circuit Diagram

Logical Expression for Sum

= ABCin + ABCin+ ABCin + ABCin
= Cin (AB + AB) + Cin’ (A’B + AB’)

A ⊕ B ⊕ Cin
= Cin XOR (A XOR B)
=

Another form in which COut can be implemented:

= A B + A Cin + B Cin (A + A’)
= A B Cin + A B + A Cin + A’ B Cin
= A B (1 + Cin) + ACin + A’ B C Cin
= A B + A Cin + A’ B Cin
= A B + A C-IN (B + B’) + A’ B Cin
= A B Cin + A B + A B’ Cin + A’ Cin
= A B (Cin + 1) + A B’ Cin + A’ B Cin
= A B + A B’ Cin + A’ B Cin
= AB + Cin (A’ B + A B’)
Therefore COut = AB + Cin (A EX – OR B)

Full Adder Logic Diagram

As the full adder circuit above is basically two half adders connected
together, the truth table for the full adder includes an additional
column to take into account the Carry-in, CIN input as well as the
summed output, S and the Carry-out, COut bit.

Implementation of Full Adder using Half Adders

Two Half Adders and a OR gate is required to implement a Full
Adder.
With this logic circuit, two bits can be added together, taking a carry
from the next lower order of magnitude, and sending a carry to the
next higher order of magnitude.
Implementation of Full Adder using NAND gates:

Implementation of Full Adder using NOR gates:

Total 9 NOR gates are required to implement a Full Adder.
A sequential circuit is a logical circuit, where the output
depends on the present value of the input signal as well as
the sequence of past inputs. While a combinational circuit is a
function of present input only. A sequential circuit is a
combination of combinational circuit and a storage element.
The sequential circuits use current input variables and
previous input variables which are stored and provide the
data to the circuit on the next clock cycle.

Sequential Circuits Block Diagram

Types of Sequential Circuits

The sequential circuits are classified in to two types.

 Synchronous Circuit
 Asynchronous Circuit
In synchronous sequential circuits, the state of device
changes at discrete times in response to a clock signal. In
asynchronous circuits, the state of the device changes in
response to changing inputs.

Synchronous Circuits
In synchronous circuits, the inputs are pulses with certain
restrictions on pulse width and propagation delay. Thus
synchronous circuits can be divided into clocked and un-
clocked or pulsed sequential circuits.

Synchronous Circuit

Clocked Sequential Circuit

The clocked sequential circuits have flip-flops or gated
latches for its memory elements. There is a periodic clock
connected to the clock inputs of all the memory elements of
the circuit to synchronize all the internal changes of state.
Hence the operation of the circuit is controlled and
synchronized by the periodic pulse of the clock.

Asynchronous Circuits
An asynchronous circuit does not have a clock signal to
synchronize its internal changes of the state. Hence the state
change occurs in direct response to changes that occur in
primary input lines. An asynchronous circuit does not require
the precise timing control from flip-flops.

Asynchronous Circuit

Asynchronous logic is more difficult to design and it has some

problems compared to synchronous logic. The main problem
is that the digital memory is sensitive to the order that their
input signals arrive them, like, if two signals arrive at a flip-
flop at the same time, which state the circuit goes into can
depend on which signal gets to the logic gate first.
Asynchronous circuits are used in critical parts of
synchronous systems where the speed of the system is a
priority, like as in microprocessors and digital signal
processing circuits.

Flip Flop Circuit

It is the basic storage element in sequential logic which

stores a bit of information i,e either 0 or 1 and fundamental
building blocks of digital electronic systems. They can be
used to keep a record of the value of a variable. Flip-flop is
also used to control the functionality of a circuit.

Flip flop is said to be edge sensitive or edge triggered rather than being level
triggered like latches.

RS Flip Flop

The R-S flip-flop is the simplest flip-flop. It has two outputs,

one output is the reverse of the other, and two inputs. The
two inputs are Set and Reset. The flip-flop basically uses
NAND gates with an additional enable pin. The circuit gives
output only when the enable pin is high.

Block Diagram
 SR Flip Flop Block Diagram

Circuit Diagram

SR Flip Flop Circuit Diagram

Truth Table

Operation

S.N Condition Operation

.

1 S = R = 0 : No
If S = R = 0 then output of NAND gates 3 and 4 are
change
forced to become 1.
Hence R' and S' both will be equal to 1. Since S'
 and R' are the input of the basic S-R latch using
NAND gates, there will be no change in the state of
outputs.

2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1
the output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset
condition.

3 S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of NAND-4
i.e. S' = 1.
Hence output of S-R NAND latch is Q n+1 = 1 and Qn+1
bar = 0. This is the reset condition.

4 S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND
gates 3 and 4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic
NAND latch.

JK Flip Flop
The name JK flip-flop is termed from the inventor Jack Kilby from texas
instruments. The basic S-R NAND flip-flop circuit has many advantages
and uses in sequential logic circuits but it suffers from two basic switching
problems.
 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be
avoided
 2. if Set or Reset change state while the enable (EN) input is high
the correct latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-
flop design, the JK flip Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs
and is considered to be a universal flip-flop circuit.

Circuit Diagram
 JK
Flip Flop Circuit

JK Flip Flop Truth Table

JK Flip Flop Truth Table

Delay Flip Flop /Data Flip Flp/D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter
connected between S and R inputs. It has only one input. The input data is
appearing at the output after some time. Due to this data delay between i/p and o/p,
it is called delay flip flop. S and R will be the complements of each other due to
NAND inverter. Hence S = R = 0 or S = R = 1, these input condition will never
appear. This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

Truth Table

Operation

S.N Condition Operation

.

1 E=0
Latch is disabled. Hence no change in output.

2 E = 1 and D =
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective
0
of the present state, the next state is Q n+1 = 0 and Qn+1‘=1.
 This is the reset condition.

3 E = 1 and D =
If E = 1 and D = 1, then S = 1 and R = 0. This will set the
1
latch and Qn+1 = 1 and Qn+1’=0 irrespective of the present
state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently
connected together. It has only input denoted by T as shown in the Symbol
Diagram. The symbol for positive edge triggered T flip flop is shown in the Block
Diagram.

Symbol Diagram

Block Diagram

Truth Table
Operation

S.N Condition Operation

.

1 T = 0, J = K = The output Q and Q’ won't change

0

2 T = 1, J = K = Output will toggle corresponding to every leading edge of clock

1 signal.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of
second to input of first. Master is a positive level triggered. But due to the presence
of the inverter in the clock line, the slave will respond to the negative level. Hence
when the clock = 1 (positive level) the master is active and the slave is inactive.
Whereas when clock = 0 (low level) the slave is active and master is inactive.

Circuit Diagram

Truth Table
Operation

S.N Condition Operation

.

1 J = K = 0 (No
When clock = 0, the slave becomes active and
change)
master is inactive. But since the S and R inputs
have not changed, the slave outputs will also remain
unchanged. Therefore outputs will not change if J =
K =0.

2 J = 0 and K = 1
Clock = 1 − Master active, slave inactive. Therefore
(Reset)
outputs of the master become Q 1 = 0 and Q1’ = 1.
That means S = 0 and R =1.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 0 and Q bar = 1.
Again clock = 1 − Master active, slave inactive.
Therefore even with the changed outputs Q = 0 and
Q’ = 1 fed back to master, its output will be Q1 = 0
and Q1’= 1. That means S = 0 and R = 1.
Hence with clock = 0 and slave becoming active the
outputs of slave will remain Q = 0 and Q’ = 1. Thus
we get a stable output from the Master slave.

3 J = 1 and K = 0 (Set)
Clock = 1 − Master active, slave inactive. Therefore
outputs of the master become Q1 = 1 and Q1‘= 0.
That means S = 1 and R =0.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the
outputs of the slave are stabilized to Q = 1 and Q
bar = 0.
4 J = K = 1 (Toggle)
Clock = 1 − Master active, slave inactive. Outputs of
master will toggle. So S and R also will be inverted.
Clock = 0 − Slave active, master inactive. Outputs of
slave will toggle.
These changed output are returned back to the
master inputs. But since clock = 0, the master is still
inactive. So it does not respond to these changed
outputs. This avoids the multiple toggling which
leads to the race around condition. The master
slave flip flop will avoid the race around condition.

Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses
only the binary numbers i.e. 0 and 1. It is also called as Binary Algebra or logical
Algebra. Boolean algebra was invented by George Boole in 1854.

Rule in Boolean Algebra

Following are the important rules used in Boolean algebra.
 Variable used can have only two values. Binary 1 for HIGH and Binary 0 for
LOW.
 Complement of a variable is represented by an overbar (-). Thus,
complement of variable B is represented as . Thus if B = 0 then = 1 and
B = 1 then = 0.
 ORing of the variables is represented by a plus (+) sign between them. For
example ORing of A, B, C is represented as A + B + C.
 Logical ANDing of the two or more variable is represented by writing a dot
between them such as A.B.C. Sometime the dot may be omitted like ABC.
A set of rules or Laws of Boolean Algebra expressions have
been invented to help reduce the number of logic gates
needed to perform a particular logic operation resulting in a
list of functions or theorems known commonly as the Laws
of Boolean Algebra.
Boolean Algebra is the mathematics we use to analyse
digital gates and circuits. We can use these “Laws of
Boolean” to both reduce and simplify a complex Boolean
expression in an attempt to reduce the number of logic gates
required. Boolean Algebra is therefore a system of
mathematics based on logic that has its own set of rules or
laws which are used to define and reduce Boolean
expressions.
The variables used in Boolean Algebra only have one of two
possible values, a logic “0” and a logic “1” but an expression
can have an infinite number of variables all labelled
individually to represent inputs to the expression, For
example, variables A, B, C etc, giving us a logical expression
of A + B = C, but each variable can ONLY be a 0 or a 1.

Properties of switching algebra –

 Annulment law – a variable ANDed with 0 gives 0, while a
variable ORed with 1 gives 1, i.e.,
A.0 = 0
A+1=1
 Identity law – in this law variable remain unchanged it is
ORed with ‘0’ or ANDed with ‘1’, i.e.,
A.1 = A
A+0=A
 Idempotent law – a variable remain unchanged when it is
ORed or ANDed with itself, i.e.,
A+A=A
A.A = A
 Complement law – in this Law if a complement is added to a
variable it gives one, if a variable is multiplied with its
complement it results in ‘0’, i.e.,
A + A’ = 1
A.A’ = 0
 Double negation law – a variable with two negation its
symbol gets cancelled out and original variable is obtained, i.e.,
((A)’)’=A
 Commutative law – a variable order does not matter in this
law, i.e.,
A+B=B+A
A.B = B.A
 Associative law – the order of operation does not matter if
the priority of variables are same like ‘*’ and ‘/’, i.e.,
A+(B+C) = (A+B)+C
A.(B.C) = (A.B).C
 Distributive law – this law governs opening up of brackets,
i.e.,
A.(B+C) = (A.B)+(A.C)
A+(B.C) = (A+B).(A+C)
 Absorption law –:-This law involved absorbing the similar
variables, i.e.,
A.(A+B) = A
A + AB = A