CS330: Operating Systems

Virtual Memory: Address translation

Recap: Process address space

Code - Address space abstraction provides the

Data same view of memory to all processes
Heap - Address space is virtual
- OS enables this virtual view
Free

Stack
Recap: Process address space

Code - Address space abstraction provides the

Data same view of memory to all processes
Heap - Address space is virtual
- OS enables this virtual view
Free
- User can organize/manage virtual
memory using OS APIs
- No control on physical memory!
Stack
Recap: Process address space

Code - Address space abstraction provides the

Data same view of memory to all processes
Heap - Address space is virtual
- OS enables this virtual view
Free
- User can organize/manage virtual
memory using OS APIs
- No control on physical memory!
Stack

Agenda: Virtual to physical address translation

 Translation at address space granularity
P1
0 Code
Data
Heap
- Physical memory of same size as
20KB the address space size is allocated
8KB Stack
P2 P1
to each process
0 Code - Physical memory for a process can
Data
28KB
Heap be at any address, but should be
32KB
contiguous
8KB Stack P2

40KB
RAM
 Translation at address space granularity
P1
0 Code
Data
Heap
- Physical memory of same size as
- How virtual address is translated to physicalofaddress?
20KB the address space is allocated
8KB - How
Stack
memory isolation isP1 achieved? to each process
P2
0 - What
Code happens on a context switch? - Physical memory for a process can
Data
- Advantages and disadvantages of 28KB
this scheme
Heap be at any address, but should be
32KB
contiguous
8KB Stack P2

40KB
RAM
ISA: commonly used addressing modes (x86)
- At a high-level, instructions contains two parts: opcode and operand
- ISA defines binary encoding of opcodes, mode and register operands
(more complex in practice)
- Operands can be specified in multiple ways
- Register: mov %rcx, %rax
- Immediate: mov $5, %rax
- Absolute: mov 8000000, %rax
- Indirect: mov (%rcx), %rax
- Displacement: mov -16(%rbp), %rax
X86 ISA: examples
- Access local variables using %rbp (examples)
- long a = 100, b =20, c;
- mov $100, -8(%rbp); mov $20, -16(%rbp)
- c = a + b;
- mov -8(%rbp), %rax; mov -16(%rbp), %rcx;
- add %rcx, %rax; mov %rax, -24(%rbp)
- PC relative jump/call
- jmp 0x20(%rip)
- call -0x20(%rip)
Role of the compiler
Compiled assembly

Simple function func: - Compiler can generate

func( ) 10: push %rbp; the code with starting
{ 12: mov %rsp, %rbp; address zero
int a = 100; 16: mov $100, (%rbp); - Compiler does not know
a+ = 10; 20: mov (%rbp), %rax
the stack address,
} 24: add $10, %rax
blindly uses the
29: mov %rax, (%rbp)
registers (rbp, rsp)!
33: pop %rbp;
35: ret;
OS during binary load (simplified exec)
load_new_executable( PCB *current, File *exe) PCB
mm_state
{
verify_executable(exe); Stack Data Code
Start Start Start
reinit_address_space(current → mm_state); End End End

allocate_phys_mem(current);
load_exe_to_physmem(current, exe);
set_user_sp(current → mm_state → stack_start);
set_user_pc(current → mm_state → code_start);
return_to_user;
}
 Address space to memory translation
P1
0 Code
Data
Heap
- Physical memory of 8KB is
20KB allocated and the code is loaded
-----------
push %rbp;
8KB Stack mov %rsp, %rbp; - The PCB memory state is updated
-------------
-------------
based on the executable format
28KB

RAM
Process state after exec( )
Kernel stack
20KB
(+10) push %rbp; User execution state
mov %rsp, %rbp; PC = 0
mov (%rbp), %rax SP = 8KB
add $10, %rax

28KB - When the process returns to user space, the

registers are loaded with virtual addresses
- PC = 0 and SP = 8KB

RAM
Process state after exec( )
Kernel stack
20KB
(+10) push %rbp; User execution state
mov %rsp, %rbp; PC = 0
mov (%rbp), %rax SP = 8KB
add $10, %rax

- When the process returns to user space, the

28KB registers are loaded with virtual addresses
- Code is loaded into physical memory (@20KB)
- At the start of “func” execution
- Instruction fetch address is 10 (PC = 10)
RAM
- SP will be around 8KB
Process state after exec( ) Dear HW! I have done my
part. Help me with the
Kernel stack translation, please!
20KB
(+10) push %rbp; User execution state
mov %rsp, %rbp; PC = 0
OS
mov (%rbp), %rax SP = 8KB
add $10, %rax

- When the process returns to user space, the

28KB registers are loaded with virtual addresses
- Code is loaded into physical memory (@20KB)
- At the start of “func” execution
- Instruction fetch address is 10
RAM
- SP will be around 8KB
Process state after exec( ) Here is a base register. I will add
the value of base register with
Kernel stack the virtual address generated by
20KB the program to get the physical
address. All yours buddy!
(+10) push %rbp; User execution state
mov %rsp, %rbp; PC = 0
mov (%rbp), %rax SP = 8KB CPU
add $10, %rax

28KB

RAM
Process state after exec( ) Here is a base register. I will add
the value of base register with
PCB the virtual address generated by
20KB the program to get the physical
address. All yours buddy!
(+10) push %rbp; User execution state
mov %rsp, %rbp; PC = 0
mov (%rbp), %rax SP = 8KB CPU
add $10, %rax

OS
28KB Hurray! I will configure the
value of base register as per
my need. I see some light
atlast!

RAM
Translation
CPU
20KB PC = 0
(+10) push %rbp; SP = 8KB
mov %rsp, %rbp;
mov (%rbp), %rax
add $10, %rax T_base = 20KB

- In this case, base register value should be 20KB

28KB - InsFetch (vaddr = 10) ⇒ InsFetch (paddr = 20KB +10)
- How “push %rbp” works?

RAM
Translation
CPU
20KB PC = 0
(+10) push %rbp; SP = 8KB
mov %rsp, %rbp;
mov (%rbp), %rax
add $10, %rax T_base = 20KB

- In this case, base register value should be 20KB

28KB - InsFetch (vaddr = 10) ⇒ InsFetch (paddr = 20KB +10)
- How “push %rbp” works?
- Assuming RSP = 8KB, “push %rbp” results in a memory
store at address (8KB - 8)
RAM
- CPU translates the address to (28KB - 8)
 Translation at address space granularity
P1
0 Code
Data
Heap
- How virtual address is translated to physical address?
- Physical memory of same size as
- The OS sets the base register value
20KBdepending onaddress
of the the physical
spacelocation.
is allocated
8KB The
Stackhardware performs the translation using the base value.
to each process
P2 P1
0 - How
Code memory isolation is achieved? - Physical memory for a process can
Data
- What
Heap happens on a context switch?
28KB
be at any address, but should be
- Advantages and disadvantages 32KB
of this scheme
contiguous
8KB Stack P2

40KB
RAM
Isolation: How to stop illegal access?
CPU
20KB
PC = 0
(+10) push %rbp;
mov %rsp, %rbp; SP = 8KB
mov (%rbp), %rax
add $10, %rax
T_base = 20KB

28KB OS How can I stop a program from

accessing VA = 20KB? If not
stopped, the program gets
access to physical address
40KB. I do not want to break
my promise of isolation.
RAM
Isolation: How to stop illegal accesses?
CPU Once a cry baby always a cry
20KB baby! I also provide a limit
PC = 0
(+10) push %rbp; register to enforce the limit
mov %rsp, %rbp; SP = 8KB during translation. Before you
mov (%rbp), %rax
add $10, %rax T_base = 20KB
ask, these registers can only be
changed from privileged mode
T_limit = 8KB

28KB

RAM
Isolation: How to stop illegal accesses?
CPU Once a cry baby always a cry
20KB baby! I also provide a limit
PC = 0
(+10) push %rbp; register to enforce the limit
mov %rsp, %rbp; SP = 8KB during translation. Before you
mov (%rbp), %rax
add $10, %rax T_base = 20KB
ask, these registers can only be
changed from privileged mode
T_limit = 8KB

28KB
- The hardware raises a fault if some program
violates the limit.
- The OS fault handler may kill the process

RAM
 Translation at address space granularity
P1
0 Code
Data
Heap
- How virtual address is translated to physical address?
- Physical memory of same size as
- The OS sets the base register value
20KBdepending onaddress
of the the physical
spacelocation.
is allocated
8KB The
Stackhardware performs the translation using the base value.
to each process
P2 P1
0 - How
Code memory isolation is achieved? - Physical memory for a process can
Data
- Limit
Heap register can be used to enforce memory
28KB
be isolation
at any address, but should be
- 32KB
What happens on a context switch? contiguous
- Advantages
Stack
and disadvantages
P2 of this scheme
8KB

40KB
RAM
Context switch and translation information

- The base and limit register values can be saved in the outgoing process
PCB during context switch
- Loaded from PCB to the CPU when a process is scheduled
 Translation at address space granularity
P1
0 Code
- How virtual address is translated to physical address?
Data
Heap
- - Physical
The OS sets the base register value depending memory
on the of location.
physical same size as
20KB of the
the base
address space is allocated
The hardware performs the translation using value.
8KB -
Stack
How
P2
memory isolation isP1 achieved? to each process
0 - Physical memory for a process can
- Limit
Code register can be used to enforce memory
Data
isolation
28KB
- What happens on a context switch?
Heap be at any address, but should be
32KB
- Save and restore limit and base registers contiguous
8KB - Advantages
Stack and disadvantages
P2 of this scheme
40KB
RAM
Translation at address space granularity: Issues

- Physical memory must be greater than address space size

- Unrealistic, against the philosophy of address space abstraction
- Small address space size ⇒ Unhappy user
Translation at address space granularity: Issues

- Physical memory must be greater than address space size

- Unrealistic, against the philosophy of address space abstraction
- Small address space size ⇒ Unhappy user
- Memory inefficient
- Physical memory size is same as address space size irrespective of
actual usage ⇒ Memory wastage
- Degree of multiprogramming is very less