Digital IC Design

Lec 1: Overview & Design Methodology

黃柏蒼 Po-Tsang (Bug) Huang

[email protected]

International College of Semiconductor Technology

National Chiao Tung Yang Ming University
 General Information
 Instructor : Professor Po-Tsang (Bug) Huang
 Email: [email protected]
 Office Hours: After class or by appointment @ MIRC 601

 Regular class hours

 Tuesday 1:20 AM – 4:20 PM

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 Grading of this Course
 60% Labs
 Tools: Verilog, HSPICE
 Most exercises are related to circuit-level implementation
 20% Final Team Project
 20% Final Exam
 On-line choice questions

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Undergraduate Course v.s. Graduate Course
 Undergraduate courses (VLSI)
 Basic transistor and circuit models
 Basic circuit design styles
 First experiences with design – creating a solution with given
numbers of specifications

 Graduate courses
 Transistor models of varying accuracy
 Design under constraints: power-constrained, flexible,
robust,…
 Learning the more advanced techniques
 Study the challenges facing design in the near future
 Creating new solutions to challenging design problems

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Digital Processing or Digital Computing
 Analog real world v.s. digital computing system
 Discrete digital data (binary digits: 0 & 1)

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Signal Characteristics
 Analog signals
 DC + Small signals (current-based or voltage-based)

 Digital binary signals

0&1

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 Binary Digital Signal
 An information variable represented by physical quantity.
 Binary values are represented abstractly by:
 Digits 0 and 1
 Words (symbols) False (F) and True (T)
 Words (symbols) Low (L) and High (H)
 And words on and off
 Binary values are represented by ranges of values of physical
quantities.

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Digital or Analog Signal?

 X1(t) is operating at 100Mb/s and X2(t) is operating at

1Gb/s.
 A digital signal operating at very high frequency is
very “analog”.
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Binary Logic Level
 The signal voltage must make into the “End
Zone” within the allotted period of time.

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 Introduction to Signal Aberration
 Power noises (power integrity)
 Parasitic R,L,C
 Coupling effect
 Non-continuous physical links

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2-level Circuits

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2-level Circuits

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 Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to
drain

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
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What is Transistor?

A Switch! An MOS Transistor

VGS ≥ V T |VGS|

Ron
S D

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CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
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CMOS NAND Gate

A B Y
ON
OFF
OFF
ON OFF
ON
0 0 1
0 1 1
1
0
Y
1 0 1
A
ON
OFF

1 1 0 0
1
1
0
B
OFF
ON
ON
OFF

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CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

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 Basic Logic for Digital System in CMOS ICs
 Combination logic
 Control switch (MUX)
 Computation (XOR)
 Basic logic – INV, NAND, NOR
 Sequential circuits & Finite State Machine (FSM)
 Storage element (Latch, Flip-Flop)
 Data storage
 Register file, SRAM, eDRAM, eFlash…
 I/O (input/output)
 ESD protection, driving ability, level-sensing

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The Regenerative Property for SRAM
Vi1 Vo1 Vi2 Vo2 C

cascaded inverters A B

A
If the gain in the transient
region is larger than 1,
C
only A and B are stable
operation points. C is a
B metastable operation
Vi1 = Vo2 point.

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How to put together millions of transistors?
 Well chosen design methodologies
 Well chosen architectures
 Extensive use of power full CAD tools
 Strict design management
 Well chosen testing methodologies
 Design re-use
 One can NOT use same design methodologies and
architectures when complexity increases orders of
magnitude

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General Principles
 Technology changes fast => important to
understand general principles
 optimization, tradeoffs
 work as part of a group
 leverage existing work: programs ,building blocks
 Concepts remain the same:
 Example: relays -> tubes -> bipolar transistors
->
MOS transistors -> FinFET -> GAAFET (MBCFET)
Future Trend for advanced
technology nodes or 3DIC
DTCO: Design-technology co-optimization
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MOS Transistor: 3D Perspective

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FinFET

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Complementary Charastertcis

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 GAAFET, MBCFET, RibbonFET
 Transistors have evolved to provide better PPA
for designers
 GAA is the ultimate transistor with 4-sided
channel
 GAA flexible Weff provides more freedom to
optimize PPA

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Design Abstraction Levels

SYSTEM
Top-Down
Design
MODULE
+
GATE

CIRCUIT
Bottom-Up
Library G
DEVICE
S D
n+ n+

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Typical IC Design Flow (Methodology)

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Foundry (Process) Design Kit (FDK, PDK)

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Full-Custom Design
 Design some or all of the circuits, logic cells,
layout specifically
 Required cells/IPs are not available
 Existing cell libraries can not meet the requirements
 Area, speed or power consumption
 Technology migration (analog or mixed-mode
design)
 Demand long design time

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 Cell-based (IP-Based) Design
 Use pre-designed logic cells (known as standard
cells) and micro cells or IPs
 Each standard cell can be optimized individually
 All mask layers are customized
 Custom blocks can be embedded

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System Design Paradigm
 Data computation (functional IP)
 Data communication (platform)
 Data storage (memory)

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SoC Hardware Design Methodology

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 Design Metrics
 Evaluate performance of a digital circuit
and System
 Cost
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function
 Robustness
 Reliability
 Scalability

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 Design Challenges for Future IC Design
 Large variations
 Increasing leakage current
 Increasing RC of Interconnects
 Power integrity (large power noises)

Ideal Voltage Level

Vdd (DC)

Voltage with
dynamic IR drop
Minimal
Tolerance Level

[IEDM’19]

Static IR drop Dynamic IR drop

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Problems of Wire Delay
 Wire loading: timing optimization is based on a
wire loading model.
 Loading of gate = input capacitance of following
gates + wire capacitance
 Gate loading known by synthesizer
 Wire loading must be estimated
 R-C delay calculation very complicated
Delay
Wire load delay Average Average

Large chip
Small chip
Gate delay

Technology Wire capacitance

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