Scribd
Upload
15 views1 page

Training On Fpga Technologies

ViZYNQ Technologies offers a training program on FPGA technologies tailored for ISRO, covering topics such as VHDL, RTL, high-level synthesis, and Zynq7000 architecture. The program includes hands-on experience with ZED boards and various interfacing techniques, as well as SDK applications for real-time projects. Note that the training is qualitative and does not include hardware, software, or placement assistance.

Uploaded by

NEERATI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
15 views1 page

Training On Fpga Technologies

ViZYNQ Technologies offers a training program on FPGA technologies tailored for ISRO, covering topics such as VHDL, RTL, high-level synthesis, and Zynq7000 architecture. The program includes hands-on experience with ZED boards and various interfacing techniques, as well as SDK applications for real-time projects. Note that the training is qualitative and does not include hardware, software, or placement assistance.

Uploaded by

NEERATI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

ViZYNQ TECHNOLOGIES

ADDRESS: H.No 3-7/51/A, PLOT No. 51. Rudra Nilayam, Shiva Sai Ram colony, Munganoor, Hayathnagar, Telangana-501505.

Estd:2021

TRAINING ON FPGA TECHNOLOGIES for ISRO


1. Basics of FPGA
2. Fundamentals of VHDL or Verilog
3. Fundamentals of Register transfer Level (RTL)
4. Working with the High level synthesis (HLS) (Ex Xilinx Vivado) to explore
a) Concurrency in algorithms
b) Clock speed optimization
c) Control path & Data path separation
d) I/O Interface (Digital and Analog)
e) Functional specification to HLS
f) Targeting computational device
g) Providing the Optimization Directives ( Ex Pipe-lining, Memory Optimization, Bit
width optimization etc..)
h) Test bench usage for verification
i) Resource usage and performance Evaluation
5. Zynq7000 architecture and features (Focusing on ZED board and its expansions)
6. Hands-On Experience on ZED board
7. Xilinx Ip core (DDS) simulation using synthesis.
8. Debugging procedure using Chip-scope.
9. Interfacing with various hardware like ADC / DAC board, LED screen etc.
10. Software defined radio (SDR) using FPGA.
SDK
1. Lwip in real-time projects with proper settings for 1/10/100Gbps using Vivado (using MIO PINS)
a) TCP/IP Server and client
b) UDP Server and client
2. Required Software for testing Server side and Client side and what are the observation/settings
required for effective response
3. Above same Lwip using EMIO pins, is there any sample vhdl code for Lwip and how to build
project and select the constrains in UCF/XDC in vivado
4. What are the speed limitations between MIO and EMIO?
5. How to connect the CLOCKS of PS to PL vice versa..
6. Bit files burning on Qspi/SD CARD
7. What are the basic tests for FPGA and how can test it?
8. Register mapping and register file design and configuration
9. How to select customized board components in UCF/XDC

NOTE: 1.If anyone having less time to complete an internship or training, the
company plans to select index items according to your time line.
2. The Company provides only Qualitative program/training not placements.
3. Company do not provide any Hardware or Software
4. We provide out materials/notes in softcopy mode that will be sent to your mail only

You might also like