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SPI-Serial Peripheral Interface

The document provides a comprehensive overview of the SPI (Serial Peripheral Interface) protocol, detailing its functionality, pin descriptions, and various communication modes. It highlights the advantages of SPI, such as high data transfer speed, while also noting its limitations in distance. Additionally, the document explains the SPI transmission and reception processes, along with configuration options like CPOL and CPHA for practical applications.

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Robert L.
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14 views18 pages

SPI-Serial Peripheral Interface

The document provides a comprehensive overview of the SPI (Serial Peripheral Interface) protocol, detailing its functionality, pin descriptions, and various communication modes. It highlights the advantages of SPI, such as high data transfer speed, while also noting its limitations in distance. Additionally, the document explains the SPI transmission and reception processes, along with configuration options like CPOL and CPHA for practical applications.

Uploaded by

Robert L.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SPI-Serial Peripheral Interface

Dhruv Satasiya
Content
• Introduction
• Why SPI Protocol?
• PIN Description
• How Does SPI Work?
• Types of SPI Communication
• SPI Protocol Configurations
• CPOL and CPHA
• SPI Transmission Process
• SPI Reception Process
Introduction
• SPI is a synchronous serial communication protocol used to communicate
with one master and one or more slave devices in Embedded Systems.
• Here, a Microcontroller can behave as a Master, while Slave devices may
include various sensors, EEPROM, Display, Bluetooth, etc.
• SPI protocol is famous for its simplicity and high data transfer speed.
• There are four fundamental pins on the master and slave sides.
Why SPI Protocol?
• SPI & I2C both protocols perform the best when it comes to speed as the
maximum rate of transferring the bits is fPLCK/2, which means if MCU is
running at 16MHz of frequency then SPI can transfer 8M bits per second.
• However the main drawback of SPI protocol is its capacity of distance. The
maximum distance for sending bits is only around 10 feet.
PIN Description
• MISO: Master In Slave Out, the
master receives data from the slave.
• MOSI: Master Out Slave In, the
master sends data to the slave.
• SLCK: Serial clock
• SS: Slave Select / Chip Select

Fig. 1 SPI Communication Protocol


How Does SPI Work?

• Connecting the MOSI pin of the master to the MOSI pin of the slave and the
MISO pin of the master to the MISO pin of the slave enables communication
between master and slave.
• One of the GPIO pins of the MCU can provide the serial clock to the slave.
• Pulling the NSS pin to the ground enables the corresponding slave device to
receive the data from the master.
• SPI communication is a simple technique based
Behind the Scene
on a shift register and two buffer registers.
• There are two buffer registers, one on the master
side and another on the slave side, usually known
as Tx and Rx buffers.
• As soon as the clock is enabled, at every clock
one bit is shifted from the master side to the
slave side and visa versa from the slave side to
the master side.
Fig. 2 SPI – Behind the Scene
• Hence, after 8 clock ticks, transmission and
reception of the one byte is accomplished.
SPI Engine with a
shift register and
Rx, Tx buffers

SPI SFRs for


various
configurations

Fig. 3 SPI Block Diagram for STM32F407VGT6 Arm Cortex M4 MCU


Types of SPI Communication
• Full Duplex Mode
In the full-duplex mode of SPI communication, the master sends data to the slave
and receives data from the slave simultaneously.
• Half Duplex Mode
In the half-duplex mode of SPI communication, Data transfer occurs in one
direction at a time —sending or receiving, but not simultaneously.
• Simplex Mode
In simplex mode, SPI communication is unidirectional, meaning data flows in only
one direction. Either the master sends data to the slave, or the slave sends data to the
master, but not both. There is no need for a MISO line. The master can behave as a
receiver by setting the RXONLY bit field in the SPI configuration register by software.
(Refer to the Fig. 3 - SPI Block diagram on the previous slide)
SPI Protocol Configurations
• SPI Peripheral Configural Items
1. SPI Device Mode – Device a master or a slave?
2. SPI Bus Config – what kind of communication? –Full, Half duplex, or simplex?
3. SPI DFF – Data Frame Format – 8 bits (default) or 16 bits packet?
4. SPI CPHA – Clock Phase
5. SPI CPOL – Clock Polarity
6. SPI SSM – Slave Management -> NSS pin managed by Hardware or Software?
7. SPI Speed – SCLK Speed. (Max 8MHz when HSI oscillator @16MHz is used.)
Fig. 4 An Example of SPI Configural Structures Using C Language
CPOL and CPHA
• CPOL – Clock Polarity decides the idle state of the serial clock
-> CPOL = 0: clock remains low in idle state.
-> CPOL = 1: clock remains high in idle state.
• CPHA – Clock Phase decides when to sample(read) the data, on the first or
second edge of the serial clock.
-> CPHA = 0: samples the data on the first edge of the clock.
-> CPHA = 1: samples the data on the second edge of the clock.
Mode CPOL CPHA Idle Clock State Data Sampled on
(read)
0 0 0 Low Rising Edge(First)
1 0 1 Low Falling Edge(second)
2 1 0 High Falling Edge(First)
3 1 1 High Rising Edge(Second)

The above table shows the details of how different modes of SPI serial communication
can be achieved while changing the states of CPHA and CPOL to fulfill real-world
Applications. The next slides incorporate practical outputs of transmitting a message or data
using SPI communication.
CPOL = 0

CPOL = 1

CPHA = 0

These results are achieved by keeping the


STM32F407 Discovery board in master mode
and capturing it through a USB logic
analyzer.
Sending a long message over the MOSI line (100+ characters)

Sending a message using interrupts


SPI Transmission Process
1. Write Data to SPI_DR
When the data is kept in the SPI_DR register it is automatically placed into the Tx
buffer resetting the TXE bit(TXE = 0) as, now, the Tx buffer will not be empty.
2. Moving Data to the Shift Register
The Tx buffer immediately places that byte to the Shift register, which is the actual
sender setting the TXE flag(TXE = 1), indicating that the Tx buffer is again empty and
ready to accept the next byte.
3. Interrupt Trigger (if TXEIE is enabled)
If the TXEIE (TXE Interrupt Enable) bit is set in SPI_CR2, the SPI will raise an interrupt
when the TXE bit becomes 1, telling the CPU, "Hey, I’m ready for more data!"
SPI Reception Process
1. Read Data from the Shift Register
When data is received on the SPI line (from the connected device), it is first placed into the
Shift Register, the part of the SPI that captures the incoming data.
2. Moving Data to the Rx Buffer
Once the entire data byte (or word) is received, the SPI hardware automatically moves this
data from the Shift Register into the Rx Buffer. Simultaneously, the Rx Buffer is filled with
the received data, and the RXNE flag (Receive Buffer Not Empty) is set to 1, indicating, "Hey,
there’s new data ready to be read!"
3. Interrupt Trigger (if RXNEIE is enabled)
After the Rx Buffer is filled with the received data, the RXNEIE flag (RXNE Interrupt Enable) is
set to 1 by the software, indicating, "Hey, there’s new data ready to be read!“
NOTE: RXNE is a read-only bit, so the data sitting in the Rx buffer must be read to reset the
RXNE flag indicating the CPU to read the next data.
Thank You…

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