BIS302: DIGITAL DESIGN AND COMPUTER ORGANIZATION

Semester: 03 Credits: 04
Number of Hours/Week: 04 IA Marks: 50
Total Number of Hours: 50 Exam Marks: 50

MODULE – III
Basic Structure of Computers
Basic Operational Concepts
Bus Structures
Performance
Processor Clock
Basic Performance Equation
Clock Rate
Performance Measurement

Machine Instructions and Programs

Memory Location and Addresses
Memory Operations
Instructions and Instruction Sequencing
Addressing Modes
 Module Objectives
o Basic structure of a computer
o Bus structures
o Performance issues in computer systems
o Machine instructions and program execution, including branching
and subroutine call and return operations
o Addressing methods for accessing register and memory operands
o Assembly language for representing machine instructions, data
and programs
o Program-controlled Input / Output operations
o Operations on stack, queue, and array data structures.

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M1.1: BASIC STRUCTURE OF COMPUTERS

1. Introduction
1.1 Computer Types
Definition Computer/Digital Computer:A contemporary computer is a fast electronic calculating
machine that accepts digitalized input information, processes it according to a list of internally stored
instructions and produces the resulting output information.
The list of instructions is called a computer program and the internal storage is called computer
memory.

Types of Computers:
 Personal Computer: It is a type of desktop computer consisting of processing and storage units,
visual display, and audio output units, keyboard. It is used in homes,schools, business offices.
 Notebook Computer: It is a compact version of a Desktop Computer where everythingis packed
together into a single unit, the size of a thin briefcase.
 Workstations: These have high resolution graphics input/output capabilities, have significantly
more processing power than personal computers. These are used in engineering applications for
interactive design work like animation.
 Enterprise system/Servers (low end)
Servers contain sizeable database and serve large volumes of requests to access the data. The
request and theresponse are usually transported over internet.
 Super Computers(high end)
These are large computers used for data intensive processing ex weather forecasting,aircraft
design
 Mainframes: Used for business data processing inmedium and large corporation that needs more
computing power and storage capacity than workstation.

1.2 Functional Units

A computer consists of five functionally independent main parts:input,memory, arithmetic logic, output,
control units as shown in fig 1.1:
 Input unit accepts user inputs via say keyboard and the information is stored in memory. The
arithmetic and logic unit operates on the input data and the result is forwarded to output unit.
The control unit manages all these units.
Data handled by a computer can be categorized as:
 Instructions or machine instructions
 These govern the transfer of information with a computer and between a computer and its
I/O device.
 It also specifies the arithmetic and logic operations to be performed.
 Set of such instructions is called a program and is stored in memory. A processor fetches
these instructions and executes them one after another.
 Data
 Number and encoded characters used as operands by the instructions.
 Source program (high level program ex program or object program (machine language
program can also be treated as data)
Encoding of data
 Data handled by a computer is encoded as a series of 0’s and 1’s called bits.
 Numbers can be represented encoded binary coded decimal (BCD)
 Alphanumeric characters can be coded using ASCII(American standard code for Information
Interchange) or EBCDIC (Extended Binary Coded Decimal Interchange Code)

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In ASCII 7-bits are used to code alphanumeric characters and EBCDIC, 8 bits are used.

1.2.1 Input Unit

 Keyboard is one of the input units
 When a key is pressed on keyboard a corresponding binary code is transmitted over a cable to the
memory/processor.
 Other input devices are: joysticks, trackball mouse, microphones.

1.2.2 Memory Unit

 Memory stores “programs” and “Data”
 There are two types of memory
 Primary Memory
 Secondary Memory

Primary Memory
o It is a fast memory where programs are stored when they are being executed.
o It is made of large number of storage cells where each cell stores one bit.
o The memory is organized into chunks of m bits called words. Data is read /written from
memory in terms of words.
o Each memory location is associated with an address. This needs to be specified while doing
a read/write operation.
o The length of word determines the type of machine. The length could be 16 bits, 32 bits or
64 bits etc.
o The primary memory is also called random access memory(RAM).The time required to
access one word is called memory access time. This memory access time ranges from few
nanoseconds(ns) to 100ns
o Hierarchy of RAM
 Cache: small and fast RAM units. These are highly coupled to processors and are part
of the same processor chip.
 Main Memory: This is largest and slowest unit.

Secondary Storage
o Primary storage is expensive hence large amount of data and programs are stored in
nonvolatile memory called secondary storage.
o For example: magnetic disks,tapes, optical disks(CD-ROMs)

1.2.3 Arithmetic and Logic Unit

 Most computer operations are executed in arithmetic and logic unit (ALU).

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 Operations like addition,subtraction,multiplication, division,comparison of numbers etc. are
performed in ALU.
 To perform these operations,the operands are placed in high speed storage elements called
registers and output could be stored in memory/register.

1.2.4 Output Unit:

 Output unit sends processed results to outside world
 Ex: printers, monitors
 The speed of output devices is slower compared to processor speeds

1.2.5 Control Unit

 Memory,ALU andI/O devices are controlled and coordinated by control unit by sending timing
signals.
 Control unit coordinates the operations. It is generally not a single unit but it is distributed throughout
the machine.

Summary
 The computer accepts information in the form of programs and data through an input unit and stores
it in memory.
 Information stored in memory is fetched under program control into an arithmetic and logic unit,
where it is processed.
 Processed information leaves the computer through an output unit.
 All activities inside the machine are directed by control unit.

1.3 Basic Operational Concepts

A computer performs task by executing instruction from memory. These are moved from memory to
processor. For example:
Add LOCA, R0

In the above instruction contents of memory location “LOCA” are added to that of R0once the sum is
stored in Register R0.
The above instruction is generally done in two steps.
Load LOCA, R1
Add R1, R0

So, the contents of memory LOCA are stored

in R1,subsequently contents of R1 are added
to R0.
The figure below shows the connections
between memory and processor.

Other than control unit and ALU, processor

contains some special registers.
 Instruction Register(IR): This register
holds the current instruction being
executed. The output of IR is available
to control unit to generate control
information.
 Program Counter(PC): This register
contains address of next instruction to

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be executed when current instruction is being executed. PC moves to the next instruction that
shall be executed.
 General purpose registers. Registers R0 to Rn-1 are general purpose registers which are used
during computation/program execution. For example,
Add R1, R0
Move LOC, R1
 Memory Address Register(MAR): It holds the address of an operand/location that needs to be
accessed. For example:
Move LOC, R1
When above instruction is being executed, the value needs to be fetched from memory. So
address of “LOC” is stored in MAR so that value from this location can be read and put into
register R1.
 Memory Data Register(MDR): It holds the data to be written to/read from memory. For
example:
Move R1, LOC
The contents of R1 need to be moved to LOC memory location. So, R1 register contents are
first moved to MDR then the address of LOC is moved to MAR and the move instruction is
executed so that value stored in MDR is written to “LOC” memory location.

Let’s look in details the operation steps:

 Step 1: The first line of code needs to be executed, so the address where the line of code
resides is placed in MAR.
 Step 2: Read control signal is issued a line of code (ex: Move LOC, R1) is copied into MDR.
 Step 3: The contents of MDR are moved to IR.
So, by Step3 the instruction that needs to be executed has been fetched and stored in IR, now
this instruction needs to be executed.

Let “Add LOC, R1” be the instruction. Let’s see how this is executed.
 Step 4: If the instruction involves memory access, the address of operand (ex: address of LOC)
is stored in MAR.
 Step 5: Then read signal is issued and the contents of memory (i.e. value stored in LOC) are
copied to MDR.
 Step 6: The value in MDR is passed to ALU to perform the operation (Add in the above
example)
 Step 7: If the result needs to be stored back in memory then the output is put back in MDR and
the location of memory is placed in MAR and “write” signal is executed to write back the result
to memory.

Interrupt:
 There are scenarios when normal execution needs to be interrupted to handle situation that needs
immediate attention. In such a scenario an interrupt signal is generated and an appropriate routine
called interrupt service routine is executed.

 Since an interrupt, interrupts normal execution of a program, the current values of PC, registers and
control information(flags) are backed up/ saved before executing an interrupt service routine (ISR).
When the ISR execution is over the values of PC, registers and control information are restored.

1.4 Bus Structures

 All the units (I/O, Processor, memory) are connected to each other by many parallel wires/lines called
bus.

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 These lines carry
 Data
 Address (of say memory location)
 Control information(read/write)
 Single bus architecture

 Single Bus Architecture:

In single bus architecture all devices are connected to a single bus. So, at any point only two
units/devices can communicate with each other.

 Each device operates at its own speed. Electromechanical devices like keyboard, printer
operate at low speeds compared to magnetic and optical disks. Optical disks and magnetic
disks are slower compared to memory and processor speeds.
However, all these operate over common bus. Hence a control/synchronization mechanism is
required to coordinate these devices that operate at varying speeds.

 Generally, buffers are used to manage the devices operating at different speeds. Ex:when the
processor needs to print a character on printer, first the character is placed in printer buffer. This
frees up the bus and processor to perform its operation. The printer reads the character from the
buffer and prints it.

1.5Performance
The performance of a computer is how quickly it can execute programs. In this section performance of
process, we consider only those periods of time when the processor is active.This is also called
processor time.This processor time depends on the hardware that is involved in execution of machine
instructions. The pertinent/relevant parts that impact the processor time are in fig 1.5.
 When execution of program is about to begin, the program is loaded to memory(main memory)
 One instruction at a time is moved from main memory into the process via bus.
A copy of it is stored in cache. When the instruction is being executed operands are read from
memory(ex: LOC) and placed in register. A copy of it is stored in cache for possible re-reading for
future instruction.
Hence, “cache memory” speeds up the program execution.Since it is within the processor, access
time to cache is much less compared to memory(main memory) access.

1.5.1 Processor Clocks

 Processor circuits are controlled
by a timing signal called a clock.
 A clock defines a regular time
interval called clock cycle.

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 A machine instruction (ex: Move Loc, R1) is divided into many basic steps and each step is
executed within a clock cycle.
 The length/duration of clock cycle plays a very important role and impacts the processor
performance.
 Inverse of clock cycle is clock rate(R): R= 1/P
Clock rate is measured in cycles per second.
 In new processors the clock rate ranges from few hundred million cycles per second i.e.
Hertz(Hz). For example:
500 million per second =500 MHz
1250 million cycles per second = 1.2GHz
Clock period for above two are 2 and 0.8 nanoseconds (ns)

1.5.2 Basic Performance Equation

Let
T = Processor time required to execute the complete program written in high level language.
N= Number of machine instructions executed to complete the execution of the program
S= Average number of steps required to execute one machine instruction.
R=Clock Rate R cycles per second.
N ×S
Hence, T =
R
Hence, if processor time required to execute a program needs to be less(i.e. T should be less) then
either N or S should be less or R should be more.
 N will be less if source program can be converted to fewer machine instructions
 S can be less if instruction can be executed in fewer basic steps.
 If a high frequency clock is used, then R will be high.
In all the above cases T will be less and hence processor performance will be high.

1.5.4 Clock Rate: (R)

Clock rate can be increased in two ways
(a) Improve the Integrated Technology to make logic circuits faster and hence time needed to execute
basic step is reduced.
(b) Reduce the amount of processing done in one basic step which in turn results in increase in clock
rate(R) and a reduction in P (where P is the length of one clock cycle).

1.5.7 Performance Measurement

 In order to compare computer architectures and measure performance certain benchmarks are
used.
 A nonprofit organization called System Performance Evaluation Corporation(SPEC) has developed
programs from different application domains. They have published results for many commercial
available computers.
 The programs range from
 Game Playing
 Compilers
 Database Applications
 Numerically Intensive Programs(example: astrophysics, quantum chemistry)
 The program is compiled on target devices and tested.The results are compared with reference
device(ex:SPEC95 uses SUN SPARC station 10/40; For SPEC2000 uses ULTRA SPARC 10
workstation with 300 MHz ULTRA SPARC- III Processor)

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 The SPEC rating is computed as:
Running time on reference computer
SPEC rating=
Running time on computer under test
So a value of 50 on spec rating indicates test device is 50 times faster than the reference device.
The tests are done for all programs (ex: gaming, database, numerically intensive programs etc.)
and final rating is arrived as
n 1
SPEC rating=( ∏ SPEC i ) n
i=1
Where “n” is the number of programs run. A spec rating gives combined rating for entire
system(i.e. memory, processor, compiler, operating system etc.)

M1.2: Machine Instructions and Programs

1.6 Memory Locations and Addresses
 Each bit is stored in a “cell” within the memory of a computer. So, a bit sequence like “0111” will be
stored in 4 cells with each cell containing a 0 or 1.
Dealing with each cell is a tough job and unnecessary. Hence, we consider with a group of bits of
fixed size called “word”. A group of “n” bits is called a word.
 Modern computers are machines which are called 16-bit, 32-bit or 64-bit machines. A 32-bit
machine operates on words which are 32bits long. So, a single word stores 32-bit 2’s complement
number or 4 ASCII characters of 8-bits length.

Specific example of a 32-bit word

Four ASCII characters can fit in a 32- bit word

 A unit of 8-bits is usually called byte

 A machine instruction could be composed of multiple 32-bit words
 Accessing Memory:
 When we want to read a 32-bit word or even a byte, we need to know the address of the
memory.
 A 2-bit system can address 4 memory location that stores say one byte of information each.

00 0 0 1 0 1 1 0 1
01 0 1 1 0 1 1 0 1
10 0 0 0 1 0 0 0 1
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So, to access the numbers”00010001”, we access the address location 10. This memory has
only 4 location & hence it is a 2-bit addressing system.
 A 4-bit system has 24 locations 0-15, So 16 words can be stored.
 Similarly, a 24-bit system has 2 24 locations in memory i.e.: 16,777,216 locations and each
could store a byte or a word. We can also call 224 locations as 16 M of memory
 Similarly, a 32-bit system has an address space of 4G (4 Giga) locations. Each location could
store 8 bits or 32-bit word.

0 1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0

1.6.1 Byte Addressability:

 There are 3- terms we have come across till now
a. Bit
b. Byte – 8 bits make a byte
c. Word – multiple bytes make up a word (ex: 32-bit word has 4 bytes)
 So, we can address a memory at bit level, or byte level or word level.
 The most practical way of assigning is to refer to memory as successive bytes’ location.
This way of addressing memory in terms of bytes is called Byte-Addressable Memory.
 Byte locations have address 0,1,2,3….
 Since a word is a set of multiple bytes, in a 32-bit machine a word address will be 0,4,
8...
 We can also visualize the memory at word level

0 0 1 2 3
4 4 5 6 7
8 8 9 10 11
12 12 13 14 15

1.6.2 Big-Endian AND Little-Endian Assignment

Let’s take a 32-bit word as given below:

8 bits 8 bits 8 bits 8 bits

 byte 0   byte 1   byte 2   byte 3 
This word can be stored in two ways in memory, namely
a. Big Endianb. Little Endian
a) BIG- ENDIAN
In this system the lower byte of memory stores the higher order byte (i.e. byte 0). We can
visualize it as below:

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b) LITTLE ENDIAN
In this system, the lower byte of memory stores the lower order byte(byte 3). We can
visualize it as below:

Example for Big Endian and Little Endian

Consider a 32-bit integer (in hex): 0xabcdef12. It consists of 4 bytes: ab, cd, ef, and 12.
Hence this integer will occupy 4 bytes in memory. Say we store it at memory address
starting 1000. The way this value gets stored in little endian and big endian is as below:

Little Endian Big Endian

Address Value Address Value

1000 12 1000 ab
1001 ef 1001 cd
1002 cd 1002 ef
1003 ab 1003 12

1.6.3 Word Alignment

If a word is 32-bit long and if the word boundaries occur at address 0, 4, 8, 12… etc. then we say
that the words have aligned address ex: word1 0-3 bytes, word 2  4-7 bytes, word 3 8-11
bytes.
Unaligned address: However, if a word (say, a 32-bit word) does not align at word boundaries 0, 4,
8, etc., then such words are called unaligned words.
Ex: word 1 2-5 bytes, word 2  6-9 bytes etc.

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1.6.4 Accessing Numbers, Characters and Character Strings

Numbers: A number can occupy one word of memory. It can be accessed (read/write) using the
address of the word.
Character: A character occupies one byte of memory. We can access a character by specifying the
byte address of the character.
Character String: A character string is a sequence of characters. The beginning of the string is
indicated by giving the address of beginning character.The ending of the string is
indicated by 2 ways:
Method 1: add a special character ex: “\0” to indicate the character string ends
Method 2: store the length of the string along with the string to indicate the length
of character string.

1.7 Memory Operations

Every program contains 2 things and both of them are stored in memory:
(a) Program instructions
(b) Data Operands

Let’s take a “C” program as an example

void main()
{
int a=5, b=7, c;
c=a + b;
}

In the above program

(a) c= a+b is a program instruction. This instruction needs to be stored in memory.
(b) The variables of instructions i.e. “a” and “b” themselves store some value i.e. “5” & “7”
respectively. Hence, “a” & “b” need some memory to store values.

To manage the instruction as well as data, two basic operations involving memory are needed:

i. Load
 Load operation transfers a copy of a memory (instruction or data) to the processor. The contents
of memory do not change (only a copy of it is transferred to processor).
 To perform the load operation, the processor sends the memory address and the data to be
readfrom the memory.
ii. Store
 Store operation transfers an item of information from processor to a specific memory location.
The previous content of that memory location is over written.
 To perform the store operation, the processor sends the memory address and the data to be
written to the memory.
Note:
i. An information item that is transferred between a memory location & a processor could be either
a word or a byte.
ii. A processor contains registers with each register size equal to the length of the word. Hence,
when a load or store operation is done, content of these registers are operated upon.

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1.8 Instructions and Instruction Sequencing:

A computer generally performs four types of operations:

(a) Transfer data between the Memory &Processor

(b) Arithmetic and Logic operations on data.
(c) Program Sequence & Control
(d) I/O transfers

To understand these, we first define some notations:

1.8.1 Register Transfer Notation

Data could be transferred between memory location, processor register &special registers in memory
system.

 A memory location could be identified by a symbolic name like LOC and a register could be
identified by names like R0, R5.
 I/O register may be identified by names like DATAIN, OUTSTATUS.
 Ex: R1 [LOC], this expression means the content of location “LOC” is copied to R1.
 Ex: R3  [R1] + [R2], this expression means add the contents of R1 register and contents of R2
register and store it in R3.
 This notation is called Register Transfer Notation(RTN).
 Note: Right hand side of notation is always a value and left hand side of notation is a
location(register/memory).
 Value of a location/register is represented by []. Forexample, [R1] means value stored in register
R1.

1.8.2 Assembly language Notation

 To represent the machine instructions, we use another notation called “assembly language”.
 Generally, a “C” program is first converted to assembly language

RTN Assembly Language

R1 [LOC] Move LOC,R1
R3 [R1] + [R2] Add R1,R2,R3

1.8.3 Basic Instruction Type:

There are four types of instructions
 Three address instruction
 Two address instruction
 One address instruction
 Zero address instruction

Three Address Instruction:

 In ‘C’ program when we perform some operation like C = A + B, we are trying to add the contents of
A & B & store it in C.
 This can be represented in RTN as C  [A] + [B].
 The corresponding assembly language instruction is Add A, B, C.

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 This instruction is called a three address instruction where A & B are “source operands” and ‘C’ is
the destination operand. In general, a three address instruction is shown as:
Operation source1,source2,destination
 If k-bits are required to specify an address and p-bits for operation, then the length of the instruction
would be represented as:

Operation Source1, Source 2, destination

 p bits   k bits   k bits   k bits 

Hence, total bits to store this type of instruction in memory is 3k + p bits.

Two Address Instruction:

 An instruction that works with two operands is called a two address instruction
Ex: RTN Assembly Instruction
C<- [B] Move B, C
 A three address operation like Add A,B,C can be represented in multiple two address instructions as
below:
Assembly Instruction RTN
Move B, C C  [B]
Add A, C C  [A] + [C]
We first move the control of B to C. Then the value in C we add the value of A. This is same as Add
A, B, C.

One Address Instruction:

 In a one address instruction, only one operand is specified. ex: Load A

In case of one address instruction, the other operand is a standard register called “Accumulator
register”. So, when we execute “Load A”, then the content of memory location “A” is loaded to the
accumulator register.

 We can do the 3-instruction operation. Add A,B,C using multiple one Address instruction as below:

RTN Description

Load A Raccum[A] Copy A’s data to accumulator register

Add B Raccum[Raccum] + [B] Add B’s data to accumulator register
& store it in register
Store C C[Raccum] accumulator register content is stored

 In case of one address instruction, based on the operation being done, a memory location could be
a source location or destination location. For example:
Load A : A is a source location
Store C : C is a destination location
 Some CPUs/Processors have the luxury of many registers. These registers (R1, R2, …. Rn) are
closest to the processor, so if an operation involves registers it will be very fast.
Ex: Add Ri, Rj Rj [Ri] + [Rj]
Will execute very fast because all operands are registers.
 Instruction to transfer content is of two types “Move” & “Load”. If one of the operands is a register,
then it’s better to use “Move” rather than “Load”
 In some processors operations can be performed only on registers. In such processor the content
from memory is first moved to registers. Before performing the operation.
Ex: If we want to do C <= A + B with only registers it is done as:

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Move A, Ri Ri [A]
Move B, Rj Rj [B]
Add Ri, Rj Rj[Ri] + [Rj]
Move Rj, C C  [Rj]
 In some processors if the flexibility is there to have one memory location as an operand, then the
C<-A + B can be represented as:

Move A, Ri Ri [A]

Add B, Ri Ri [B] + [Ri]
Move Ri ,C C [Ri]

Zero Address Instructions:

Some CPU’s store the operands on a special structure called push down stack. In this case, zero
address instructions are possible.

1.8.4 Instruction Execution and Straight Line Sequencing:

In this section, we will see the following:
a) How instruction execution happens using Program Counter(PC) and Instruction register(IR).
b) Meaning of straight line sequencing.

In the previous section, we saw how C  [A] + [B], was written as

Move A, R0
Add B, R0
Move R0, C

These instructions are stored in the RAM before they are executed on the processor as shown below:

In the above representation,we can note the following:

 Program that does the addition is stored in 3 contiguous word locations, named as program
segment.
 The program uses memory locations A, B and C, which are again stored in the Data part of the
program.
 Each instruction is assumed to occupy one word of 32 bits (that’s why the instruction starts at i, i+4
& i+8).

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 There is a special register called as “Program Counter (PC)”. It points to the instruction being
executed.So, when the program starts executing PC points to address i, i.e. the value stored in PC
register is address i.
 The execution of this program happens in two phases:
Phase 1: Instruction Fetch
The Program Counter (PC) points to the instruction to execute. The processor picks the content
locatedorpointed to by PC (i.e. Move A, R0) and dumps it into another special register called
“Instruction Register (IR)”. This phase is called Instruction Fetch.

Phase 2: Instruction Execute

In this phase, the operation to be performed is identified (Move, Add etc.). The required operands
are fetched (Ex: value from memory location A). Then, the operation is executed and finally the
result is stored (ex: Add B, R0).

Note:

 All these steps are for one operand like Add B, R0. When phase 2 is going on PC moves to the next
word (i.e. say from “i” to “i+4”). So by the time phase 2 is done, PC would have moved to next
instruction and phase 1 & phase 2 are repeated for the next instruction.
 This method of executing one instruction after another from start to finish is called straight line
sequence. (The other method of execution is branching, discussed in the next section).

1.8.5 Branching
Let us assume that we need to add “n” numbers NUM1 to NUMn and store the result in a variable
SUM, the code and corresponding data can be written as shown below:

Instead of doing it in straight line fashion, it can also be done as:

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 The variable N stores the number of times SUM operation needs to be performed (i.e. n)
 Register “R0” stores the intermediate sum as it keeps getting added. Final result is stored in SUM.
 The looping block is shown in the brace “{“. In the looping block the next “NUM” is fetched from
memory & added to Register “R0”. The variable R1 is then decremented by 1.
 A special instruction is executed called “Branch >0 Loop”, what this instruction means is that, if the
result of the instruction above it (i.e. Decrement R1) resulted in a value> 0 then go back to “Loop”,
else go to next instruction, i.e. “Move R0,SUM”.
 So, this special instruction is called a “branch instruction” and the place where we branch i.e. “Loop”
is called “branch target”. Since branching is based on a condition that R1 > 0, the branching is also
called “conditional branching”.

1.8.6 Conditional codes:

Processor has a special register called as “condition codes register” or “status register”. This register is a
set of flags. Each flag has a special meaning.
Four out of these flags are:

Flag Description
N(negative) set to 1 if result is negative, otherwise cleared to 0
Z(zero) set to 1 if result is 0, otherwise cleared to 0
V(overflow) set to 1 if arithmetic overflow occurs, otherwise cleared to 0.
C(Carry) set to 1 if a carryout results for the operation, otherwise cleared to 0.

Let’s take each one of them

 V(Overflow)
 Suppose,we add two numbers as below:
0111 (7)
+ 0001 (1) both numbers are in 2’s complement
----------------------
1000 (-8)!!! (overflow occurred)

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So, addition of two +ve numbers results in a negative number, because there was an overflow into the
MSB bit. As soon as this overflow occurs, the overflow bit in this special “condition code register”
becomes 1 to indicate that overflow occurred.Programmer can check this bit and add special code to
handle overflow. A special instruction “Branch If Overflow” is provided to handle this.

 Carry (C)
 Suppose, we add two numbers as below:
1001 (-7)
1111 (-1) Both numbers in 2’s complement
11000 (-8) overflow occurred
The last bit was an overflow. There is no space for this bit. This bit is stored in the “carry bit of
special register” (condition code register). Again, the programmer can check this bit and handle the
bit accordingly.

 Zero (Z)
This bit gets set, if the result of an arithmetic operation is 0.
Ex: If “LOC” memory location had 1.

Move LOC,R1
Decrement R1
When we execute “Decrement R1”, the value of R1 becomes 0, at this point the zero flag in the
special register becomes 1.
Now, how is this helpful? Let’s take an example.
Let LOC be a memory location that store 2

MOV LOC,R1 (R1 has value 2)

Loop Decrement R1
Branch > 0 Loop
<next instruction>

Initially, LOC has 2 and this is copied to location R1. Then, decrement R1 reduces the value by 1.
So, R1 = 1. When the instruction “Branch > 0” is executed; it checks the “zero flag” in the special
register. Since, it has not been set it jumps back to “LOOP” & “Decrement R1” is executed again.
Now, R1 becomes 0. At this point the “zero flag” has been set. So, we do NOT jump to loop,instead
“<Next instruction>” is executed.
It is like coming out of “for” loop in a C program.

 N(negative):
If an arithmetic or logical operation results in a negative answer, this flag bit in special register is set.
Programmer can test for this flag and handle the scenario of negative answer.
Let’s take an example. Consider, LOC variable to hold value 0, then

MOV LOC,R1
Loop Decrement R1
Branch > 0 Loop
<next instruction>

Initially R1 has 0. When “decrement R1” is done, the value of R1 becomes “-1”. At this point, the
negative bit (N) is set to 1 in the special register. So, when “Branch > 0 Loop” instruction is executed,
it checks the “zeroflag” AND “negative flag”. Since negative flag is set, it will NOT jump to loop,instead
“Next instruction” is executed.

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1.9 Addressing Modes

1.9.1 Addressing Modes Definition
The different ways in which the location of an operand is specified in an instruction are referred to
as addressing modes.

Mode 1: Immediate Mode

In immediate mode, the operand is given explicitly in the instruction.
Example 1: Move #200,R0
The above instruction places 200 in register R0.
Example 2: In C language we do something like A=B + 6 in assembly language. The same
statement is executed as:

Move B,R1
Add #6,R1 // Immediate Mode
Move R1,A

The add operation uses immediate mode to add number “6” to the value of B.

Mode 2: Register Mode

The operand is the contents of a processor register, the name (address) of the register is given in the
instruction.
i.e. if one of the operand is a register then the mode is called Register Mode
Ex: Move LOC, R2

Mode 3: Absolute Mode

The operand is a memory location; the address of this location is given explicitly in the instruction (it is also
called Direct Mode)
Ex: Move LOC, R2

1.9.2 Mode 4: Indirect Mode (Indirection & Pointers)

When we add two operand values using one of the following instructions:

Add R1, R0 (If R1 = 5 and R0 = 10 then finally R0 = 10 + 5 = 15)

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OR

Add A, R0 (If A = 5 and R0 = 10 then finally R0 = 10 + 5 = 15)

In the first case “5” is stored in R1 which is directly added to Register R0. Similarly, in 2 nd case “5” is stored
in memory and it is added directly to R0.

But what if “R1” stores address to a memory location that has the value “5” in it. The Instruction to
represent this is as below. Register R1 stores the address of memory location B which had the value “5”
stored in it. This method of accessing data is called “Indirect Mode”

Add (R1), R0

Indirect mode can occur through memory location as well as shown below. The below instruction means
that the memory location “A” contains the address of memory location “B” and the value at memory location
“B” is added to register R0.

Add (A), R0

Indirect Mode definition: The effective address of the operand is the contents of a register or a memory
location whose address appears in the instruction.

Note: Parenthesis is used to refer operands accessed that are accessed in indirect mode.
Note: The register or memory location that contains the address of an operand is called a pointer.

Example 1:
Let us see an example of adding n numbers using a pointer:

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In the above program, Add (R2), R0 will add the contents of memory pointed to by register R2 withthe
register R0, and the instruction “Add #4,R2” is executed, then R2 points to next location which has next
number to be added to R0 (provided the index in R1 has not reached 0).

Example 2: In a “C” program, the instruction A = *B, copies the value pointed to by pointer B into variable
A. The above can be done in assembly language in two ways:
Method 1:
Move B, R1
Move (R1), A
Method 2:
Move (B), A
Note: Method 2 seems simple but it is rarely used. Method 1 is generally preferred by processor designers,
apparently it is faster.

1.9.3 Mode 5: Index Mode (Indexing and Arrays)

Index Mode: The effective address of the operand is generated by adding a constant value to the contents
of register.
Analogy in “C” program: int p = arr[20];
What the above statement means is that, to the base address of the array “arr”, add 20 and you will get the
address from where the value should be picked and copied to “p”. Similarly, in terms of registers the same
can be expressed as X(Ri).
What the above statement means is that, to the value stored in register Ri, add X to get the address in the
memory, then from that location, pick the operand.

Effective Address EA = [Ri] + X

There are two possibilities:

Possibility 1: Register contains base address
Ex: Add 20(R1), R2
In this case, we shall add the value stored at location 1020 with the value in Register R2. Register R1
contains base address 1000.

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Hence, when Add 20(R1),R2 instruction is executed, then the following steps happen:

Step 1: 20 is added to R1 register value 1000 to get 1020.

Step 2: Value stored in location 1020 is picked
Step 3: This value is added to the value stored in register R2.

Possibility 2: Register contains offset address

Ex: Add 1000(R1), R2//R1 contains offset 20

In this case, we shall add the value stored at location 1020 with the value in Register R2. Register R1
contains the offset 20.

Hence, when Add 1000(R1), R2 instruction is executed, then the following steps happen:

Step 1: 1000 gets added to the register value 20 to get 1020.

Step 2: Value stored in location 1020 is picked
Step 3: This value is added to the value stored in register R2

Example 3: We have a student database with following fields: Student ID, Test 1 marks, Test 2 marks and
Test 3 marks as shown below:

Student ID Test 1 Test 2 Test 3

Calculate the total of Test 1, calculate Total of Test 2 and calculate Total of Test 3.
Solution: The aim is to separately add all the Test 1 score, Test 2 score & Test 3 score.
If there are “n” students in the class, let us list the student details for all students one after the other in the
memory as shown below:

Points to note: Each Student details occupies 4 words = 4 x 4 bytes = 16 bytes.

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So, student1 details take “LIST” to “LIST + 15”
Student2 details take “LIST + 16” to “LIST + 31” and so on…
 Consider the base address of student as LIST, then test1 details is obtained by adding 4 to LIST, the
test2 details by adding 8 to LIST, the test3 details by adding 12 to LIST.
 To jump from student 1’s details to student 2’s details we need to add “16” to base address, i.e. LIST +
16 onwards gives the student 2 details.
 The code for the program is below:

Move R3, SUM3

To understand the above code, we can divide the code into 3 parts:
Part 1: Initialization
Move #List, R0 makes R0 contain base address of the student array
Clear R1, Clear R2, Clear R3 makes R1, R2, R3 to 0.
R1, R2, R3 will be used for temporary calculations.
Move N, R4 makes R4 contain N (no. of students)
Part 2: Calculation
 Add 4(R0), R1: This means, to base address add 4 to reach Test1 marks of student1, then add it
to R1.Now, R1 contains 1st students test1 marks
 Add 8(R0), R2: This means, to base address add 8 to reach Test2 marks of student 1. Add the
marks to R2. Now, R2 contains 1st students test2 marks.
 Add 12(R0), R3: This means to base address add 12 to reach Test3. Now, R3 contains 1 st
students Test3 marks.
 Add #16, R0: R0 was pointing to 1st student’s base address. When we add 16 to it, R0 now jumps
to 2nd student’s base address.
 Decrement R4 to indicate we are done with 1st student.
 Now repeat part 2 again, since R0 now points to 2nd student, we will end up adding 2ndstudent’s
marks to 1st student.
 Again when we do Add #16, R0 we will jump to 3 rd student and add 3rd student’s marks to that of
2nd& 1st.
 This goes on till “Decrement R4” results in 0 which means we are done with all students.
Part 3: At this point, R1 has the sum of Test 1 marks of all students, R2 has the sum of Test 2 marks of all
students, R3 has the sum of Test 3 marks of all students.
Move R1, SUM1 // Copies the contents of R1 to SUM1
Move R2, SUM2 // Copies the contents of R2 to SUM2
Move R3, SUM3 // Copies the contents of R3 to SUM3.

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Note: In all the examples, we were using a register to store base address & the index value was being
specified directly. Example: Add 4(R0), R1
The constant can also be stored in a register. In which case the operand looks as (Ri, Rj)

Example: Add (R5, R0), R1

Where R5 can store the value 4, generally this is used for 2-D array manipulation.

Note: Another improvisation is that to the two register notation, we could add a constant value. This is
represented as X (Ri,Rj).

1.9.4 Mode 6: Relative Mode (Relative Addressing)

Relative Mode: The effective address is determined by the index mode using the program counter in place
of the general purpose register Ri, that is the relative mode is similar to index mode
discussed previously, but here the base address is specified by program counter (PC)
instead of some register Ri.

This is represented as X(PC)

(Note: index mode was represented as X(Ri)

1.9.5 Mode 7: Auto-increment mode:

Auto-increment mode: The effective address of the operand is the contents of a register specified in the
instruction. After accessing the operand, the contents of this register are automatically
incremented to point to the next item in a list.

In a “C” program, when we do “ptr++”, the pointer “ptr” jumps 4 bytes to point to the next integer (assuming
1 integer is 4 bytes). Similarly, there is an addressing mode that increments 1 byte, 2 (16-bit operands) or 4
bytes (32-bit operands).

The instruction is shown as (Ri)+, if Ri register points to an operand which is 32-bit, then (Ri)+ will move the
pointer by 4 bytes to the next word.

1.9.6 Mode 8: Auto-decrement mode

Auto-decrement mode: The contents of the register specified in the instruction are first automatically
decremented and then used as the effective address of the operand.
It is shown as –(Ri).
It is similar to Auto-increment except that
 The address is decremented first before using the value of the address, and
 It is a decrement operation.
The below program is to add “n” numbers using auto-increment operation.

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1.18: Additional Problems & Solutions

1) List the steps needed to execute the machine instruction “Add LOCA, R0” in terms of transfers
between the components shown in Figure (Connection between processor and memory) and some
simple control commands. Assume that the instruction itself is stored in the memory at location INSTR
and that this address is initially in register PC. The first 2 steps are expressed as:

 Transfer the contents of register PC to register MAR.

 Issue a read command to the memory and then wait until it has transferred the requested word into
the register MDR.

Remember to include the steps needed to update the contents of PC from INSTR to INSTR+1 so that the
next instruction can be fetched.

Solution:

 Transfer the contents of register PC to register MAR

 Issue a Read command to memory, and then wait until it has transferred the requested word into
register MDR
 Transfer the instruction from MDR into IR and decode it
 Transfer the address LOCA from IR to MAR
 Issue a Read command and wait until MDR is loaded
 Transfer contents of MDR to the ALU
 Transfer contents of R0 to the ALU
 Perform addition of the two operands in the ALU and transfer result into R0
 Transfer contents of PC to ALU
 Add 1 to operand in ALU and transfer incremented address to PC
2) Repeat Problem 1 for the machine instruction “Add R1,R2,R3”

Solution:
 First three steps are the same as in Problem 1
 Transfer contents of R1 and R2 to the ALU
 Perform addition of two operands in the ALU and transfer answer into R3
 Last two steps are the same as in Problem 1

3) A) Give a short sequence of machine instructions for the task: “Add the contents of memory location A
to those of location B, and place the answer in location C”. Instructions “Load LOC,Ri” and “Store
Ri,LOC” are the only instructions available to transfer data between the memory and GPR Ri. Do not
destroy the contents of either location A or B.

Solution:
Load A, R0
Load B, R1
Add R0, R1
Store R1, C

B) Suppose that Move and Add instructions are available with the format “Move/Add Location1,
Location2”. These instructions move or add a copy of the operand at the first location to the second
location, overwriting the original operand at the second location. Location i can be in either the memory
or the processor register set. Is it possible to use fewer instructions to accomplish the task in Part A? If
Yes, Give the sequence.

Solution:

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Yes.

Move B, C
Add A, C

4) A) Program Execution Time, T is to be examined for a certain high-level language program. The
program can be run on a RISC or a CISC computer. Both computers use pipelined instruction
execution, but pipelining in the RISC machine is more effective than in the CISC machine. Specifically,
the effective value of S in the T expression for the RISC machine is 1.2, but it is only 1.5 for the CISC
machine. Both machines have the same clock rate, R. What is the largest allowable value for N, the
number of instructions executed on the CISC machine, expressed as percentage of the N value for the
RISC machine, if time for execution on the CISC machine is to be no longer than that on the RISC
machine?

Solution:
Let TR = (NR * SR) / RR and TC = (NC * SC) / RC be execution times on the RISC and CISC processors,
respectively. Equating execution times and clock rates, we have

1.2 * NR = 1.5 * NC
Then
NC / NR = 1.2 / 1.5 = 0:8
Therefore, the largest allowable value for NC is 80% of NR.

B) Repeat Part A if the clock rate, R, for the RISC machine is 15 percent higher than that for the CISC
machine.

Solution:

In this case
1.2*NR / 1.15 = 1.5*NC / 1.00
Then
NC / NR = 1.2 / (1.15 * 1.5) = 0:696
Therefore, the largest allowable value for NC is 69.6% of NR.

5) A) Consider the concept of processor cache. Suppose the execution time for a program is directly
proportional to instruction access time and that access to an instruction in the cache is 20 times faster
than access to an instruction in the main memory. Assume that a requested instruction is found in the
cache with probability 0.96, and also assume that if an instruction is not found in the cache, it must be
first fetched from the main memory to the cache and then fetched from the cache to be executed.
Compute the ratio of program execution time with the cache. This ratio is usually defined as the
speedup factor resulting from the presence of the cache.

Solution:

Let cache access time be 1 and main memory access time be 20. Every instruction that is executed
must be fetched from the cache, and an additional fetch from the main memory must be performed for
4% of these cache accesses. Therefore,

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B) If the size of the cache is doubled, assume that the probability of not finding a requested instruction
there is cut in half. Repeat Part (A) for a doubled cache size.

6) How the performance of a computer is measured? Assuming that the reference computer is Ultra
SPARC10 workstation with 300MHz Ultra SPARC –III processor. A company has to purchase 500 new
computers, hence ordered testing of a new computer with SPEC2000 (run on reference as well as new
computer). Following observations were made.

Programs Runtime on reference computer Runtime in new computer

1 50 mins 5 mins
2 75 mins 4 mins
3 60 mins 6 mins
4 30 mins 3 mins

The company’s system manager will place the orders for purchasing new computers only if the overall
SPEC rating is at least 12. After the said test, will the system manger place order for the purchase of
new computers?

Solution:

i.e. geometric mean

SPECi = Runtime on the reference computer / Runtime on the computer under test

Therefore, SPEC1= 50/5=10

SPEC2= 75/4=18.75

SPEC3= 60/6=10

SPEC4= 30/3=10

Overall SPECrating = [10*18.75*10*10]1/4

= 11.70

Since the rating is 11.7 which is less than the benchmark rating 12, the purchase orders will not be
issued.

7. Write 1-address, 2-address & 3-address instructions for the following expressions:
a. Z = A + BCx + D
b. Y = Ax2 + Bx + C
Ans: (a)
One Address Two Address Three Address

Load B Mult B, C Mult B, #x, y

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Mult #x Mult #x, C Mult C, Y, C
Mult C Add C, D Add C, D, E
Add D Add D, A Add E, A, Z
Add A Move A, Z
Store Z

(b)
One Address Two Address Three Address

Load A Mult #x, B Mult #x, A, A

Mult #x Mult #x, A Mult #x, A, A
Mult #x Mult #x, A Mult #x, B, B
Store Z Add A, B Add A, B, E
Load B Add B, C Add C, E, Y
Mult #x Move C, Y
Add Z
Add C
Store Y

Exercise Problems from Chapter 2 (Text Book 1)

2.3 Given a binary pattern in some memory location, is it possible to tell whether this pattern represents a
machine instruction or a number?
Ans: No; any binary pattern can be interpreted as a number or as an instruction.
2.4 A memory byte location contains the pattern 00101100. What does this pattern represent when
interpreted as a binary number? What does it represent as an ASCII code?
Ans: The number 44 and the ASCII punctuation character “comma”.
2.5 Consider a computer that has a byte-addressable memory organized in 32-bit words according to the
big-endian scheme. A program reads ASCII characters entered at a keyboard and stores them in
successive byte locations, starting at location 1000. Show the contents of the two memory words at
locations 1000 and 1004 after the name “Johnson” has been entered.

Ans:
Byte contents in hex, starting at location 1000, will be 4A, 6F, 68, 6E, 73, 6F, 6E.
The two words at 1000 and 1004 will be 4A6F686E and 736F6EXX, Byte 1007 (shown as XX) is
unchanged.
Word
Byte Address
Address
1000 J o h n Write the hexadecimal values for each.
1004 S o n

Word
Byte Address
Address
1000 4A 6F 68 6E
1004 73 6F 6E XX

2.6 Repeat Problem 2.5 for the little – endian scheme.

Ans:

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Word Word
Byte Address Byte Address
Address Address
1000 n h o J 1000 6E 68 6F 4A
1004 XX n o s 1004 XX 6E 6F 73

2.8 Write a program that can evaluate the expression A x B + C x D in a single-accumulator processor.
Assume that the processor has Load, Store, Multiply, and Add instructions, and that all values fit in the
accumulator.
Ans:
Load A
Multiply B
Store RESULT
Load C
Multiply D
Add RESULT
Store RESULT

2.13 Registers R1 and R2 of a computer contain the decimal values 1200 and 4600. What is the effective
address of the memory operand in each of the following instructions?
(a) Load 20 (R1), R5
(b) Move #3000, R5
(c) Store R5, 30 (R1, R2)
(d) Add – (R2), R5
(e) Subtract (R1)+, R5
Ans:
(a) 1220
(b) Part of the instruction
(c) 5830 (4600+1200+30)
(d) 4599 (BYTE ADDRESSABLE)
(e) 1200 (POST INCREMENT)

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