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INTRODUCTION TO MICROPROCESSOR:

Microprocessors are regarded as one of the most important devices in our everyday
machines called computers. Before we start, we need to understand what exactly
microprocessors are and their appropriate implementations. Microprocessor is an
electronic circuit that functions as the central processing unit (CPU) of a computer,
providing computational control. Microprocessors are also used in other advanced
electronic systems, such as computer printers, automobiles, and jet airliners Typical
microprocessors incorporate arithmetic and logic functional units as well as the associated
control logic, instruction processing circuitry, and a portion of the memory hierarchy.
Portions of the interface logic for the input/output (I/O) and memory subsystems may also
be infused, allowing cheaper overall systems. While many microprocessors and
single-chip designs, some high-performance designs rely on a few chips to provide
multiple functional units and relatively large caches. When combined with other
integrated circuits that provide storage for data and programs, often on a single
semiconductor base to form a chip, the microprocessor becomes the heart of a small
computer, or microcomputer. Microprocessors are classified by the semiconductor
technology of their design (TTL,transistor-transistor logic; CMOS, complementary-metal-oxide
semiconductor; or ECL, emitter-coupled logic), by the width of the data format (4-bit,
8-bit, 16-bit, 32-bit, or 64-bit) they process; and by their instruction set (CISC,
complex-instruction-set computer, or RISC, reduced-instruction-set computer; see RISC
processor). TTL technology is most commonly used, while CMOS is preferred for
portable computers and other battery-powered devices because of its low power
consumption. ECL is used where the need for its greater speed offsets the fact that it
consumes the most power. Four-bit devices, while inexpensive, are good only for simple
control applications; in general, the wider the data format, the faster and more expensive
the device. CISC processors, which have 70 to several hundred instructions, are easier to
program than RISC processors, but are slower and more expensive.

Microprocessors have been described in many different ways. They have been compared
with the brain and the heart of humans. Their operation has been likened to a switched
board, and to the nervous system in an animal. They have often been called
microcomputers. The original purpose of the microprocessor was to control memory.
That is what they were originally designed to do, and that is what they do today.
Specifically, a microprocessor is “a component that implements memory.
A microprocessor can do any information-processing task that can be expressed, precisely, as
a plan. It is totally uncommitted as to what its plan will be. It is a truly general-purpose
information-processing device. The plan, which it is to execute—which will, in other words,
control its operation—is stored electronically. This is the principle of “stored program
control”. Without a program the microprocessor can do nothing. With one, it can do anything.
Furthermore, microprocessors can only perform information-processing tasks. To take action
on the outside world, or to receive signals from it, a connection must be provided between the
microprocessor’s representation of information (as digital electronic signals) and the real
world representation.

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4-BIT MICROPROCESSORS:
Historically, the 4-bit microprocessor was the first general-purpose microprocessor
introduced on the market. The basic design of the early microprocessors was derived from
that of the desk late 1971, the 4004 was originally designed for a Japanese manufacturer
as the processing element of a desk calculator; it was not designed as a general-purpose
computer. The shortcomings of the 4004 were recognized as soon as it was introduced.
But it was the first general-purpose computing device on a chip to be placed on the
market. Many of the chips introduced at about the same time by other companies were, in
fact, mere calculator chips. Some of them were even serial-by-bit devices, which
performed calculations a single bit at a time. The Intel 4004 chip took the integrated
circuit down one step further by placing all the parts that made a computer think (i.e.
central processing unit, memory, input and output controls) on one small chip.
Programming intelligence into inanimate objects had now become possible. The 4004
was the world's first universal microprocessor. In the late 1960s, many scientists had
discussed the possibility of a computer on a chip, but nearly everyone felt that integrated
circuit technology was not yet ready to support such a chip. Intel's Ted Hoff felt
differently; he was the first person to recognize that the new silicon-gated MOS
technology might make a single-chip CPU (central processing unit) possible.

8-BIT MICROPROCESSORS:
Today, 8-bit microprocessors coexist with 16-bit microprocessors as the design standard.
Although 16-bit chips provide higher performance computationally, 8-bit designs have more
than adequate power for many applications—plus the advantage of lower cost. As originally
design, most 16-bit microprocessors were limited to packages with a maximum of 40 to48
pins. This was not due to physical, but rather to economic, constraints: industrial tester of the
time was generally limited to 40-pin DIPs. The ancestor of today’s 8-bit microprocessors was
the Intel 8008, introduced in 1972-1973. The 8008 was not intended to be a general-purpose
microprocessor. IT was to be a CRT display controller for Data point. Taking into account all
of its design inadequacies and its limited performance, the 8008 was an overwhelming
success. (Bernstein, p.202)

INTEL (8-BIT MICROPROCESSORS) :

The 8080, designed as a successor to Intel’s 8008, was the first powerful microprocessor
introduced on the market. Several other microprocessors of similar performance were
introduced on the market within a year after the 8080 appeared, and several additional
powerful designs were introduced later. Technically, however, the 8080 long remained the
most powerful product on the market. Furthermore, Intel was the first company to invest in
the development of support chips and software for its products. This ensured the continued
success of the 8080 because its performance was then sufficient for many applications. The
early 8080 competitors were introduced with at least a nine-month delay and failed to
dislodge it. The 8080 is still sold today thought It has been largely eclipsed by successor
products—most notably the 8085 microprocessor. Today, the 8085 accounts for roughly one
of every four 8-bit microprocessors sold.

MICROCOMPUTER

 As the name implies, Microcomputers are small computers

 They range from small controllers that work directly with 4-bit words to larger
units that work directly with 32-bit words
 Some of the more powerful Microcomputers have all or most of the features
of earlier minicomputers.

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Examples of Microcomputers are Intel 8051 controller-a single board

computer, IBM PC and Apple Macintosh computer.
MICRO CONTROLLER

 Single-chip Microcomputers are also known as Microcontrollers.

 They are used primarily to perform dedicated functions.
 They are used primarily to perform dedicated functions or as slaves in
distributed processing.
 Generally they include all the essential elements of a computer on a single
chip: MPU, R/W memory, ROM and I/O lines.
 Typical examples of the single-chip microcomputers are the Intel 8051,
AT89C51, AT89C52 and Zilog Z8.
 Most of the micro controllers have an 8-bit word size, at least 64 bytes of
R/W memory, and 1K byte of ROM
I/O lines varies from 16 to 40

APPLICATIONS OF MICROPROCESSOR
 Microcomputers
 Industrial Control
 Robotics
 Traffic Lights
 Washing Machines
 Microwave Oven
 Security Systems
 On Board Systems

8085 Pin Diagram :

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The features of INTEL 8085 are:

• It is an 8 bit processor.
• It is a single chip N-MOS device with 40 pins.
• It works on 5 Volt dc power supply.
• The maximum clock frequency is 3 MHz while minimum frequency is 500
KHz.
• It provides 74 instructions with 5 different addressing modes.
• It has multiplexed address and data bus (AD0-AD7).
• It provides 16 address lines so it can access 216 =64K bytes of memory.
• It generates 8 bit I/O address so it can access 28=256 input ports.

ARCHITECTURE OF 8086:
Unlike microcontrollers, microprocessors do not have inbuilt memory. Mostly Princeton
architecture is used for microprocessors where data and program memory are combined
in a single memory interface. Since a microprocessor does not have any inbuilt
peripheral, the circuit is purely digital and the clock speed can be anywhere from a few
MHZ to a few hundred MHZ or even GHZ. This increased clock speed facilitates
intensive computation that a microprocessor is supposed to do.
We will discuss the basic architecture of Intel 8086 before discussing more advanced
microprocessor architectures.

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Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and 20-bit address bus. The
lower 16-bit address lines and 16-bit data lines are multiplexed (AD0-AD15). Since
20-bit address lines are available, 8086 can access up to 2 20 or 1 Giga byte of physical
memory.The basic architecture of 8086 is shown below.The internal architecture of Intel
8086 is divided into two units, viz., Bus Interface Unit (BIU) and Execution Unit (EU).

Bus Interface Unit (BIU )

The Bus Interface Unit (BIU) generates the 20-bit physical memory address and provides the
interface with external memory (ROM/RAM). As mentioned earlier, 8086 has a single
memory interface. To speed up the execution, 6-bytes of instruction are fetched in advance
and kept in a 6-byte Instruction Queue while other instructions are being executed in the
Execution Unit (EU). Hence after the execution of an instruction, the next instruction is
directly fetched from the instruction queue without having to wait for the external memory to
send the instruction. This is called pipe-lining and is helpful for speeding up the overall
execution process.
8086's BIU produces the 20-bit physical memory address by combining a 16-bit segment
address with a 16-bit offset address. There are four 16-bit segment registers, viz., the code
segment (CS), the stack segment (SS), the extra segment (ES), and the data segment (DS).
These segment registers hold the corresponding 16-bit segment addresses. A segment
address is the upper 16-bits of the starting address of that segment. The lower 4-bits of the
starting address of a segment is always zero. The offset address is held by another 16-bit
register. The physical 20-bit address is calculated by shifting the segment address 4-bit
left and then adding that to the offset address.

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8085 INSTRUCTION SETS :

a) Data Transfer Instructions
b) Arithmetic Instructions
c) Logical Instructions
d) Rotate Instructions
e) Branching Instructions
f) Control Instructions

a) Data Transfer instructions

Mnemonics Description Example

 Copies the content of source MOV A, B
register Rs into destination
MOV Rd, Rs register Rd
 Rs and Rd can be A, B, C, D,
E, H, L
 Copies the content of memory MOV A, M
location M into the
destination register Rd
MOV Rd, M  Rd can be A, B, C, D, E, H, L
 The memory location M is
specified by HL pair
 Copies the content of register MOV M, A
Rs into memory location M
MOV M, Rs  Rs can be A, B, C, D, E, H, L
 The memory location M is
specified by HL pair
 The 8-bit data is stored in the MVI A, 32H
destination register Rd
MVI Rd, 8-bit  Rd can be A, B, C, D, E, H, L

MVI M, 8-bit The 8-it data is stored in

 MVI M, 32H
memory location M
 M is specified by HL pair
LDA 16-bit  Copies the content of memory LDA 2015H

(Load Accumulator location specified by 16-bit A [2015 ]
Direct) address into A
STA 16-bit  Copies the content of A into STA 2015H

(Store Accumulator 16-bit memory address A [ 2015]
Direct)
Copies the content of
 memory LDAX B
location specified by
LDAX Rp register
(Load Accumulator pair Rp into A
Rp can be B or D i.e. BC
Inirect)  pair

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or DE pair
 Copies the content of A into STAX B
STAX Rp 16-bit memory address
(Store Accumulator specified by register pair Rp
Rp can be B or D i.e. BC
Indirect)  pair
or DE pair
Loads 16-bit data into
LXI Rp, 16-bit  register LXI H, 2015H

(Load Register Pair) pair L 15

 Rp can be B, D or H i.e. BC H 20
pair, DE pair or HL pair
IN 8-bit  The data from i/p port IN 40H

specified by 8-bit address is A [40]
transferred into A 40H is address
of input port
OUT 8-bit  The data of A is transferred OUT 10H
into output port specified by A[10]
8-bit address 10H is address
of output port
XCHG  Exchange the content of HL XCHG
pair with DE pair i.e. the HD

content of H and D are L E
exchanged whereas content
of
L and E are exchanged
b) Arithmetic
Instructions
Mnemonics Description Example
 The content of register ADD B

ADD R/M /memory (R/M) is added to A A+B
the A and result is stored in
(add A
register/memory)  The memory M is specified ADD M

by HL pair A A+M
 The content of register ADC B

ADC R/M /memory (R/M) is added to A A+B+CF
(add with carry) the A along with carry flag
CF and result is stored in A ADC M

 The memory M is specified A A+M+CF
by HL pair
ADI 8-bit  The 8-bit data is added to A ADI 32H

(add immediate) and result is stored in A A A+32
ACI 8-bit  The 8-bit data is added to A ACI 32H

(add immediate along with carry flag CF and A A+32+CF
with carry) result is stored in A
 The content of register SUB B

SUB R/M /memory (R/M) is subtracted A A-B

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(subtract from A and result is stored in

register/memory) A SUB M

 The memory M is specified A A-M
by HL pair
 The content of register SBB B

SBB R/M /memory (R/M) is subtracted A A-B-BF
(subtract with from A along with borrow
borrow) flag BF and result is stored in SBB M

A A A-M-CF
 The memory M is specified
by HL pair
SUI 8-bit  The 8-bit data is subtracted SUI 32H

(subtract from A and result is stored in A A-32
immediate) A
 Increment the content of INR B

INR R/M register/memory by 1 B B+1
(Increment  Memory is specified by HL
Register/Memory) pair INR M

M M+1
 Decrement the content of DCR B

DCR R/M register/memory by 1 B B-1
(Decrement  Memory is specified by HL
Register/Memory) pair DCR M

M M-1
INX Rp  Increment the content of INX H

(Increment Register register pair Rp by 1 HL HL+1
Pair)
DCX Rp  Decrement the content of DCX H

(Decrement register pair Rp by 1 HL HL-1
Register Pair)

c) Logical Instructions
Mnemonics Description Example
CMP R/M  Compares the content of CMP B
(Compare register/memory with A
Register/Memory)  The result of comparison is: CMP M
If A< R/M : Carry Flag CY=1
If A= R/M : Zero Flag Z=1
If A> R/M : Carry Flag CY=0
CPI 8-bit  Compares 8-bit data with A
(Compare  The result of comparison is:
Immediate)
If A< 8-bit : Carry Flag CY=1 CPI 32H
If A= 8-bit : Zero Flag Z=1
If A> 8-bit : Carry Flag CY=0

ANA R/M  The content of A are logically ANA B


(logical AND ANDed with the content of A A.B
register/memory) register/memory and result is ANA M

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stored in A

 Memory M must be specified A A.M
by HL pair
ANI 8-bit  The content of A are logically ANI 32H

(AND immediate) ANDed with the 8-bit data A A.32H
and result is stored in A
ORA R/M  The content of A are logically ORA B

(logical OR ORed with the content of A A or B
register/memory) register/memory and result is
stored in A ORA M

 Memory M must be specified A A or M
by HL pair
ORI 8-bit  The content of A are logically ORI 32H

(OR immediate) ORed with the 8-bit data and A A or 32H
result is stored in A
XRA R/M  The content of A are logically XRA B

(logical XOR XORed with the content of A A xor B
register/memory) register/memory and result is
stored in A XRA M

 Memory M must be specified A A xor M
by HL pair
XRI 8-bit  The content of A are logically XRI 32H

(XOR immediate) XORed with the 8-bit data A A xor 32H
and result is stored in A

d) Rotate Instructions
Mnemonics Description Example
RLC  Each bit of A is rotated left by RLC
(Rotate one bit position.
Accumulator Left)  Bit D7 is placed in the
position of D0.
RRC  Each bit of A is rotated right RRC
(Rotate by one bit position.
Accumulator Right)  Bit D0 is placed in the
position of D7.
RAL  Each bit of A is rotated left by RAL
(Rotate one bit position along with
Accumulator Left carry flag CY
with Carry)  Bit D7 is placed in CY and
CY in the position of D0.
RAR  Each bit of A is rotated right RLC
(Rotate by one bit position along with
Accumulator Right carry flag CY.
with Carry)  Bit D7 is placed in CY and

Branching Instructions
Mnemonics Description Example
JMP 16-bit The program sequence is transferred JMP C000H

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(Unconditional to the memory location specified by

Jump) 16-bit address
JC Jump on Carry (CY=1)
JNC Jump No Carry (CY=0)
JP Jump on Positive (S=0)
JM Jump on Negative (S=1)
JZ Jump on Zero (Z=1)
JNZ Jump No Zero (Z=0)
JPE Jump on Parity Even (P=1)
JPO Jump on Parity Odd (P=0)
CALL 16-bit The program sequence is transferred CALL C000H
to the subroutine at memory location
specified by the 16-bit address
RET The program sequence is transferred RET
from the subroutine program to
calling program

f)Control Instructions
Mnemonics Description Example
NOP No operation is performed NOP
HLT The CPU finishes executing the HLT
current instruction and stops any
further execution

MACROS Vs PROCEDURES
Procedure:
- Only one copy exists in memory. Thus memory consumed is less.
- Called when required
- Return address (IP or CS:IP) is saved (PUSH) on stack before transferring control to the subroutine
through CALL instruction. It should be popped (POP) again when control comes back to calling
program with RET instruction.
- Execution time overhead is present because of the call and return instructions.
- If more lines of code, better to write a procedure than a macro.

Macro:

- When a macro is invoked, the corresponding code is inserted into the source. Thus multiple copies
of the same code exist in the memory leading to greater space requirements.However, there is no
execution overhead because there are no additional call and return instructions.
No use of stack for operation.
- Good if few lines of code are in the Macro body.

INTERRUPTS :
Interrupt is considered as an emergency signal to which the MP responds as soon as
possible. When the microprocessor receives an interrupt signal, it suspends the
current executing program and jumps to an interrupt service routine (ISR) to respond
to the incoming interrupt When a device interrupts, it actually wants the
microprocessor to give a service which is equivalent to asking the microprocessor to
call a subroutine. This subroutine is call Interrupt Service Routine (ISR).

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SOURCES OF INTERRUPTS
There are three sources of interrupts and they are as follows:
1. Processor Interrupt
2. Software Interrupt
3. Hardware Interrupt

Processor Interrupt
These interrupts are generated by processor itself, usually in response to an error
condition. For example: In 8086 Type 0 interrupt occurs when attempt to divide by
zero which is a processor interrupt.
Software Interrupt
These are special instructions that trigger an interrupt response to processor.
In 8086 the general form of software interrupt instruction is INT nnH (eg: INT 21H)

Hardware Interrupt
Hardware interrupts are interrupt request initiated by external hardware.
8086 have two pins reserved for hardware interrupts. They are NMI and INTR

CLASSIFICATIONS OF INTERRUPTS
Interrupts can be classified as:
 Maskable Interrupt or Non-Maskable Interrupt
 Vectored Interrupt or Non-Vectored Interrupt
Maskable Interrupt
 The interrupts which can be blocked or delayed by using instructions
are called maskable interrupts.
 In 8085, the RESET interrupts (RST 5.5, RST 6.5 and RST 7.5) and
INTR are maskable interrupts. They can be enabled/disabled by using
instructions EI/DI.
In 8086, INTR is maskable interrupt. It can be enabled/disabled
by using instructions STI/CLI.

Non-Maskable Interrupt
 Those interrupts which cannot be blocked by instructions are termed
as non-maskable interrupts.
 In 8085, TRAP is only non-maskable interrupt and it is used for power
failure and emergency cutoff.
In 8086, NMI is non-maskable interrupt.

Vectored Interrupt
 The interrupts for which address of ISR is already known to MP
are called vectored interrupts.
 In 8085, RESET interrupts (RST 5.5, RST 6.5 and RST 7.5) are
vectored interrupts.
Interrupt Vector Address (Hex)
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C

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Non-Vectored Interrupt
 In non-vectored interrupts, the interrupting device needs to supply the
address of the ISR to the microprocessor.
 In 8085, INTR is non-vectored interrupt.

8085 INTERRUPTS
8085 microprocessor consists of five interrupt signals: INTR, RST 5.5, RST 6.5, RST
7.5 and
TRAP

1. INTR (Interrupt Request)

 The INTR is only non-vectored interrupt.
 INTR is maskable interrupt and can be masked by using EI
(Enable Interrupt)/DI (Disable Interrupt) instruction pair.
 INTR can be used for external hardware interrupts for various
applications.
2. RESET Interrupts
 8085 consists of three reset interrupts: RST 5.5, RST 6.5 and RST 7.5
 They are vectored interrupts whose address are defined in
interrupt vector table
 They are maskable interrupts and can be enabled or disabled
individually by using RIM and SIM instructions.
Interrupt Vector Address (Hex)
TRAP 0024
RST 5.5 002C
RST 6.5 0034
RST 7.5 003C
Fig: 8085 Interrupt Vector Table
3. TRAP
 It is only non-maskable interrupt of 8085 MP.
 It is a vectored interrupt whose address is defined in interrupt vector
table.
 It is used as external hardware interrupt source and is used for
power failure and emergency shutoff instruction.
8086 INTERRUPTS
 An 8086 interrupt can come from any one of 3 sources.
 One source is an external signal applied to the Nonmaskable Interrupt (NMI)
or to the (INTR) input pin. An interrupt caused by a signal applied to one of
these inputs (NMI or INTR) is referred as Hardware Interrupt.
 A second source of an interrupt is execution of the interrupt instruction INT
nn. This is referred as Software Interrupt.
 The third source of an interrupt is some error conditions produced in 8086,
by the execution of an instruction, referred as processor interrupt.

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INTERRUPT VECTOR TABLE (IVT)

 8086 consists of 256 interrupts stored from memory location 00000H to
003FFH i.e. 1024 Bytes (1KB) of memory.
 These 256 interrupts are stored in memory location forming a table which is
called Interrupt Vector Table (IVT).
 An Interrupt Vector contains the address (segment CS and offset IP) of the
Interrupt Service Routine.
 Each vector is a 4 byte long and contains the starting address of the Interrupt
Service Routine.
 The first 2 bytes of the vector contain the offset address (IP) and the last two
bytes contain the segment address (CS).

DIVIDE BY ZERO INTERRRUPT: TYPE 0

 Divide error occurs when the result of division overflow or whenever an attempt is
made
to divide by zero.
 The 8086 type 0 is automatic and cannot be disabled in any way

2. SINGLE STEP INTERRUPT : TYPE 1

 If the 8086 trap flag is set, the 8086 will automatically do a type 1 interrupt after
each instruction executes.
 When a MP is interrupted using Type 1 interrupt, it will execute one instruction
and stop so that we can then examine the contents of registers and memory
locations.
In other words, in single step mode, a system will stop after it executes each
instruction and waits for further direction from us.

3. NON MASKABLE INTERRUPT : TYPE 2

 A result of placing logic 1 on the NMI input pin causes type 2 interrupt.

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 This input is non-maskable, which means that it cannot be disabled.

 Another common use of type 2 interrupt is to save program data in case of a
system power failure or to deal with some other catastrophic failure conditions.
Some external circuitry detects when the AC power to the system fails and sends
an Interrupt signal to the NMI.

PRIORITY OF 8086 INTERRUPTS

INTERRUPTS PRIORITY
DIVIDE ERROR, INT n , INTO HIGHEST
NMI
INTR
SINGLE STEP LOWEST

PRIORITISING INTERRUPTS
1. Polled Interrupts
A polling procedure is used to identify the interrupt source having the highest
priority. Only one branch address is used for all interrupts.
The priority of each interrupt source determines the order in which it is polled. The
source with the highest priority is tested first, and if its interrupt signal is on, control
branches to a routine that services that source. Otherwise, the source with the next
lower priority is tested, and so on.
2. Vectored Interrupt
A vectored interrupt unit functions as an overall manager in an interrupt system
environment. The unit accepts interrupt requests from many sources, determines
which request has the highest priority, and issues an interrupt request to the computer
based on this determination. To speed up the operation, each interrupt source has its
own interrupt vector address to access its own service routine directly.

Figure: Vectored Interrupt

Operation:
1. All devices that can request an interrupt are connected serially and in priority
order with the highest priority device placed first on the daisy chain, farthest from
the CPU, and the lowest priority device placed last and closest to the CPU.
2. First, any (or all) of the devices signal an interrupt on the Interrupt Request line.

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3. Next, the CPU acknowledges the interrupt on the Interrupt Acknowledge line.
4. A device on the line passes the Interrupt Acknowledge signal to the next lower
priority device only if it has NOT requested service.
5. The first device on the priority chain requiring service asserts it interrupt vector
address (VAD) on the CPU data bus.
6. The CPU services the device
7. The Interrupt Acknowledge signal is passed to the next lower priority device and
steps 2 –6 are performed for the next lower priority device.
DIRECT MEMORY ACCESS 8237 CONTROLLER:

Introduction: Direct Memory Access (DMA) allows devices to transfer data without
subjecting the processor a heavy overhead. Otherwise, the processor would have to copy each
piece of data from the source to the destination. This is typically slower than copying normal
blocks of memory since access to I/O devices over a peripheral bus is generally slower than
normal system RAM. During this time the processor would be unavailable for any other tasks
involving processor bus access. But it can continue to work on any work which does not
require bus access. DMA transfers are essential for high performance embedded systems
where large chunks of data need to be transferred from the input/output devices to or from the
primary memory.

DMA Controller: A DMA controller is a device, usually peripheral to a CPU that is

programmed to perform a sequence of data transfers on behalf of the CPU. A DMA controller
can directly access memory and is used to transfer data from one memory location to another,
or from an I/O device to memory and vice versa. A DMA controller manages several DMA
channels, each of which can be programmed to perform a sequence of these DMA transfers.
Devices, usually I/O peripherals, that acquire data that must be read (or devices that must
output data and be written to) signal the DMA controller to perform a DMA transfer by
asserting a hardware DMA request (DRQ) signal. A DMA request signal for each channel is
routed to the DMA controller. This signal is monitored and responded to in much the same
way that a processor handles interrupts. When the DMA controller sees a DMA request, it
responds by performing one or many data transfers from that I/O device into system memory
or vice versa. Channels must be enabled by the processor for the DMA controller to respond
to DMA requests. The number of transfers performed, transfer modes used, and memory
locations accessed depends on how the DMA channel is programmed. A DMA controller
typically shares the system memory and I/O bus with the CPU and has both bus master and
slave capability. Fig.16.1 shows the DMA controller architecture and how the DMA
controller interacts with the CPU. In bus master mode, the DMA controller acquires the
system bus (address, data, and control lines) from the CPU to perform the DMA transfers.
Because the CPU releases the system bus for the duration of the transfer, the process is
sometimes referred to as cycle stealing.

In bus slave mode, the DMA controller is accessed by the CPU, which programs the
DMA controller's internal registers to set up DMA transfers. The internal registers consist
of source and destination address registers and transfer count registers for each DMA
channel, as well as control and status registers for initiating, monitoring, and sustaining
the operation of the DMA controller.

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DMA Transfer Types and Modes :

DMA controllers vary as to the type of DMA transfers and the number of DMA channels they
support. The two types of DMA transfers are flyby DMA transfers and fetch-and-deposit
DMA transfers. The three common transfer modes are single, block, and demand transfer
modes. A DMA controller is a device, usually peripheral to a CPU that is programmed to
perform a sequence of data transfers on behalf of the CPU. A DMA controller can directly
access memory and is used to transfer data from one memory location to another, or from an
I/O device to memory and vice versa. When the DMA controller sees a DMA request, it
responds by performing one or many data transfers from that I/O device into system memory
or vice versa.

The second type of DMA transfer is referred to as a dual-cycle, dual-address, flow-through, or

fetch-and-deposit DMA transfer. As these names imply, this type of transfer involves two
memory or I/O cycles. The data being transferred is first read from the I/O device or memory
into a temporary data register internal to the DMA controller. The data is then written to the
memory or I/O device in the next cycle. Fig.5.11 shows the fetch-and-deposit DMA transfer
signal protocol. Although inefficient because the DMA controller performs two cycles and
thus retains the system bus longer, this type of transfer is useful for interfacing devices with
different data bus sizes. For example, a DMA controller can perform two 16-bit read
operations from one location followed by a 32-bit write operation to another location. A
DMA controller supporting this type of transfer has two address registers per channel (source
address and destination address) and bus-size registers, in addition to 96the usual transfer
count and control registers.

DMA request remains high for additional transfers. DMA Request (I/O Device)
DMA Acknowledge* (DMA Controller) I/O Read. Unlike the flyby operation, this type
of DMA transfer is suitable for both memory-to-memory and I/O transfers.

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Fig 5.11 Fetch-and-Deposit DMA Transfer

8237 DMA controller IC :

Fig 5.12 pin diagram of 8237 DMA controller

VCC: is the +5V power

supply pin GND Ground

CLK: CLOCK INPUT: The Clock Input is used to generate the timing signals which
control 82C37A operations.

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CS: CHIP SELECT: Chip Select is an active low input used to enable the controller onto
the data bus for CPU communications.

RESET: This is an active high input which clears the Command, Status, Request, and
Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask
register is set to ignore requests. Following a Reset, the controller is in an idle cycle.

READY: This signal can be used to extend the memory read and write pulses from the
82C37A to accommodate slow memories or I/O devices.

HLDA: HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU
indicates that it has relinquished control of the system busses.

DREQ0-DREQ3: DMA REQUEST: The DMA Request (DREQ) lines are individual
asynchronous channel request inputs used by peripheral circuits to obtain DMA service.
In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A
request is generated by activating the DREQ line of a channel. DACK will acknowledge
the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes
these lines to active high. DREQ must be maintained until the corresponding DACK goes
active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs
should be pulled High or Low (inactive) and the corresponding mask bit set.

DB0-DB7: DATA BUS: The Data Bus lines are bidirectional three -state signals connected to
the system data bus. The outputs are enabled in the Program condition during the I/O Read to
output the contents of a register to the CPU. The outputs are disabled and the inputs are read
during an I/O Write cycle when the CPU is programming the 82C37A control registers.
During DMA cycles, the most significant 8-bits of the address are output onto the data bus to
be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the
memory enters the 82C37A on the data bus during the read-from -memory transfer, then
during the write-to-memory transfer, the data bus outputs write the data into the new
memory location.
IOR: READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is
an input control signal used by the CPU to read the control registers. In the Active cycle,
it is an output control signal used by the 82C37A to access data from the peripheral
during a DMA Write transfer.
IOW: WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it
is an input control signal used by the CPU to load information into the 82C37A. In the
Active cycle, it is an output control signal used by the 82C37A to load data to the
peripheral during a DMA Read transfer.
EOP: END OF PROCESS: End of Process (EOP) is an active low bidirectional signal.
Information concerning the completion of DMA services is available at the bidirectional
EOP pin. The 82C37A allows an external signal to terminate an active DMA service by
pulling the EOP pin low. A pulse is generated by the 82C37A when terminal count (TC)
for any channel is reached, except for channel 0 in memory-to-memory mode. During
memory-to-memory
Transfers , EOP will be output when the TC for channel 1 occurs. The EOP pin is driven
by an open drain transistor on-chip, and requires an external pull-up resistor to VCC.
When an EOP pulse occurs, whether internally or externally generated, the 82C37A will

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terminate the service, and if auto-initialize is enabled, the base registers will be written to
the current registers of that channel. The mask bit and TC bit in the status word will be set
for the currently active channel by EOP unless the channel is programmed for
autoinitialize. In that case, the mask bit remains clear.

A0-A3: ADDRESS: The four least significant address lines are bidirectional three -state
signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the
control register to be loaded or read. In the Active cycle, they are outputs and provide the
lower 4-bits of the output address.

A4-A7: ADDRESS: The four most significant address lines are three-state outputs and
provide 4-bits of address. These lines are enabled only during the DMA service.

HRQ: HOLD REQUEST: The Hold Request (HRQ) output is used to request control of
the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a
software DMA request is made, the 82C37A issues HRQ. The HLDA signal then informs
the controller when access to the system busses is permitted. For stand-alone operation
where the 82C37A always controls the busses, HRQ may be tied to HLDA. This will
result in one S0 state before the transfer.

DACK0-DACK3: DMA ACKNOWLEDGE: DMA acknowledge is used to notify the

individual peripherals when one has been granted a DMA cycle. The sense of these lines
is programmable. RESET initializes them to active low.

AEN: ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper
8 address bits onto the system address bus. AEN can also be used to disable other system
bus drivers during DMA transfers. AEN is active high.

ADSTB: ADDRESS STROBE: This is an active high signal used to control latching of
the upper address byte. It will drive directly the strobe input of external transparent octal
latches, such as the 82C82. During block operations, ADSTB will only be issued when
the upper address byte must be updated, thus speeding operation through elimination of
S1 states. ADSTB timing is referenced to the falling edge of the 82C37A clock.
MEMR: MEMORY READ: The Memory Read signal is an active low three-state output
used to access data from the selected memory location during a DMA Read or a
memory-to-memory transfer.

MEMW MEMORY WRITE: The Memory Write signal is an active low three-state
output used to write data to the selected memory location during a DMA Write or a
memory-to-memory transfer.

NC: NO CONNECT: Pin 5 is open and should not be tested for continuity.

DMA Operation:
In a system, the 82C37A address and control outputs and data bus pins are basically
connected in parallel with the system buses. An external latch is required for the upper
address byte. While inactive, the controller’s outputs are in a high impedance state. When
activated by a DMA request and bus control is relinquished by the host, the 82C37A drives

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the busses and generates the control signals to perform the data transfer. The operation
performed by activating one of the four DMA request inputs has previously been programmed
into the controller via the Command,

Mode, Address, and Word Count registers. For example, if a block of data is to be transferred
from RAM to an I/O device, the starting address of the data is loaded into the 82C37A
Current and Base Address registers for a particular channel, and the length of the block is
loaded into the channel’s Word Count register . The corresponding Mode register is
programmed for a memory-to-I/O operation (read transfer), and various options are selected
by the Command register and the other Mode register bits. The channel’s mask bit is cleared
to enable recognition of a DMA request (DREQ). The DREQ can either be a hardware signal
or a software command. Once initiated, the block DMA transfer will proceed as the controller
outputs the data address, simultaneous MEMR and IOW pulses, and selects an I/O device via
the DMA acknowledge (DACK) outputs. The data byte flows directly from the RAM to the
I/O device. After each byte is transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The operation is then repeated for the next
byte. The controller stops transferring data when the Word Count register underflows, or an
external EOP is applied.

8255A PROGRAMMABLE PERIPHERAL INTERFACE:

The 8255A is a general purpose programmable I/O device designed for use with Intel
Microprocessors. It consists of three 8-bit bidirectional I/O ports (24I/O lines) that can
be configured to meet different system I/O needs. The three ports are PORT A, PORT
B & PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
Port B is same as PORT A or PORT B. However, PORT C can be split into two parts
PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the control word. The
three ports are divided in two groups Group A (PORT A and upper PORT C) Group B
(PORT B and lower PORT C). The two groups can be programmed in three different
modes. In the first mode (mode 0), each group may be programmed in either input
mode or output mode (PORT A, PORT B, PORT C lower, PORT C upper). In mode 1,
the second’s mode, each group may be programmed to have 8-lines of input or output
(PORT A or PORT B) of the remaining 4-lines (PORT C lower or PORT C upper)
3-lines are used for hand shaking and interrupt control signals. The third mode of
operation (mode 2) is a bidirectional bus mode which uses 8-line (PORT A only for a
bidirectional bus and five lines (PORT C upper 4 lines and borrowing one from other
group) for handshaking. The 8255 is contained in a 40-pin package, whose pin out is
given below:

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Fig 5.1 Pin diagram of 8255 PPI

Fig. 5.2 Block diagram of 8255 programmable peripheral interface

Functional Description: This support chip is a general purpose I/O component to interface
peripheral equipment to the microcomputer system bus. It is programmed by the system software
so that normally no external logic is necessary to interface peripheral devices or structures.

Data Bus Buffer: It is a tri-state 8-bit buffer used to interface the chip to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions by the

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CPU. Control words and status information are also transferred through the data bus buffer. The
data lines are connected to BDB of microprocessor

Read/Write and logic control: The function of this block is to control the internal operation of the
device and to control the transfer of data and control or status words. It accepts inputs from the
CPU address and control buses and in turn issues command to both the control groups.

Chip Select: A low on this input selects the chip and enables the communication between the 8255
A & the CPU. It is connected to the output of address decode circuitry to select the device when it
(Read). A low on this input enables the 8255 to send the data or status information to the CPU on
the data bus.

Write: A low on this input pin enables the CPU to write data or control words into the 8255 A. A1,
A0

port select: These input signals, in conjunction with the and inputs, control the selection of one of
the three ports or the control word registers. They are normally connected to the least significant
bits of the address bus (A0 and A1). Following Table gives the basic operation,
All other states put data bus into tri-state/illegal condition.

RESET: A high on this input pin clears the control register and all ports (A, B & C) are initialized
to input mode. This is connected to RESET OUT of 8255. This is done to prevent destruction of
circuitry connected to port lines. If port lines are initialized as output after a power up or reset, the
port might try to output into the output of a device connected to same inputs might destroy one or
both of them.

PORTs A, B and C: The 8255A contains three 8-bit ports (A, B and C). All can be configured in a
variety of functional characteristic by the system software.

PORTA: One 8-bit data output latch/buffer and one 8-bit data input latch.

PORT B: One 8-bit data output latch/buffer and one 8-bit data input buffer.

PORT C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This
port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch
and it can be used for the control signal outputs and status signals inputs in conjunction with ports A
and B.

Group A & Group B control: The functional configuration of each port is programmed by the
system software. The control words outputted by the CPU configure the associated ports of the
each of the two groups. Each control block accepts command from Read/Write content logic
receives control words from the internal data bus and issues proper commands to its associated
ports.

Control Group A – Port A & Port C upper

Control Group B – Port B & Port C lower
The control word register can only be written into No read operation if the control word register is
allowed.

Operation Description: Mode selection: There are three basic modes of operation that can be
selected by the system software.

Mode 0: Basic Input/output

Mode 1: Strobes Input/output
Mode 2: Bi-direction bus.

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When the reset input goes HIGH all poets are set to mode’0’ as input which means all 24 lines are
in high impedance state and can be used as normal input. After the reset is removed the 8255A
remains in the input mode with no additional initialization. During the execution of the program
any of the other modes may be selected using a single output instruction.

The modes for PORT A & PORT B can be separately defined, while PORT C is divided into two
portions as required by the PORT A and PORT B definitions. The ports are thus divided into two
groups Group A & Group B. All the output register, including the status flip-flop will be reset
whenever the mode is changed. Modes of the two group may be combined for any desired I/O
operation e.g. Group A in mode ‘1’ and group B in mode ‘0’.

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Add two 2-digit BCD numbers in memory location 2200H and 2201H and store the result in memory
location 2300H.

LXI H, 2200H

MOV A,M
INX H
ADD M
DAA
STA 2300H
HLT

Add two 4 digits BCD numbers in HL and DE register pairs and store the result in
memory locations 2300H and 2301H. Ignore carry after 16bit.

MOV A, L
ADD E
DAA
STA 2300H
MOV A, H
ADC D
DAA
STA 2301H
HLT
Problem statement: Subtract the BCD number stored in E register from the number
stored in D register.

Process: (i) Find 100’s complement of subtrahend

(ii) Add two numbers using BCD
addition

MVI A, 99H
SUB E
INR A
ADD D
DAA
HLT

Problem statement: WAP to convert the content of 5 memory locations starting

from 2000H into Binary code. Place the result in five memory locations starting
from 2200H.

LXI SP, 27FFH

LXI H, 2000H
LXI D, 2200H
MVI C, 05H

X: MOV A,M
CALL ASCII
STAX D
INX H
INX D
DCR C

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JNZ X
HLT

ASCII:CPI 3AH
JNC Y
SUI 37H
JMP Z

Y: SUI 30H
Z: RET

BINARY TO BCD CONVERSION

LXI SP,27FFH
LDA 6000H
CALL BIN2BCD
HLT

BIN2BCD: PUSH B
PUSH D
MVI B, 64H
MVI C,0AH
MVI D, 00H
MVI E,00H

STEP1: CMP B
JC STEP2
SUB B
INR E
JMP STEP1

STEP2: CMP C
JC STEP3
SUB C
INR D
JMP STEP2

STEP3: STA 6100H

MOV A,D
STA 6101H
MOV A,E
STA 6102H
POP B
POP D
RET

BCD TO BINARY CONVERSION

Problem statement: Convert a 2 digit BCD number stored at memory address

2200H into its binary equivalent number and store the result in memory location
2300H.

LDA add

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MOV B,A
ANI 0FH
MOV C,A
MOV A.B
ANI F0H
RRC
RRC
RRC
RRC
MOV B,A
XRA A
MVI D, 0AH
X: ADD D
DCR B
JNZ X
ADD C
STA 2300H
HLT

WAP to generate square wave from SOD pin.

LXI SP, 27FFH

LXI B, 1388H
BACK: MVI A, C0H
SIM
CALL DELAY
MVI A, 40H
CALL DELAY
DCX B
MOV A, C
ORA B
JNZ BACK
HLT
MVI D, FFH
DELAY: DCR D
JNZ DELAY
RET

WAP to calculate average of three numbers. Assume the numbers begins from
2200H.

LXI H, 2200H
MOV A, M
INX H
ADD M
INX H
ADC M
MVI B, 03
MVI D, 00
MVI E, 00
Y: SUB B
JC X

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INR D
JMP Y
X: ADD B
MOV E, A
HLT

WAP to generate Fibonacci series.

MVI D, 05H
MVI B, 00H
MVI C, 01H
X: MOV A, B
ADD C
MOV B, C
MOV C, A
DCR D
JNZ X
HLT

Write a program to sort given 10 numbers from memory location 2200H in the
ascending order.

Source program
MVI B, 09 : Initialize counter
START : LXI H, 2200H: Initialize memory pointer
MVI C, 09H : Initialize counter 2

BACK: MOV A, M : Get the number

INX H : Increment memory pointer
CMP M : Compare number with next number
JC SKIP : If less, don't interchange
JZ SKIP : If equal, don't interchange
MOV D, M
MOV M, A
DCX H
MOV M, D
INX H : Interchange two numbers
SKIP:DCR C : Decrement counter 2
JNZ BACK : If not zero, repeat
DCR B : Decrement counter 1
JNZ START
HLT : Terminate program execution

WAP to find the largest number in a block of data. The length of block is in memory
location 2200H and the block itself begins from location 2201H. Store the maximum
number in 2300H.

LDA 2200H
MOV C, A
XRA A
LXI H, 2201H
X: CMP M
JNC Y

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MOV A, M
Y: INX H
DCR C
JNZ X STA
2300H
HLT

Interfacing Examples:
Draw the circuit diagram of an 8085 system, having a 4 KB EPROM and two 8 KB RAM
ICs. The starting address of the EPROM is 0000H and that of RAM is 8000H. The
address of the decoder circuits should be clearly shown.
Answer :
EPROM-4 KB (Address lines required is 12 – A0
to A11) RAM-I-8 KB (Address lines required is 13
– A0 to A12) RAM-II-8 KB (Address lines
required is 13 – A0 to A12)

Mapping of Addresses to Memory Ics

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8086 Programs :

Program to add numbers input from keyboard------

.model small
.stack
.data
.code
main proc
.startup
mov ah,01h
int 21h
sub al,30h
mov bl,al ;store 1st number in bl
mov ah,01
int 21h
sub al,30h
add
al,b
l
push
al
jnc
SKIP
mov dl,
‘1’
mov
ah,02h
int
21h
SKIP: pop al
add
al,30
h mov
dl,al
mov
ah,02
h int
21h
.exit
main endp
end main

Program to concatenate two Strings

.model small
.stack
.data

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string1 db
'Microprocessor$' string2
db 'Assembly Language$'
string3 db ?
.code
main proc
.startup
mov di,offset
string3 mov
si,offset string1
mov cx,14
AGAIN1:
mov
bx,[si]
mov
[di],b
x inc
si
inc di
loop
AGAIN1
mov si,offset
string2 mov cx,18
AGAIN2:
mov
bx,[si]
mov
[di],b
x inc
si
inc di
loop
AGAIN2
.exit
main endp
end main

Program to change LOWERCASE string into UPPERCASE-----

.model small
.stack
.data
name1 db 'pokhara university$'
.code
main proc
.startup
mov dx,offset name1 mov ah,09h

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int 21h
mov cx,18
mov si, offset name1
UPPERCASE:
sub [si],20h ;note: to change UPPERCASE into lowercase add 20h
mov dl,[si] mov ah,02h int 21h inc si
loop UPPERCASE
.exit
main endp
end main

Program to input a string from keyboard and print it

in reverse order----------------

.model small
.stack
.data
string db ?
len db 10 ; length of string to be input
.code
main proc
.startup
mov cx, len
mov si, offset string
AGAIN:
mov ah, 01h int 21h
mov [si], al inc si
loop AGAIN
mov cx, len
REPEAT:
mov dl, [si] mov ah, 02h int 21h
dec si loop REPEAT
.exit
main endp
end main

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BUS STRUCTURE
In any microprocessor system, the system bus consists of a number of separate lines.
Each line is assigned a particular function. Fundamentally in any system, the system
bus can be classified into three functional groups: the address, the data and control
lines or buses.

Fig: Bus Structure

Data Bus
 The data bus provides path for transferring data between the microprocessor
system and the peripherals.
 The data bus consists of a number of separate lines, generally 8, 16, 32 or
64. The number of lines is referred as the width of the data bus.
 Since, each line carry only one bit at a time, the number of lines
determines how many bits can be transmitted at a time.
 The width of data bus is a key factor in determining the overall system
performance.

Address Bus
 The address bus which consists of a number of separate lines, are used to
designate the source or destination of the data on data bus. For example, if
the CPU requires reading a word (8, 16, 32 or 64 bits of data) from
memory, it put the address of the desired word on the address bus.
 The width of address bus (i.e number of lines) determines the maximum
possible memory capacity of the system.
 The address bus is also used to address IO ports.

Control Bus
 The control bus is a group of lines used to control the access to and the use of
the data and address bus since the data and address bus are shared by all
components of microcomputer system. Hence control bus provides a means of
controlling their use.
 The control bus carries the control signals. The control signals
transmit both command and timing information between the system
modules.

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 The timing signals indicate the validity of data and address information;
whereas the command signals specify the operations to be performed.
 Some control signals are: Memory Read, Memory Write, IO Read, IO Write,
Interrupt Request, Interrupt Acknowledge, Bus request, Bus Grant etc.
SYNCHRONOUS AND ASYNCHRONOUS BUS
Synchronous Bus
In a synchronous bus, the occurrence of the events on the bus is determined by a
clock. The clock transmits a regular sequence of 0’s and 1’s of equal duration. A
single 1-0 transition is called clock cycle or bus cycle and defines a time slot. All
other devices on the bus can read the clock live, and all events start at the beginning
of the clock cycle. In synchronous bus, all devices are tied to a fixed rate, and hence
the system cannot take advantage of device performance. It is easier to implement.

Asynchronous Bus
In an asynchronous bus, the timing is maintained in such a way that occurrence of
one event on the bus follows and depends on the occurrence of previous event.
Asynchronous bus are faster than the synchronous bus as the events are independent
of the processor timing.

Timing Diagram of MVI A,32H

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Timing Diagram of IN 84H

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Timing Diagram of
STA 8000H

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Opcode fetch

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Timing Diagram of OUT 01H

Polling versus Interrupt :

 Each time the device is given a command, for example ``move the read head
to sector 42 of the floppy disk'' the device driver has a choice as to how it finds
out that the command has completed. The device drivers can either poll the
device or they can use interrupts.
 Polling the device usually means reading its status register every so often until
the device's status changes to indicate that it has completed the request.
 Polling means the CPU keeps checking a flag to indicate if something
happens.
 An interrupt driven device driver is one where the hardware device being
controlled will cause a hardware interrupt to occur whenever it needs to be
serviced.
 With interrupt, CPU is free to do other things, and when something happens,
an interrupt is generated to notify the CPU. So it means the CPU does not need
to check the flag.
 Polling is like picking up your phone every few seconds to see if you have a
call. Interrupts are like waiting for the phone to ring.
 Interrupts win if processor has other work to do and event response time is not
critical.
 Polling can be better if processor has to respond to an event ASAP; may be
used in device controller that contains dedicated secondary processor.

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Advantages of interrupt over Polling :

1)Interrupts are used when you need the fastest response to an event. For
example, you need to generate a series of pulses using a timer. The timer
generates an interrupt when it overflows and within 1 or 2 sec, the interrupt
service routine is called to generate the pulse. If polling were used, the delay
would depend on how often the polling is done and could delay response to
several msecs. This is thousands times slower.

2)Interrupts are used to save power consumption. In many battery powered

applications, the microcontroller is put to sleep by stopping all the clocks and
reducing power consumption to a few micro amps. Interrupts will awaken the
controller from sleep to consume power only when needed. Applications of this
are hand held devices such as TV/VCR remote controllers.

3)Interrupts can be a far more efficient way to code. Interrupts are used for
program debugging.

1. External interrupts:
These interrupts are initiated by external devices such as A/D converters and
classified on following types.
 Maskable interrupt :
It can be enabled or disabled by executing instructions such as EI and DI. In
8085, EI sets the interrupt enable flip flop and enables the interrupt process.
DI resets the interrupt enable flip flop and disables the interrupt.
 Non-maskable interrupt:
It has higher priority over maskable interrupt and cannot be enabled or
disabled by the instructions.

2. Internal interrupts:
 These are indicated internally by exceptional conditions such as overflow,
divide by zero, and execution of illegal op-code. The user usually writes a
service routine to take correction measures and to provide an indication in
order to inform the user that exceptional condition has occurred.
 There can also be activated by execution of TRAP instruction. This interrupt
means TRAP is useful for operating the microprocessor in single step mode
and hence important in debugging.
These interrupts are used by using software to call the function of an operating
system. Software interrupts are shorter than subroutine calls and they do not
need the calling program to know the operating system’s address in memory.

Interrupt Pins and Priorities (Hardware interrupts) :

An external device initiates the hardware interrupts and placing an appropriate
signal at the interrupt pin of the processor.
If the interrupt is accepted then the processor executes an interrupt
service routine. The 8085 has five hardware interrupts
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

TRAP:
 This interrupt is a non-maskable interrupt. It is unaffected by any mask
or interrupt enable.

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 TRAP bas the highest priority and vectored interrupt.

 TRAP interrupt is edge and level triggered. This means hat the TRAP must
go high and remain high until it is acknowledged.
 In sudden power failure, it executes a ISR and send the data from main
memory to backup memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the
processor receives HOLD and TRAP at the same time then HOLD is
recognized first and then TRAP is recognized).
 There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External signal)
2. By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:
 The RST 7.5 interrupt is a maskable interrupt.
 It has the second highest priority.
 It is edge sensitive. ie. Input goes to high and no need to maintain high
state until it recognized.
 Maskable interrupt. It is disabled by,
1. DI instruction
2. System or processor reset.
3. After reorganization of interrupt.
 Enabled by EI instruction.

RST 6.5 and 5.5:

 The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high
and stay high until it recognized.
 Maskable interrupt. It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt.
 Enabled by EI instruction.

 The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:
 INTR is a maskable interrupt.
 It is disabled by,
1. DI, SIM instruction
2. System or processor reset.
3. After reorganization of interrupt.
 Enabled by EI instruction.
 Non- vectored interrupt. After receiving INTA (active low) signal, it has to
supply the address of ISR.
 It has lowest priority.
 It is a level sensitive interrupts. ie. Input goes to high and it is necessary to
maintain high state until it recognized.
 The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each
instruction.

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2. If INTR signal is high, then 8085 complete its current instruction and
sends active
Low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an
instruction OPCODE on the data bus. In the case of multibyte
instruction, additional interrupt acknowledge machine cycles are
generated by the 8085 to transfer the additional bytes into the
microprocessor.
4. On receiving the instruction, the 8085 save the address of next
instruction on
stack and execute received instruction.

Design an address decoding circuit for two RAM chips each of 256 bytes at
address 5300H.
256 bytes requires 8 address lines.
2x=256, x=8
So to address one of 256 bytes in each RAM requires 8 address lines A0-A7
A8 A7 A6 A5 A4 A3 A2
Block Address A15 A14 A13 A12 A11 A10 A9 A1 A0
1 Start 5300H 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0
End 53FFH 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1
2 Start 5400H 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0
End 54FFH 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1
Address Decoding Circuit:

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