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Cs202 Computer Organisation and Architecture, August 2021

The document outlines the examination structure for the Fourth Semester B.Tech Degree in Computer Organisation and Architecture at APJ Abdul Kalam Technological University. It includes various parts with questions on topics such as subroutine calls, addressing modes, memory organization, and microprogrammed CPUs. Each part contains questions of varying marks, requiring detailed answers and explanations.

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yabey63124
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0% found this document useful (0 votes)
15 views2 pages

Cs202 Computer Organisation and Architecture, August 2021

The document outlines the examination structure for the Fourth Semester B.Tech Degree in Computer Organisation and Architecture at APJ Abdul Kalam Technological University. It includes various parts with questions on topics such as subroutine calls, addressing modes, memory organization, and microprogrammed CPUs. Each part contains questions of varying marks, requiring detailed answers and explanations.

Uploaded by

yabey63124
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B 02000cs202052002

RegNo.:
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
Fourth Semester B.Tech Degree (S,FE) Examination August 202I (2015

Course Code: CS202


Course Name: COMPUTER ORGANISATION AND ARCHITECTURE (CS,IT)
Max, Marks: 100 uration: 3 Hours
PART A
Answer all questions, each curries 3 marks

\
I How are nested subroutine calls internally implemented in a computer? 3

2 Index addressing mode is useful in dealing with lists and arrays. Justify the 3

statement.

List the control signals that are activated while storing a word in memory using a 3

single bus organization


Design a 3x2array multiplier 3

PART B
Answer any two questions, each carries 9 marks
5a) Write notes on one address, two address and three address instructions with proper 5

examples.
,b) List and explain any 4 addressing modes with examples 4
16 a) Write a program that can evaluate the expression AxB+CxD in a single 5

accumulator processor. Assume that the processor has Load, Store, Multiply and
Add instructions, and that all values fit in the accumulator.
b) Divide 24by 7 using restoring division algorithm 4

7a) Draw and explain the flowchart of floating point multiplication algorithm 5

b) Explain multiple bus organization with the help of a diagram 4

PART C I
Answer all question, each carries 3 marks
8 List the functions of VO interface circuits. 3

9 Illustrate how various devices are addressed on the USB? J

a
10 What is MFC signal? How is it related to memory access time? J

a
1l With a neat diagram explain the structure of a synchronous DRAM J

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02000cs202052002

PART D
Answer any two questions, each carries 9 marks
12 a) program controlled I/O is performed using polling? 5
.How
b) Explain the working of a PCI bus with the help of timing diagrams. 4

13 a) Explain internal organization of memory chips with the help of a neat diagram. 5

b) Explain direct cache mapping with the help of an example. What are the issues 4

associated with direct mapping?


-
. 14 a) diagram.
Illustrate USB architecture and working with the help of a neat 5

b) ' Write notes on flash memory. List its advantages and disadvantages 4
; PART E
t

.I ,5 a) Draw the brock !,:{^:#:,#T:;f:::i:^:"#ri::::L':^:i:{,king register 5

transfer statement:

yTr: R, <- &, 4e R,

b) List and discuss about shift and logic microoperations. 5


' 16 Explain how control signals are generated using PLA control, using an example l0
with a neat diagram
17 Describe the basic organization of a microprogrammed CPU with the help of a l0
diagram
I 8 List and explain the different control organisations with the help of neat diagrams I0

19 a) Starting from an initial value of R=11011101, determine the sequence of binary 5

.1 values in R after a logical shift-Ieft, followed by a circular shift-right, followed by

. a logical shift-right and a circular shift left.

" b) Write notes on status register. 5

t
' Z0 Explain the design of accumulator. 10

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