What’s new in VHDL-2019

vhdlwhiz.com/vhdl-2019/

The VHDL Analysis and Standardization Group (VASG), has been working for quite some time on
finishing the draft for the upcoming VHDL-2019 revision of the language. The ballot has been held, and a
list of approved changes has emerged.

What’s left before this becomes the latest revision of the VHDL language is for the draft to be reviewed by
the IEEE Standards Review Committee. With their approval, IEEE 1076-2019 will become the official
standard.e

Unfortunately, work on the draft has been delayed*.

* Update (Feb 10th, 2020): The new VHDL standard was approved on Sept 5, 2019.
Purchase the 1076-2019 Language Reference Manual from IEEE.

VHDL-2017? VHDL-2018? VHDL-2019?

Due to the delay, what started off as VHDL-2017 is now VHDL-2018, and is likely to become VHDL-2019
before the standard is approved. This has led to a slight confusion about the name of the revision. Some
websites refer to it as VHDL-2017, others VHDL-2018, while VHDL-2019 might be the one that prevails.

1/18
VHDLwhiz has been in touch with Jim Lewis, chair of VASG, who is responsible for maintaining the VHDL
standard. Work on the revision has been delayed due to problems finding a person to edit using Adobe
Framemaker. Mr. Lewis says: «at this point it will be 1076-2019».

Highlights
Vendors who aim to support the bleeding edge of VHDL revisions must incorporate a long list of new
features and changes into their tools. So how can VHDL-2019 make your life better?

Here are some highlights of the upcoming VHDL-2019 revision:

For a more detailed description of the changes and new features, continue reading the rest of this post.

Approved changes
Each of the proposed changes can be identified by a Language Change Specification (LCS) number on
the format LCS-2016-NNN. The details can be viewed on the EDA wiki, but the rest of this section will
explain the implications of each LCS using straightforward examples and uncomplicated language.

Partially connected vectors in port maps

LCS-2016-001

This is a very welcome change which will serve to make module instantiation less annoying. Currently,
whenever you assign an interface array of mode out to a signal, you have to assign every bit of the array.
In VHDL-2019 you will be allowed to declare the subelements as unconnected by using the open
keyword:

1 i_MyModule : entity work.MyModule(rtl)

2 port map(
3 Port8(7 downto 4) => SlvNibble,
Port8(3 downto 0) => open
4 );
5

Similarly, you will be allowed to connect only selected bits of ports with mode in or generic ports. Of
course, there will still have to be a default value set in the port declaration.

This change isn’t functionally important, but it fixes something that has been irritating. You’ve had to
declare an intermediate signal to assign to a long port, only to leave half of the bits unused. Now we can
assign the shorter signal directly to the port, and leave the unused bits disconnected. Overall, it’s a
change that makes VHDL feel a bit more flexible.

Access, file, and protected types are now allowed as subprogram parameters in
protected types

LCS-2016-002, LCS-2016-004

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This change affects functions and procedures declared in protected types. They can now have
parameters that are access, file, and protected types.

Extensions to the file type

LCS-2016-006a

New subprograms for manipulating files have been added to the TEXTIO package.

New procedures:

FILE_REWIND: Move the position to the start of the file

FILE_SEEK: Move the position back or forth
FILE_TRUNCATE: Set the size of a file. Can be used for shrinking or growing files

New function:

FILE_STATE: Returns the state of a file, open or closed

FILE_MODE: Returns the mode of a file, read, write, etc.
FILE_POSITION: Returns the position of the file
FILE_SIZE: Returns the size of a file
FILE_CANSEEK: Returns true if seek is supported

Added read/write mode to file types. Previously, a file had to be opened either for reading or writing.
Now, you can get both.

New Directory API

LCS-2016-006c

New functions, procedures, and types for handling directories have been added to the ENV package. The
standard environmental package (ENV), which was introduced in VHDL-2008, has been extended with
subprograms for reading and writing in directories on the native filesystem.

New subprograms include:

1. DIR_OPEN: Open dir and return a record containing the directory items
2. DIR_CLOSE: Deallocate directory object.
3. DIR_ITEMEXISTS: Check if file or dir exists
4. DIR_ITEMISDIR: Check if the dir exists
5. DIR_ITEMISFILE: Check if the file exists
6. DIR_WORKINGDIR: Sets the working dir
7. DIR_CREATEDIR: Create a new dir
8. DIR_DELETEDIR: Deletes an empty dir
9. DIR_DELETEFILE: Delete a file

Read environment variables

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LCS2016_006e

Finally, this much-wanted feature will be implemented in VHDL. The ability to read environment variables
will be ensured by two new functions in the ENV package.

1 impure function GETENV(Name : STRING) return STRING;

2 impure function GETENV(Name : STRING) return LINE;

Standard environment awareness

LCS2016_006f

These additions to the ENV package will reveal things like VHDL version, tool type, and vendor. Definitely
useful functions to have when you are developing code that needs to be aware of such specifics.

1 impure function VHDL_VERSION return string ;

2 function TOOL_TYPE return string ;
3 function TOOL_VENDOR return string ;
4 function TOOL_NAME return string ;
5 function TOOL_EDITION return string ;
6 function TOOL_VERSION return string ;

Sequential block statement

LCS2016_007, LCS2016_007a

The block statement is an old feature in VHDL. It is used for separating logic within an architecture,
limiting the scope of signals to within the block. What is new in VHDL-2019 is that the block statement
can be used in sequential logic, within a process or subprogram.

A trivial example to illustrate such usage:

1 process is
2 variable MyVar : integer;
3 begin
4
5 InnerBlock : block
6 variable InnerVar : integer;
7 begin
8
9
10 end block ;
11
wait;
12
end process;
13
14

Date and time

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LCS2016_011

A set of new types and functions in the ENV package will give access to the local date and time.

New types are:

1 type DAYOFWEEK is (
2 SUNDAY, MONDAY, TUESDAY, WEDNESDAY, THURSDAY,
3 FRIDAY, SATURDAY
4 );
5
6 type TIME_RECORD is record
7 microsecond : INTEGER range 0 to 999_999
8 second : INTEGER range 0 to 61;
9 minute : INTEGER range 0 to 59;
10 hour : INTEGER range 0 to 23;
11 day : INTEGER range 1 to 31;
12 month : INTEGER range 0 to 11;
13 year : INTEGER range 1 to 4095;
weekday : DAYOFWEEK;
14
dayofyear : INTEGER range 0 to 365;
15
end record TIME_RECORD;
16
17

New subprograms include:

LOCALTIME: Local time

GMTIME: UTC time
EPOCH: Epoch time
TIME_TO_SECONDS: Convert to seconds in real
SECONDS_TO_TIME: Opposite conversion

Additionally, there are TO_STRING functions which will come in handy for logging purposes. They generate
string timestamps on the format “YYYY-MM-DDTHH:mm:ss”.

Even better, there exists overloaded + and - operators for incrementing or decrementing the
TIME_RECORD.

String representation of composite types

LCS2016_012

Through the T'image(X) attribute you will be able to get a string representation of composite types.
Records will convert into comma-separated strings within parentheses, such as ("1001000", '0', 0,
3.14).

Similarly, the T.value(X) attribute can be used to fill records with values stored in the string format. In
this case, extra spaces will be ignored.

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Composites of protected types

LCS2016_014

This change will allow the class-like objects of protected types to be stored in composite types. In other
words, you can create arrays with them, or they can be members of a record.

When passing a protected type as a parameter to a function, it shall be passed by reference. This means
that you can enjoy bouncing the class-like objects back and forth, just like you would do in any other
object-oriented programming language.

Access types to protected types

LCS2016_014a

With this change, the designated type of an access types can be a protected type. Access types in VHDL
are pointers to an object, and protected types are class-like constructs which you can create objects of. In
more regular programming language terms, VHDL already had both pointers and classes.

In VHDL-2019 you will be allowed to create pointers to objects of protected types. You will also be able to
create pointers to file types, as well as objects and file types that are composites of protected types.

Get calling path and stack info

LCS2016_015

This is an addition to the standard ENV package which lets you get call path information for the current
stack frame. By calling the GET_CALL_PATH function from the ENV package, a pointer to a vector of
records will be returned. The leftmost element in the record will be the current stack frame, while the
rightmost element is the root of the call stack.

The vector contains a record of the following type:

1 type CALL_PATH_ELEMENT is record

2 name : LINE;
3 file_name : LINE;
4 file_path : LINE;
file_line : POSITIVE;
5
end record;
6

The name element refers to the name of the current subprogram or construct. The other elements in the
record contain information about the calling position in the VHDL file.

Get current line and file

LCS2016_015a

Another addition to the ENV package. Six new functions that will get the name and path of the current
VHDL file, as well as the line number which is executing:

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 1 impure function FILE_NAME return LINE ;
2 impure function FILE_NAME return STRING ;
3 impure function FILE_PATH return LINE ;
4 impure function FILE_PATH return STRING ;
5 impure function FILE_LINE return POSITIVE ;
6 impure function FILE_LINE return STRING ;

Anonymous types in interface lists

LCS2016_016

This change allows anonymous types in interface list declarations, like ports or subprogram’s parameter
lists. Instead of specifying std_logic_vector or bit_vector, you will be able to write <>, which covers all
scalar types. The possible type categories are private, scalar, discrete, integer, physical, and floating.

Example usage of this feature:

1 Architecture A of E is
2 signal SigA : std_logic_vector(7 downto 0) ;
3 signal SigB : std_logic ;
4 component E is
5 port (
6 A : type is private ;
7 B : type is <>
8 ) ;
9 end component E ;
10
11 begin
12 E1 : E
13 port map (
A => SigA ;
14
B => SigB
15 ) ;
16 ...
17

Attributes for Enumerated Types

LCS2016_018, LCS2016_018a, LCS2016_018d

A number of new attributes have been defined for enumerated types:

‘LENGTH
‘RANGE
‘REVERSE_RANGE
‘IMAGE
‘POS
‘SUCC
‘PRED
‘LEFTOF

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 ‘RIGHTOF
‘INDEX[(N)]
‘DESIGNATED_SUBTYPE

Most of these attributes should be known to you already, as they have existed for scalar types before.
Now you can use them for enumerated types as well.

Infer signal and variable subtype constraints from initial value

LCS-2016-019

When dealing with ports of unconstrained types, defining signals and variables with derived types has
been cumbersome. This change is perhaps better explained with the example taken from here.

Currently, you must do this:

1 entity
2 port (
3 a_port : sfixed;
4 b_port : sfixed;
...
5
6
constant prod_proto : sfixed := a_port * b_port;
7
8
variable prod : prod_proto'subtype;
9
...
10
11 prod := a_port * b_port;
12
13
14

In VHDL-2019, you will be allowed to do this:

1 entity
2 port (
3 a_port : sfixed;
4 b_port : sfixed;
...
5
6
variable prod : sfixed := a_port * b_port;
7
8
...
9
10 prod := a_port * b_port;
11
12
13
14

Allow configuration and entity libraries to differ

LCS-2016-023

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Currently, entities must be defined in the same library as their configurations. This requirement has now
been relaxed.

Long integers

LCS-2016-026c

Finally, VHDL number types are catching up with the 21st century. The INTEGER type has been increased
from 32 to 64 bits.

Access external types through the library path

LCS-2016-028

This added language feature allows you to hierarchically reference a type or subtype. Hierarchical signal
access has been available since VHDL-2008 through the use of the << library_path >> construct. Now,
you can also reference types and subtypes by using the following syntax:

architecture_path_name ::= entity_simple_name ( architecture_simple_name)

This is useful in verification scenarios where the testbench needs to have access to a type that is
declared in the module. Usually, this is solved by declaring the type in a package common both the
testbench and the RTL module. Another way to solve this has been to redefine the type in the testbench.

With this change, it can be accomplished in the testbench by hierarchically referencing the type in the
module where it is declared:

alias extStateType is work.EntityName(ArchitectureName).StateType;

Garbage collection
LCS-2016-030

In the code below, there is a potential memory leak. In VHDL-2019, you won’t have to worry about that
because it has automatic garbage collection. As soon as the last reference to an object is lost, it shall be
deallocated.

1 function to_string (
2 value : in integer_vector
3 ) return string is
4 variable L : line;
5 begin
6 write(L, value) ;
7 return L.all ;
8 end function to_string ;

More explicit ‘PATH_NAME and ‘INSTANCE_NAME paths

9/18
LCS-2016-032

There are changes to the attributes for getting the hierarchy path of an object. They have been changed
to include the full package name and instance path, even when the object resides within a protected type.

This is useful, especially for algorithms that rely on having a unique string descriptor for an object. For
example RandomPck’s InitSeed procedure.

Public variable declaration in protected types and the PRIVATE keyword

LCS-2016-033

The word private has been added to the list of reserved words in VHDL.

Currently, the declarative region of protected types cannot include variable declaration. This is usually
solved by using getter and setter subprograms. Now, you can simply add the variable declarations to the
protected type declaration to make them public.

Furthermore, you can make a variable private by using the new private keyword. Then, you can expose
a member of the private variable by creating an alias for it:

1 package MyPkg... is
2 type MyPkg is protected
3 private shared variable Name : MyType;
4 alias SetMessage is Name.SetMessage [String];
5 alias WriteMessage is Name.WriteMessage;

Generics on protected types

LCS-2016-034

This change allows generics to be mapped to an object of protected type when a variable is created of it.
Kind of like the function template in C++, types can now be specified when creating the object. You can
avoid hard-coding types within the protected type, making them more versatile.

An example shared variable declaration using generics:

1 shared variable MyVar : MyType generic map (

2 InternalType => integer
3 );

Conditional assignment of initial values

LCS-2016-036a

Conditional assignments have previously been allowed for signals in the architecture of the VHDL file.
Now, you can use the same shorthand format within the declarative region as well.

10/18
It will be allowed to assign to constants conditionally like this:

constant T : time := 1 ns when GenericBoolean else 10 ns;

New ‘reflect attribute

LCS-2016-41

This change introduces a new 'reflect attribute to VHDL. Calling this attribute function will return a new
object of protected type, which has a copy of the current state of the object. The name of the new
protected type is VALUE_MIRROR.

Example code from the LCS:

1
2 process
3 type Rec is record
4 I : INTEGER_VECTOR(0 to 3);
5 R : REAL;
6 T : TIME;
7 end record;
8
9 constant test : Rec := (
I => (1, 3, 7, 9),
10
R => 3.14,
11 T => 25 ns
12 );
13
14 variable mirror : VALUE_MIRROR := test'reflect;
15 begin
16 report to_string(mirror);
17 wait;
18 end process;
19
20
21
22
23

New PSL attributes and functions

LCS-2016-43

The following functions have been added to the ENV package to make Property Specification Language
(PSL) more usable with VHDL:

11/18
 1 impure function PslAssertFailed return boolean ;
2
3 impure function PslIsCovered return boolean ;
4
5 procedure SetPslCoverAssert( Enable : boolean := TRUE) ;
6 impure function GetPslCoverAssert return boolean ;
7
8 impure function PslIsAssertCovered return boolean ;
9
10 procedure ClearPslState ;
11
12
13
14
15

Additional 'signal and 'event attributes have been added to PSL objects.

Separate modes for composite type members

LCS-2016-45a, LCS-2016-45b, LCS-2016-45c

Previously, we have been forced to give composite types in port declarations the same mode (in, out
e.g.) for all of its data members. Now, we can give modes to each individual member of records or arrays.
Thus, you can implement an interface using records without resorting to using the inout mode on every
entity where it’s used.

Two new mode keywords have been introduced in VHDL; view and null. The view mode enables
individual mode control of the composite type members. Example taken from the EDA wiki:

1 port(
2 rst_i : in std_logic;
3 clk_i : in std_logic;
4 cpu_bus_rif : view cpu_bus_r(
5 element(
6 arbiter_al : view arbiter_a(
7 element(
8 others : view arbiter_r;
element(
9
master_rl : in master_r;
10
bus_req_l : in std_logic;
11
bus_grnt_l : buffer std_logic
12

The null mode can be used to denote unconnected interface objects:

12/18
 1 port configuration SLAVE_pcfg is
2 generic(
3 SEL_jg : SEL_jst
4 );
port(
5 MASTER_rl : in;
6 SLAVE_al : composite(
7 SEL_jg : buffer;
8 others : null
9 )
10 );
11 end port configuration SLAVE_pcfg;
12

Shared variables on entities

LCS-2016-47

You will finally be allowed to send shared variables of protected type through entity ports. With this
change, you should be able to write some creative testing strategies, for instance, by passing
scoreboards passed between verification components.

Generics on subprograms
LCS-2016-49

Subprograms can now* have generics in addition to the normal parameter list. The advantage of this is
that you can pass types through the generic parameters, eliminating the need for an overloaded version
of the subprogram for each data type.

* Update (Feb 18th, 2021): Actually, generics on subprograms have existed since VHDL-2008. But
VHDL-2019 brought some refinements to the specification. See LCS-2016-49 in the EDA wiki.

Thanks to Richard from the comment section for the clarification!

Example taken from EDA wiki:

1 function Mux4
2 generic ( type DataType )
3 parameter (
4 MuxSel : in std_logic_vector(1 downto 0) ;
5 A, B, C, D : in DataType
6 ) return DataType is
7 . . .
8 end function Mux4;

New assert API utility subprograms

LCS-2016-50

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The following new subprograms have been added to the ENV package to help with assertion-based
verification in VHDL:

1 impure function IsVhdlAssertFailed return boolean ;

2 impure function IsVhdlAssertFailed (Level : SEVERITY_LEVEL ) return boolean ;
3
4 impure function GetVhdlAssertCount return natural ;
5 impure function GetVhdlAssertCount (Level : SEVERITY_LEVEL ) return natural ;
6
7 procedure ClearVhdlAssert;
8
9 procedure SetVhdlAssertEnable(Enable : boolean := TRUE) ;
10 procedure SetVhdlAssertEnable(Level : SEVERITY_LEVEL := NOTE; Enable : boolean :=
11 TRUE) ;
12 impure function GetVhdlAssertEnable(Level : SEVERITY_LEVEL := NOTE) return boolean ;
13
14 procedure SetVhdlAssertFormat(Level : SEVERITY_LEVEL; format: string) ;
15 procedure SetVhdlAssertFormat(Level : SEVERITY_LEVEL; format: string; Valid : out
16 boolean) ;
17 impure function GetVhdlAssertFormat(Level : SEVERITY_LEVEL) return string ;
18
19 procedure SetVhdlReadSeverity(Level: SEVERITY_LEVEL := FAILURE) ;
20 impure function GetVhdlReadSeverity return SEVERITY_LEVEL ;
21
22
23
24

Relax component end syntax

LCS-2016-55a

This change makes the end component; optional. Now, you can write just end;. The syntax has
previously been a bit inconsistent with the “entity” in end entity; being optional, while “component” was
mandatory in end component;.

Type class insurance for generic types

LCS-2016-59

This change allows arrays of generic types to be constructed of a preceding type on the same generic
port. Previously, types passed through a generic port could not be used as part of a subprogram or array
in the same generic port. Now, the type class (scalar, array, e.g.) will be determined before elaboration
time. Thus, attributes like 'length or 'range can also be used.

Example taken from the EDA wiki

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 1 entity mux
2 generic (
3 type ELEM;
4 type ARR is array (integer) of ELEM);
5 port (
6 inputs : in ARR;
7 select : in integer;
8 muxed : out ELEM);
9 end entity;

Use relational operators with arrays of scalar types as operands

LCS-2016-59a

In VHDL-2019, you will be allowed to use relational operators like = or < to compare arrays of scalar
types, for example integer.

Conditional analysis
LCS-2016-61

Much like the beloved C preprocessor, VHDL-2019 has the ability to include or exclude blocks of code
based on the value of a constant. Tools are required to support a syntax on the form:

1 `if G_MY_GENERIC then

2 attribute my_attribute_typ : string;
3 attribute an_attribute of my_attribute_typ: signal is "value";
4 `else
5 `end if
6

The possibilities are endless. You could set the constant in the VHDL code where the module is
instantiated, or it could be set from the TCL script, which starts the compilation or synthesis. Either way, it
enables you to drastically change the function of the module, making it more versatile.

Note that the “`” character is mandatory in front of all tool instructions. See Mr. Lehmann’s comment in the
comment section.

Optional trailing semicolon in interface lists

LCS-2016-71a

This is an unimportant change, but it is one that will save you a lot of time in the long run!

You know, when you make some changes to the entity of a module, perhaps you remove the last signal
from the interface list. Then, when you try to compile, you get the annoying near “)”: (vcom-1576)
expecting IDENTIFIER.” error because you forgot to remove the trailing semicolon from the second last
signal.

15/18
Now, a trailing semicolon after the last signal on the interface list has been made optional. You can do
this:

1 entity someEntity is
2 port
3 (
4 a : std_logic;
b : integer;
5
);
6 end entity;
7

Functions will have knowledge of the array bounds of the receiver of the return value
LCS-2016-72b

This change allows functions to access attributes belonging to the receiver of its return value. An
annoying side effect of not knowing anything about the signal that its return value is to be assigned to is
evident in the to_unsigned function:

x <= to_unsigned(i, x'length);

You have to include the array length of the receiver of the return value as a parameter because the
function has no way of knowing it. Now, you can simply do this:

x <= to_unsigned(i);

This is possible because the receiving signal can optionally be referenced from within the function.

It is not only limited to standard functions like to_unsigned. You can use this in your own custom
functions as well. The function specification has changed, the new optional handle of the receiver of the
return value is denoted in red:

function_specification ::=
[ pure | impure ] function designator
subprogram_header
[ [ parameter ] ( param_list) ] return [ return_identifier of ] type_mark

Implicit conversion of closely related record types

LCS-2016-75

An automatic cast from one record type to another if each element of the source record can be implicitly
converted to a matching element in the destination record.

An example of two closely related record types:

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 1 type SourceRec is record
2 a : natural;
3 b : real;
4 c : boolean;
5 end record;
6
7 type DestRec is record
d : integer;
8 e : real;
9 f : boolean;
10 end record;
11

Allow empty records

LCS-2016-82

Records with no data members will be allowed. Now you can kick off your design by specifying interfaces
as empty records before completing them at a later stage.

An empty record:

1 type MyRecord is record

2 end record;

Use interface objects later in the same interface list

LCS-2016-86

This allows you to use an object listed in an interface list, later in the same interface list to provide an
initial value or to access an attribute.

An example taken from the LCS:

1 entity E is
2 generic (G1: INTEGER; G2: INTEGER := G1; G3, G4, G5, G6: INTEGER);
3 port (P1: STRING(G3 to G4); P2: STRING(P1'RANGE); P3: P1'SUBTYPE);
4 procedure X (Y1, Y2: INTEGER; Y3: INTEGER range Y1 to Y2; Y4: Y1'SUBTYPE);
5 end E;

Conditional return statement

LCS-2016-94a

In VHDL-2019 you will be able to write return statements on the When-Else form instead of wrapping
them in If-Then-Elseif-Else statements. This is the new accepted format:

1 return (<expression 1>) when <condition 1> else

2 (<expression 2>) when <condition 2> else
3 (<expression N>);

17/18
Return statements are still mandatory in functions.

Range record

LCS-2016-99

Two new attributes have been defined, which can be applied to ranges. The first one is R'RECORD which
will get the range record type on the format:

1 type <unnamed_range_record> is record

2 Left : <scalar_type>;
3 Right : <scalar_type>;
4 Direction : DIRECTION;
5 end record;

The second attribute is R'VALUE which will retrieve the values for the given range. This feature will come
in handy for anyone who wishes to perform calculations on ranges of scalar types.

When can I start using VHDL-2019?

Even though VHDL-2008 has been around for quite a few years, not all tools support it yet. Most of the
new functionality and changes are not intended to be synthesizable. They are testbench features.
Therefore, the best we can hope for is that the simulator vendors will adopt VHDL-2019 before the end of
the decade.

The only simulator that claims to support VHDL-2019 is Aldec Riviera-PRO. Aldec refers to the standard
as “VHDL 2018”.

Update (Feb 10th, 2020): The new VHDL standard was approved on Sept 5, 2019.
Purchase the 1076-2019 Language Reference Manual from IEEE.

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