REL670
REL670
The software and hardware described in this document is furnished under a license and may be used or
disclosed only in accordance with the terms of such license.
This product includes software developed by the OpenSSL Project for use in the OpenSSL Toolkit
(https://www.openssl.org/). This product includes cryptographic software written/developed by: Eric
Young ([email protected]) and Tim Hudson ([email protected]).
Trademarks
ABB is a registered trademark of ABB Asea Brown Boveri Ltd. Manufactured by/for a Hitachi Energy
company. All other brand or product names mentioned in this document may be trademarks or
registered trademarks of their respective holders.
Warranty
Please inquire about the terms of warranty from your nearest Hitachi Energy representative.
Disclaimer
When the products and services provided by Hitachi Energy are designed to be connected to and
to communicate information and data via a network interface with Customer’s network or system
(Customer System), it is the sole responsibility of the Customer to provide and continuously ensure
a secure connection between the Customer’s System and Customer's network and any other network.
It is the sole responsibility of the Customer to establish and maintain any appropriate measures (e.g.,
the installation of firewalls, application of authentication measures, encryption of data, installation of
anti-virus programs, etc.) to protect the Customer’s System including its network and external interfaces
against any kind of security breaches, unauthorized access, interference, intrusion, leakage and/or theft
or losses of data or information. As necessary for the provision of work, the Customer will permit Hitachi
Energy’s employees, agents, consultants and/or subcontractors to remotely access certain systems
owned, controlled or operated by or on behalf of Customer.
Not withstanding any other provision to the contrary and regardless whether the contract is terminated or
not, Hitachi Energy, its subcontractors, its and their affiliates and its and their employees are under no
circumstances liable for and the Customer shall defend and indemnify said parties from and against any
claim for damages and/or losses related to any security breaches, unauthorized access, interference,
intrusion, leakage and/or theft or loss of data or information resulting from Customer’s failure to secure
Customer’s System. In the event a Security Incident on Customer’s System results in Hitachi Energy
Information being disclosed such that notification is required to be made under any applicable laws, or
pursuant to a request or directive from a governmental authority, Customer will coordinate with Hitachi
Energy prior to the disclosure as mutually agreed, except as required by applicable law.
The data, examples and diagrams in this manual are included solely for the concept or product
description and are not to be deemed as a statement of guaranteed properties. All persons responsible
for applying the equipment addressed in this manual must satisfy themselves that each intended
application is suitable and acceptable, including that any applicable safety or other operational
requirements are complied with. In particular, any risks in applications where a system failure and/or
product failure would create a risk for harm to property or persons (including but not limited to personal
injuries or death) shall be the sole responsibility of the person or entity applying the equipment, and
those so responsible are hereby requested to ensure that all measures are taken to exclude or mitigate
such risks.
This document has been carefully checked by Hitachi Energy, but deviations cannot be completely ruled
out. In case any errors are detected, the reader is kindly requested to notify the manufacturer. Other
than under explicit contractual commitments, in no event shall Hitachi Energy be responsible or liable for
any loss or damage resulting from the use of this manual or the application of the equipment.
Conformity
This product complies with the directive of the Council of the European Communities on the
approximation of the laws of the Member States relating to electromagnetic compatibility (EMC Directive
2004/108/EC) and concerning electrical equipment for use within specified voltage limits (Low-voltage
directive 2006/95/EC). This conformity is the result of tests conducted by Hitachi Energy in accordance
with the product standard EN 60255-26 for the EMC directive, and with the product standards EN
60255-1 and EN 60255-27 for the low voltage directive. The product is designed in accordance with the
international standards of the IEC 60255 series and ANSI C37.90.
1MRK506370-UUS Rev. S Table of contents
Table of contents
Section 1 Introduction...................................................................................................... 49
1.1 This manual..............................................................................................................................49
1.1.1 Presumptions for Technical Data............................................................................................49
1.2 Intended audience....................................................................................................................49
1.3 Product documentation............................................................................................................ 50
1.3.1 Product documentation set.....................................................................................................50
1.3.2 Document revision history...................................................................................................... 51
1.3.3 Related documents................................................................................................................ 52
1.4 Document symbols and conventions........................................................................................53
1.4.1 Symbols..................................................................................................................................53
1.4.2 Document conventions...........................................................................................................53
1.5 IEC 61850 Edition 1, Edition 2, and Edition 2.1 mapping.........................................................54
7.2.4 Signals..................................................................................................................................121
7.2.5 Settings................................................................................................................................ 125
7.2.6 Monitored data..................................................................................................................... 134
7.2.7 Operation principle............................................................................................................... 137
7.2.7.1 Frequency reporting........................................................................................................ 139
7.2.7.2 Reporting filters............................................................................................................... 140
7.2.7.3 Scaling Factors for ANALOGREPORT channels............................................................ 140
7.2.8 Technical data...................................................................................................................... 142
9.5 Full-scheme distance protection, quadrilateral for earth faults ZMMPDIS (21),
ZMMAPDIS (21)..................................................................................................................... 227
9.5.1 Identification......................................................................................................................... 227
9.5.2 Functionality ........................................................................................................................ 227
9.5.3 Function block...................................................................................................................... 228
9.5.4 Signals..................................................................................................................................229
9.5.5 Settings................................................................................................................................ 230
9.5.6 Operation principle............................................................................................................... 231
9.5.6.1 Full scheme measurement.............................................................................................. 231
9.5.6.2 Impedance characteristic................................................................................................ 231
9.5.6.3 Minimum operating current..............................................................................................233
9.5.6.4 Measuring principles....................................................................................................... 233
9.5.6.5 Directionality....................................................................................................................235
9.5.6.6 Simplified logic diagrams.................................................................................................237
9.5.7 Technical data...................................................................................................................... 240
9.6 Directional impedance element for mho characteristic and additional distance protection
directional function for earth faults ZDMRDIR (21D), ZDARDIR............................................240
9.6.1 Identification......................................................................................................................... 240
9.6.2 Functionality ........................................................................................................................ 240
9.6.3 Function block...................................................................................................................... 241
9.6.4 Signals..................................................................................................................................241
9.6.5 Settings................................................................................................................................ 242
9.6.6 Monitored data..................................................................................................................... 243
9.6.7 Operation principle............................................................................................................... 243
9.6.7.1 Directional impedance element for mho characteristic ZDMRDIR (21D) ....................... 243
9.6.7.2 Additional distance protection directional function for ground faults ZDARDIR ............. 245
9.7 Mho impedance supervision logic ZSMGAPC....................................................................... 247
9.7.1 Identification......................................................................................................................... 247
9.7.2 Functionality ........................................................................................................................ 247
9.7.3 Function block...................................................................................................................... 247
9.7.4 Signals..................................................................................................................................248
9.7.5 Settings................................................................................................................................ 248
9.7.6 Operation principle............................................................................................................... 248
9.7.6.1 Fault inception detection................................................................................................. 248
9.8 Faulty phase identification with load encroachment FMPSPDIS (21).................................... 250
9.8.1 Identification......................................................................................................................... 250
9.8.2 Functionality ........................................................................................................................ 250
9.8.3 Function block...................................................................................................................... 250
9.8.4 Signals..................................................................................................................................250
9.8.5 Settings................................................................................................................................ 251
9.8.6 Operation principle............................................................................................................... 252
9.8.6.1 The phase selection function...........................................................................................252
9.8.7 Technical data...................................................................................................................... 261
9.9 Distance protection zone, quadrilateral characteristic, separate settings ZMRPDIS (21),
ZMRAPDIS (21) and ZDRDIR (21D)......................................................................................261
9.9.1 Identification......................................................................................................................... 261
9.9.2 Functionality ........................................................................................................................ 261
10.7.5 Signals..................................................................................................................................516
10.7.6 Settings................................................................................................................................ 516
10.7.7 Monitored data..................................................................................................................... 518
10.7.8 Operation principle............................................................................................................... 518
10.7.9 Technical data...................................................................................................................... 521
10.8 Breaker failure protection CCRBRF (50BF) .......................................................................... 521
10.8.1 Function revision history.......................................................................................................521
10.8.2 Identification......................................................................................................................... 522
10.8.3 Functionality ........................................................................................................................ 522
10.8.4 Function block...................................................................................................................... 522
10.8.5 Signals..................................................................................................................................523
10.8.6 Settings................................................................................................................................ 523
10.8.7 Monitored data..................................................................................................................... 524
10.8.8 Operation principle .............................................................................................................. 524
10.8.9 Technical data...................................................................................................................... 530
10.9 Stub protection STBPTOC (50STB)....................................................................................... 530
10.9.1 Function revision history.......................................................................................................530
10.9.2 Identification......................................................................................................................... 531
10.9.3 Functionality ........................................................................................................................ 531
10.9.4 Function block...................................................................................................................... 531
10.9.5 Signals..................................................................................................................................531
10.9.6 Settings................................................................................................................................ 532
10.9.7 Monitored data..................................................................................................................... 532
10.9.8 Operation principle............................................................................................................... 532
10.9.9 Technical data...................................................................................................................... 533
10.10 Overcurrent protection with binary release BRPTOC.............................................................533
10.10.1 Function revision history.......................................................................................................533
10.10.2 Identification......................................................................................................................... 534
10.10.3 Functionality ........................................................................................................................ 534
10.10.4 Function block...................................................................................................................... 534
10.10.5 Signals..................................................................................................................................534
10.10.6 Settings................................................................................................................................ 535
10.10.7 Monitored data..................................................................................................................... 535
10.10.8 Operation principle............................................................................................................... 535
10.10.9 Technical data...................................................................................................................... 536
10.11 Pole discrepancy protection CCPDSC(52PD)........................................................................537
10.11.1 Identification......................................................................................................................... 537
10.11.2 Functionality ........................................................................................................................ 537
10.11.3 Function block...................................................................................................................... 538
10.11.4 Signals..................................................................................................................................538
10.11.5 Settings................................................................................................................................ 539
10.11.6 Monitored data..................................................................................................................... 539
10.11.7 Operation principle............................................................................................................... 539
10.11.7.1 Pole discrepancy signaling from circuit breaker ............................................................. 541
10.11.7.2 Unsymmetrical current detection.....................................................................................542
10.11.8 Technical data...................................................................................................................... 542
15.2.4 Signals..................................................................................................................................687
15.2.5 Settings................................................................................................................................ 687
15.2.6 Monitored data..................................................................................................................... 688
15.2.7 Operation principle............................................................................................................... 688
15.2.7.1 Zero and negative sequence detection........................................................................... 688
15.2.7.2 Delta current and delta voltage detection........................................................................690
15.2.7.3 Dead line detection..........................................................................................................693
15.2.7.4 Main logic........................................................................................................................ 694
15.2.8 Technical data...................................................................................................................... 697
15.3 Fuse failure supervision VDSPVC (60).................................................................................. 697
15.3.1 Identification......................................................................................................................... 697
15.3.2 Functionality ........................................................................................................................ 697
15.3.3 Function block...................................................................................................................... 698
15.3.4 Signals..................................................................................................................................698
15.3.5 Settings................................................................................................................................ 698
15.3.6 Monitored data..................................................................................................................... 699
15.3.7 Operation principle............................................................................................................... 699
15.3.8 Technical data...................................................................................................................... 700
15.4 Voltage based delta supervision DELVSPVC(78V)................................................................ 700
15.4.1 Identification......................................................................................................................... 700
15.4.2 Functionality......................................................................................................................... 701
15.4.3 Function block...................................................................................................................... 701
15.4.4 Signals..................................................................................................................................701
15.4.5 Settings................................................................................................................................ 702
15.4.6 Monitored data..................................................................................................................... 702
15.4.7 Operation principle............................................................................................................... 702
15.4.7.1 Minimum signal level check.............................................................................................703
15.4.7.2 Mode of operation........................................................................................................... 703
15.4.7.3 Instantaneous 1 cycle / 2 cycle ...................................................................................... 703
15.4.7.4 RMS/DFT based supervision.......................................................................................... 704
15.4.7.5 Angle based supervision or vector shift supervision....................................................... 704
15.4.8 Technical data...................................................................................................................... 706
15.5 Current based delta supervision DELISPVC(7I).................................................................... 706
15.5.1 Identification......................................................................................................................... 706
15.5.2 Functionality......................................................................................................................... 706
15.5.3 Function block...................................................................................................................... 706
15.5.4 Signals..................................................................................................................................707
15.5.5 Settings................................................................................................................................ 707
15.5.6 Monitored data..................................................................................................................... 708
15.5.7 Operation principle............................................................................................................... 708
15.5.7.1 Minimum signal level check.............................................................................................709
15.5.7.2 Mode of operation........................................................................................................... 709
15.5.7.3 Instantaneous 1 cycle / 2 cycle ...................................................................................... 709
15.5.7.4 RMS/DFT based supervision.......................................................................................... 710
15.5.7.5 2nd Harmonic blocking.....................................................................................................710
15.5.7.6 3rd Harmonic based adaption.......................................................................................... 711
18.5.4 Signals..................................................................................................................................943
18.5.5 Settings................................................................................................................................ 943
18.5.6 Operation principle............................................................................................................... 944
18.5.7 Technical data...................................................................................................................... 944
18.6 Logic for group indication INDCALH...................................................................................... 944
18.6.1 Identification......................................................................................................................... 944
18.6.2 Functionality ........................................................................................................................ 944
18.6.3 Function block...................................................................................................................... 945
18.6.4 Signals..................................................................................................................................945
18.6.5 Settings................................................................................................................................ 945
18.6.6 Operation principle............................................................................................................... 946
18.6.7 Technical data...................................................................................................................... 946
18.7 Basic configurable logic blocks.............................................................................................. 946
18.7.1 AND function block...............................................................................................................947
18.7.1.1 Function block................................................................................................................. 947
18.7.1.2 Signals.............................................................................................................................947
18.7.1.3 Technical data................................................................................................................. 947
18.7.2 Controllable gate function block GATE.................................................................................948
18.7.2.1 Function block................................................................................................................. 948
18.7.2.2 Signals.............................................................................................................................948
18.7.2.3 Settings........................................................................................................................... 948
18.7.2.4 Technical data................................................................................................................. 948
18.7.3 Inverter function block INV................................................................................................... 948
18.7.3.1 Function block................................................................................................................. 948
18.7.3.2 Signals.............................................................................................................................949
18.7.3.3 Technical data................................................................................................................. 949
18.7.4 Loop delay function block LLD............................................................................................. 949
18.7.4.1 Function block................................................................................................................. 949
18.7.4.2 Signals.............................................................................................................................949
18.7.4.3 Technical data................................................................................................................. 949
18.7.5 OR function block................................................................................................................. 950
18.7.5.1 Function block................................................................................................................. 950
18.7.5.2 Signals.............................................................................................................................950
18.7.5.3 Technical data................................................................................................................. 950
18.7.6 Pulse timer function block PULSETIMER............................................................................ 950
18.7.6.1 Function block................................................................................................................. 950
18.7.6.2 Signals.............................................................................................................................951
18.7.6.3 Settings........................................................................................................................... 951
18.7.6.4 Technical data................................................................................................................. 951
18.7.7 Reset-set with memory function block RSMEMORY........................................................... 951
18.7.7.1 Function block................................................................................................................. 951
18.7.7.2 Signals.............................................................................................................................952
18.7.7.3 Settings........................................................................................................................... 952
18.7.7.4 Technical data................................................................................................................. 952
18.7.8 Set-reset with memory function block SRMEMORY............................................................ 952
18.7.8.1 Function block................................................................................................................. 952
18.7.8.2 Signals.............................................................................................................................953
18.7.8.3 Settings........................................................................................................................... 953
18.7.8.4 Technical data................................................................................................................. 953
18.7.9 Settable timer function block TIMERSET............................................................................. 953
18.7.9.1 Function block................................................................................................................. 954
18.7.9.2 Signals.............................................................................................................................954
18.7.9.3 Settings........................................................................................................................... 954
18.7.9.4 Technical data................................................................................................................. 954
18.7.10 Exclusive OR function block XOR........................................................................................ 954
18.7.10.1 Function block................................................................................................................. 955
18.7.10.2 Signals.............................................................................................................................955
18.7.10.3 Technical data................................................................................................................. 955
18.8 Configurable logic blocks Q/T ............................................................................................... 955
18.8.1 ANDQT function block..........................................................................................................956
18.8.1.1 Function block................................................................................................................. 956
18.8.1.2 Signals.............................................................................................................................956
18.8.1.3 Technical data................................................................................................................. 957
18.8.2 Single point indication related signals combining function block INDCOMBSPQT.............. 957
18.8.2.1 Function block................................................................................................................. 957
18.8.2.2 Signals.............................................................................................................................957
18.8.2.3 Technical data................................................................................................................. 958
18.8.3 Single point input signal attributes converting function block INDEXTSPQT....................... 958
18.8.3.1 Function block................................................................................................................. 958
18.8.3.2 Signals.............................................................................................................................958
18.8.3.3 Technical data................................................................................................................. 959
18.8.4 Invalid logic function block INVALIDQT................................................................................959
18.8.4.1 Function block................................................................................................................. 959
18.8.4.2 Signals.............................................................................................................................959
18.8.4.3 Technical data................................................................................................................. 960
18.8.5 Inverter function block INVERTERQT.................................................................................. 960
18.8.5.1 Function block................................................................................................................. 960
18.8.5.2 Signals.............................................................................................................................961
18.8.5.3 Technical data................................................................................................................. 961
18.8.6 ORQT function block............................................................................................................ 961
18.8.6.1 Function block................................................................................................................. 961
18.8.6.2 Signals.............................................................................................................................961
18.8.6.3 Technical data................................................................................................................. 962
18.8.7 Pulse timer function block PULSETIMERQT....................................................................... 962
18.8.7.1 Function block................................................................................................................. 962
18.8.7.2 Signals.............................................................................................................................962
18.8.7.3 Settings........................................................................................................................... 962
18.8.7.4 Technical data................................................................................................................. 963
18.8.8 Reset/Set function block RSMEMORYQT........................................................................... 963
18.8.8.1 Function block................................................................................................................. 963
18.8.8.2 Signals.............................................................................................................................963
18.8.8.3 Settings........................................................................................................................... 963
Section 21 Ethernet.........................................................................................................1155
21.1 Access point......................................................................................................................... 1155
21.1.1 Introduction ........................................................................................................................1155
21.1.2 Settings...............................................................................................................................1155
21.2 Access point diagnostics...................................................................................................... 1157
21.2.1 Functionality ...................................................................................................................... 1157
21.2.2 Function block.................................................................................................................... 1157
21.2.3 Signals................................................................................................................................1158
21.2.4 Monitored data....................................................................................................................1158
21.3 Redundant communication................................................................................................... 1159
21.3.1 Identification....................................................................................................................... 1159
21.3.2 Functionality....................................................................................................................... 1159
21.3.3 Operation principle............................................................................................................. 1159
Section 24 Security.........................................................................................................1309
24.1 Authority check ATHCHCK...................................................................................................1309
24.1.1 Identification....................................................................................................................... 1309
24.1.2 Functionality ...................................................................................................................... 1309
24.1.3 Operation principle ............................................................................................................ 1310
24.1.3.1 Authorization with Central Account Management enabled IED.................................... 1312
24.2 Authority management AUTHMAN...................................................................................... 1313
24.2.1 Identification....................................................................................................................... 1313
24.2.2 AUTHMAN..........................................................................................................................1313
24.2.3 Settings.............................................................................................................................. 1314
24.3 FTP access with password FTPACCS................................................................................. 1314
24.3.1 Identification....................................................................................................................... 1314
24.3.2 FTP access with TLS, FTPACCS.......................................................................................1314
24.3.3 Settings.............................................................................................................................. 1314
24.4 Authority status ATHSTAT.................................................................................................... 1315
24.4.1 Identification....................................................................................................................... 1315
24.4.2 Functionality ...................................................................................................................... 1315
24.4.3 Function block.................................................................................................................... 1315
24.4.4 Signals................................................................................................................................1315
24.4.5 Settings.............................................................................................................................. 1315
24.4.6 Operation principle ............................................................................................................ 1315
24.5 Self supervision with internal event list INTERRSIG............................................................ 1316
24.5.1 Functionality ...................................................................................................................... 1316
24.5.2 Function block.................................................................................................................... 1316
24.5.3 Signals................................................................................................................................1316
24.5.4 Settings.............................................................................................................................. 1316
Section 27 Labels............................................................................................................1435
27.1 Labels on IED.......................................................................................................................1435
Section 30 Glossary........................................................................................................1471
Section 1 Introduction
1.1 This manual GUID-AB423A30-13C2-46AF-B7FE-A73BB425EB5F v21
The technical manual contains operation principle descriptions, and lists function blocks, logic diagrams,
input and output signals, setting parameters and technical data, sorted per function. The manual can be
used as a technical reference during the engineering phase, installation and commissioning phase, and
during normal service.
The technical data stated in this document are only valid under the following circumstances:
1. Main current transformers with 1 A or 2 A secondary rating are wired to the IED 1 A rated CT inputs.
2. Main current transformer with 5 A secondary rating are wired to the IED 5 A rated CT inputs.
3. CT and VT ratios in the IED are set in accordance with the associated main instrument transformers.
Note that for functions which measure an analogue signal which do not have corresponding primary
quantity the 1:1 ratio shall be set for the used analogue inputs on the IED. Example of such
functions are: HZPDIF, ROTIPHIZ and STTIPHIZ.
4. Parameter IBase used by the tested function is set equal to the rated CT primary current.
5. Parameter UBase used by the tested function is set equal to the rated primary phase-to-phase
voltage.
6. Parameter SBase used by the tested function is set equal to:
• √3 × IBase × UBase
8. For operate and reset time testing, the default setting values of the function and BOM module are
used if not explicitly stated otherwise.
All reset times are measured using BOM output contacts if not explicitly stated otherwise. The
operate/reset times are determined by characteristics of the output module used.
9. During testing, signals with rated frequency have been injected if not explicitly stated otherwise.
10. All declared operate times are with BOM module unless specified. All the declared operate (trip)
times can be reduced by 3-4 ms when using SOM module.
This manual addresses system engineers and installation and commissioning personnel, who use
technical data during engineering, installation and commissioning, and in normal service.
The system engineer must have a thorough knowledge of protection systems, protection equipment,
protection functions and the configured functional logic in the IEDs. The installation and commissioning
personnel must have a basic knowledge in handling electronic equipment.
Decommissioning
Commissioning
Maintenance
Engineering
Operation
Installing
Engineering manual
Installation manual
Commissioning manual
Operation manual
Application manual
Technical manual
Communication
protocol manual
Cyber security
deployment guideline
IEC07000220-4-en.vsd
IEC07000220 V4 EN-US
The engineering manual contains instructions on how to engineer the IEDs using the various tools
available within the PCM600 software. The manual provides instructions on how to set up a PCM600
project and insert IEDs to the project structure. The manual also recommends a sequence for the
engineering of protection and control functions, as well as communication engineering for IEC 61850.
The installation manual contains instructions on how to install the IED. The manual provides procedures
for mechanical and electrical installation. The chapters are organized in the chronological order in which
the IED should be installed.
The commissioning manual contains instructions on how to commission the IED. The manual can also
be used by system engineers and maintenance personnel for assistance during the testing phase. The
manual provides procedures for the checking of external circuitry and energizing the IED, parameter
setting and configuration as well as verifying settings by secondary injection. The manual describes the
process of testing an IED in a substation which is not in service. The chapters are organized in the
chronological order in which the IED should be commissioned. The relevant procedures may be followed
also during the service and maintenance activities.
The operation manual contains instructions on how to operate the IED once it has been commissioned.
The manual provides instructions for the monitoring, controlling and setting of the IED. The manual also
describes how to identify disturbances and how to view calculated and measured power grid data to
determine the cause of a fault.
The application manual contains application descriptions and setting guidelines sorted per function. The
manual can be used to find out when and for what purpose a typical protection function can be used.
The manual can also provide assistance for calculating settings.
The technical manual contains operation principle descriptions, and lists function blocks, logic diagrams,
input and output signals, setting parameters and technical data, sorted per function. The manual can be
used as a technical reference during the engineering phase, installation and commissioning phase, and
during normal service.
The communication protocol manual describes the communication protocols supported by the IED. The
manual concentrates on the vendor-specific implementations.
The point list manual describes the outlook and properties of the data points specific to the IED. The
manual should be used in conjunction with the corresponding communication protocol manual.
The cyber security deployment guideline describes the process for handling cyber security when
communicating with the IED. Certification, Authorization with role based access control, and product
engineering for cyber security related events are described and sorted by function. The guideline can be
used as a technical reference during the engineering phase, installation and commissioning phase, and
during normal service.
The electrical warning icon indicates the presence of a hazard which could result in electrical
shock.
The warning icon indicates the presence of a hazard which could result in personal injury.
The caution hot surface icon indicates important information or warning about the
temperature of product surfaces.
Class 1 Laser product. Take adequate measures to protect the eyes and do not view directly
with optical instruments.
The caution icon indicates important information or warning related to the concept discussed
in the text. It might indicate the presence of a hazard which could result in corruption of
software or damage to equipment or property.
The information icon alerts the reader of important facts and conditions.
The tip icon indicates advice on, for example, how to design your project or how to use a
certain function.
Although warning hazards are related to personal injury, it is necessary to understand that under certain
operational conditions, operation of damaged equipment may result in degraded process performance
leading to personal injury or death. It is important that the user fully complies with all warning and
cautionary notices.
• Abbreviations and acronyms in this manual are spelled out in the glossary. The glossary also contains
definitions of important terms.
• Push button navigation in the LHMI menu structure is presented by using the push button icons.
For example, to navigate between the options, use and .
• HMI menu paths are presented in bold.
For example, select Main menu/Settings.
• LHMI messages are shown in Courier font.
For example, to save the changes in non-volatile memory, select Yes and press .
• Parameter names are shown in italics.
For example, the function can be enabled and disabled with the Operation setting.
• Each function block symbol shows the available input/output signal.
• the character ^ in front of an input/output signal name indicates that the signal name may be
customized using the PCM600 software.
• the character * after an input signal name indicates that the signal must be connected to another
function block in the application configuration to achieve a valid application configuration.
• Dimensions are provided both in inches and millimeters. If it is not specifically mentioned then the
dimension is in millimeters.
• Logic diagrams describe the signal logic of the function block and are bordered by dashed lines.
In a logic diagram, input and output signal paths are shown as lines that touch the outer border of the
diagram. Input signals are always on the left-hand side and output signals are on the right-hand side.
Input and output signals can be configured using PCM600. They can be connected to the inputs and
outputs of other functions and to binary inputs and outputs. Examples of input signals are BLKTR,
BLOCK, and VTSZ. Examples of output signals are TRIP, START, STL1, STL2, and STL3.
• Frames with a shaded area on the right-hand side represent setting parameters. These parameters
can only be set via the PST or LHMI. Their values are high (1) only when the corresponding setting
parameter is set to the symbolic value specified within the frame. Example is the signal Timer
tPP=On. Their logical values correspond automatically to the selected setting value.
• Internal signals are illustrated graphically and end approximately 2 mm from the frame edge. If an
internal signal path cannot be drawn with a continuous line, the same signal name is used where the
signal should continue, see figure "" and figure "". Example of the internal signal is BLK.
• Signal paths that extend beyond the logic diagram and continue in another diagram will be
approximately 2 mm from the frame edge, see figure "" and figure "". Examples are STNDL1N,
STNDL2N, STNDL3N, STNDL1L2, STNDL2L3, and STNDL3L1.
1.5 IEC 61850 Edition 1, Edition 2, and Edition 2.1 mapping GUID-C5133366-7260-4C47-A975-7DBAB3A33A96 v10
Function block names are used in ACT and PST to identify functions. Respective function block names
of Edition 1, Edition 2, and Edition 2.1 logical nodes are shown in the table below.
Function block name Edition 1 logical nodes Edition 2 and Edition 2.1 logical nodes
- - ALGOS
- - ALSVS
AGSAL AGSAL AGSAL
SECLLN0
ALMCALH ALMCALH ALMCALH
ALTIM - ALTIM
ALTMS - ALTMS
ALTRK - ALTRK
APPTEF
BRCPTOC BRCPTOC BRCPTOC
BRPTOC BRPTOC BRPTOC
BTIGAPC B16IFCVI BTIGAPC
CCPDSC CCRPLD CCPDSC
CCRBRF CCRBRF CCRBRF
CCSSPVC CCSRDIF CCSSPVC
CHMMHAI CHMMHAI CHMMHAI
CMMXU CMMXU CMMXU
CMSQI CMSQI CMSQI
Table continues on next page
Function block name Edition 1 logical nodes Edition 2 and Edition 2.1 logical nodes
COUVGAPC COUVLLN0 COUVPTOV
COUVPTOV COUVPTUV
COUVPTUV
CVGAPC GF2LLN0 GF2MMXN
GF2MMXN GF2PHAR
GF2PHAR GF2PTOV
GF2PTOV GF2PTUC
GF2PTUC GF2PTUV
GF2PTUV GF2PVOC
GF2PVOC PH1PTRC
PH1PTRC
CVMMXN CVMMXN CVMMXN
DELISPVC DELISPVC DELISPVC
DELSPVC DELSPVC DELSPVC
DELVSPVC DELVSPVC DELVSPVC
DPGAPC DPGGIO DPGAPC
DRPRDRE DRPRDRE DRPRDRE
ECPSCH ECPSCH ECPSCH
ECRWPSCH ECRWPSCH ECRWPSCH
EF4PTOC EF4LLN0 EF4PTRC
EF4PTRC EF4RDIR
EF4RDIR GEN4PHAR
GEN4PHAR PH1PTOC
PH1PTOC
EFPIOC EFPIOC EFPIOC
ETPMMTR ETPMMTR ETPMMTR
FDPSPDIS FDPSPDIS FDPSPDIS
FLTMMXU FLTMMXU FLTMMXU
FMPSPDIS FMPSPDIS FMPSPDIS
FRPSPDIS FPSRPDIS FPSRPDIS
FUFSPVC SDDRFUF FUFSPVC
SDDSPVC
GOPPDOP GOPPDOP GOPPDOP
PH1PTRC
GUPPDUP GUPPDUP GUPPDUP
PH1PTRC
HZPDIF HZPDIF HZPDIF
INDCALH INDCALH INDCALH
ITBGAPC IB16FCVB ITBGAPC
L4UFCNT L4UFCNT L4UFCNT
LAPPGAPC LAPPLLN0 LAPPPDUP
LAPPPDUP LAPPPUPF
LAPPPUPF
LCCRPTRC LCCRPTRC LCCRPTRC
LCNSPTOC LCNSPTOC LCNSPTOC
LCNSPTOV LCNSPTOV LCNSPTOV
LCP3PTOC LCP3PTOC LCP3PTOC
LCP3PTUC LCP3PTUC LCP3PTUC
LCPTTR LCPTTR LCPTTR
LCZSPTOC LCZSPTOC LCZSPTOC
LCZSPTOV LCZSPTOV LCZSPTOV
LD0LLN0 LLN0 -
Table continues on next page
Function block name Edition 1 logical nodes Edition 2 and Edition 2.1 logical nodes
LDRGFC STSGGIO LDRGFC
LLDLPTRC
PHPTUC
PHPTUV
SVABPTOC
SVBCPTOC
SVCAPTOC
ZSPTOC
LFPTTR LFPTTR LFPTTR
LMBRFLO LMBRFLO LMBRFLO
LOVPTUV LOVPTUV LOVPTUV
LPHD LPHD
MVGAPC MVGGIO MVGAPC
NS4PTOC EF4LLN0 EF4PTRC
EF4PTRC EF4RDIR
EF4RDIR PH1PTOC
GEN4PHAR
PH1PTOC
OC4PTOC OC4LLN0 GEN4PHAR
GEN4PHAR PH3PTOC
PH3PTOC PH3PTRC
PH3PTRC
OEXPVPH OEXPVPH OEXPVPH
OOSPPAM OOSPPAM OOSPPAM
OOSPTRC
OV2PTOV GEN2LLN0 OV2PTOV
OV2PTOV PH1PTRC
PH1PTRC
PAPGAPC PAPGAPC PAPGAPC
PCFCNT PCGGIO PCFCNT
PHPIOC PHPIOC PHPIOC
PSLPSCH ZMRPSL PSLPSCH
PSPPPAM PSPPPAM PSPPPAM
PSPPTRC
PTRSTHR PTRSTHR PTRSTHR
QCBAY QCBAY BAY/LLN0
QCRSV QCRSV QCRSV
RCHLCCH RCHLCCH RCHLCCH
ROV2PTOV GEN2LLN0 PH1PTRC
PH1PTRC ROV2PTOV
ROV2PTOV
SAPFRC SAPFRC SAPFRC
SAPTOF SAPTOF SAPTOF
SAPTUF SAPTUF SAPTUF
SCCVPTOC SCCVPTOC SCCVPTOC
SCHLCCH SCHLCCH SCHLCCH
SCILO SCILO SCILO
SCSWI SCSWI SCSWI
SDEPSDE SDEPSDE SDEPSDE
SDEPTOC
SDEPTOV
SDEPTRC
Table continues on next page
Function block name Edition 1 logical nodes Edition 2 and Edition 2.1 logical nodes
SESRSYN RSY1LLN0 AUT1RSYN
AUT1RSYN MAN1RSYN
MAN1RSYN SYNRSYN
SYNRSYN
SLGAPC SLGGIO SLGAPC
SMBRREC SMBRREC SMBRREC
SMPPTRC SMPPTRC SMPPTRC
SP16GAPC SP16GGIO SP16GAPC
SPC8GAPC SPC8GGIO SPC8GAPC
SPGAPC SPGGIO SPGAPC
SSCBR SSCBR SSCBR
SSIMG SSIMG SSIMG
SSIML SSIML SSIML
STBPTOC STBPTOC BBPMSS
STBPTOC
SXCBR SXCBR SXCBR
SXSWI SXSWI SXSWI
TEIGAPC TEIGGIO TEIGAPC
TEIGGIO
TEILGAPC TEILGGIO TEILGAPC
TMAGAPC TMAGGIO TMAGAPC
UV2PTUV GEN2LLN0 PH1PTRC
PH1PTRC UV2PTUV
UV2PTUV
VDCPTDV VDCPTOV VDCPTOV
VDSPVC VDRFUF VDSPVC
VHMMHAI VHMMHAI VHMMHAI
VHMQVHA VHMQVHA
VMMXU VMMXU VMMXU
VMSQI VMSQI VMSQI
VNMMXU VNMMXU VNMMXU
VRPVOC VRLLN0 PH1PTRC
PH1PTRC PH1PTUV
PH1PTUV VRPVOC
VRPVOC
VSGAPC VSGGIO VSGAPC
WRNCALH WRNCALH WRNCALH
ZCLCPSCH ZCLCPLAL ZCLCPSCH
ZCPSCH ZCPSCH ZCPSCH
ZCRWPSCH ZCRWPSCH ZCRWPSCH
ZCVPSOF ZCVPSOF ZCVPSOF
ZMCAPDIS ZMCAPDIS ZMCAPDIS
ZMCPDIS ZMCPDIS ZMCPDIS
ZMFCPDIS ZMFCLLN0 PSFPDIS
PSFPDIS ZMFPDIS
ZMFPDIS ZMFPTRC
ZMFPTRC ZMMMXU
ZMMMXU
ZMFPDIS ZMFLLN0 PSFPDIS
PSFPDIS PSFPDIS
ZMFPDIS ZMFPDIS
ZMFPTRC ZMFPTRC
ZMMMXU ZMMMXU
Table continues on next page
Function block name Edition 1 logical nodes Edition 2 and Edition 2.1 logical nodes
ZMHPDIS ZMHPDIS ZMHPDIS
ZMMAPDIS ZMMAPDIS ZMMAPDIS
ZMMPDIS ZMMPDIS ZMMPDIS
ZMQAPDIS ZMQAPDIS ZMQAPDIS
ZMQPDIS ZMQPDIS ZMQPDIS
ZMRAPDIS ZMRAPDIS ZMRAPDIS
ZMRPDIS ZMRPDIS ZMRPDIS
ZMBURPSB ZMBURPSB ZMBURPSB
ZPCPSCH ZPCPSCH ZPCPSCH
ZPCWPSCH ZPCWPSCH ZPCWPSCH
ZSMGAPC ZSMGAPC ZSMGAPC
Read the entire manual before doing installation or any maintenance work on the product.
Class 1 Laser product. Take adequate measures to protect your eyes and do not view
directly with optical instruments.
Do not touch the unit in operation. The installation shall take into account the worst case
temperature.
Observe the warnings during all types of work related to the product.
GUID-C9B6638A-57E7-4E05-9A33-A60E359C54AF v2
Only electrically skilled persons with the proper authorization and knowledge of any safety
hazards are allowed to carry out the electrical installation.
M2366-2 v2
National and local electrical safety regulations must always be followed. Working in a high
voltage environment requires serious approach to avoid human injuries and damage to
equipment.
M2362-2 v1
Do not touch circuitry during operation. Potentially lethal voltages and currents are present.
M2364-2 v1
Always use suitable isolated test pins when measuring signals in open circuitry. Potentially
lethal voltages and currents are present.
M2370-2 v1
Never connect or disconnect a wire and/or a connector to or from a IED during normal
operation. Hazardous voltages and currents are present that may be lethal. Operation may
be disrupted and IED and measuring circuitry may be damaged.
GUID-BEDD698E-356C-4CF9-9DAE-64DB3CEADEAD v1
Dangerous voltages can occur on the connectors, even though the auxiliary voltage has
been disconnected.
M2369-2 v3
Always connect the IED to protective ground, regardless of the operating conditions.
This also applies to special occasions such as bench testing, demonstrations and off-site
configuration. This is class 1 equipment that shall be grounded.
M2367-2 v1
Never disconnect the secondary connection of current transformer circuit without short-
circuiting the transformer’s secondary winding. Operating a current transformer with the
secondary winding open will cause a massive potential build-up that may damage the
transformer and may cause injuries to humans.
M2372-2 v1
Never remove any screw from a powered IED or from a IED connected to powered circuitry.
Potentially lethal voltages and currents are present.
SEMOD168311-3 v1
Take adequate measures to protect the eyes. Never look into the laser beam.
GUID-11CCF92B-E9E7-409C-84D0-DFDEA1DCBE85 v3
The IED with accessories should be mounted in a cubicle in a restricted access area within a
power station, substation or industrial or retail environment.
During decommissioning, wait 2 minutes for capacitor discharge after removing all external
X1 connections.
GUID-5D1412B8-8F9D-4D39-B6D1-60FB35797FD0 v3
Whenever changes are made in the IED, measures should be taken to avoid inadvertent
tripping.
GUID-F2A7BD77-80FB-48F0-AAE5-BE73DE520CC2 v1
The IED contains components which are sensitive to electrostatic discharge. ESD
precautions shall always be observed prior to touching components.
M2695-2 v2
M2696-2 v1
Do not connect live wires to the IED. Internal circuitry may be damaged
M2697-2 v2
Always use a conductive wrist strap connected to protective ground when replacing modules.
Electrostatic discharge (ESD) may damage the module and IED circuitry.
M2698-2 v2
M2693-2 v2
Changing the active setting group will inevitably change the IED's operation. Be careful and
check regulations before making the change.
M19-2 v3
Observe the maximum allowed continuous current for the different current transformer inputs
of the IED. See technical data.
The following tables list all the functions available in the IED. Those functions that are not
exposed to the user or do not need to be configured are not described in this manual.
IEC 61850 or
ANSI Function description Line Distance
function name
REL670
(Customized)
Differential protection
HZPDIF 87 High impedance differential protection, single phase 0-3
LDRGFC 11REL Additional security logic for differential protection 0-1
Impedance protection
ZMQPDIS, 21 Distance protection zone, quadrilateral characteristic 1-7
ZMQAPDIS
ZDRDIR 21D Directional impedance quadrilateral 1-2
ZMCPDIS, 21 Distance measuring zone, quadrilateral characteristic for series compensated lines 1-6
ZMCAPDIS
ZDSRDIR 21D Directional impedance quadrilateral, including series compensation 1-2
FDPSPDIS 21 Phase selection, quadrilateral characteristic with fixed angle 2
ZMHPDIS 21 Full-scheme distance protection, mho characteristic 1-5
ZMMPDIS, 21 Full-scheme distance protection, quadrilateral for ground faults 1-5
ZMMAPDIS
ZDMRDIR 21D Directional impedance element for mho characteristic 1-2
ZDARDIR Additional distance protection directional function for ground faults 1-2
ZSMGAPC Mho impedance supervision logic 1
FMPSPDIS 21 Faulty phase identification with load enchroachment 2
ZMRPDIS, 21 Distance measuring zone, quad characteristic separate Ph-Ph and Ph-E settings 1-5
ZMRAPDIS
FRPSPDIS 21 Phase selection, quadrilateral characteristic with settable angle 2
ZMFPDIS 21 High speed distance protection, quad and mho characteristic 1-2
ZMFCPDIS 21 High speed distance protection for series comp. lines, quad and mho characteristic 1-2
PPLPHIZ Phase preference logic 0-1
PPL2PHIZ Phase preference logic 0-2
ZMBURPSB 68 Power swing detection, blocking and unblocking 0-2
PSLPSCH Power swing logic 0-2
PSPPPAM 78 Pole slip/out-of-step protection 0-2
OOSPPAM 78 Out-of-step protection 0-2
ZCVPSOF Automatic switch onto fault logic, voltage and current based 2
IEC 61850 or
ANSI Function description Line Distance
function name
REL670
(Customized)
Current protection
PHPIOC 50 Instantaneous phase overcurrent protection 0-3
OC4PTOC 51_67 1) Directional phase overcurrent protection, four steps 0-3
EFPIOC 50N Instantaneous residual overcurrent protection 0-3
EF4PTOC 51N_67N 2) Directional residual overcurrent protection, four steps 0-3
NS4PTOC 46I2 Directional negative phase sequence overcurrent protection, four steps 0-2
SDEPSDE 67N Sensitive directional residual overcurrent and power protection 0-2
LCPTTR 26 Thermal overload protection, one time constant, Celsius 0-2
LFPTTR 26 Thermal overload protection, one time constant, Fahrenheit 0-2
CCRBRF 50BF Breaker failure protection 0-2
STBPTOC 50STB Stub protection 0-2
CCPDSC 52PD Pole discordance protection 0-2
GUPPDUP 37 Directional underpower protection 0-2
GOPPDOP 32 Directional overpower protection 0-2
BRCPTOC 46 Broken conductor check 2
VRPVOC 51V Voltage restrained overcurrent protection 0-3
APPTEF 67NT Average power transient earth fault protection 0-2
BRPTOC 50 Overcurrent protection with binary release 0-3
Voltage protection
UV2PTUV 27 Two step undervoltage protection 0-2
OV2PTOV 59 Two step overvoltage protection 0-2
ROV2PTOV 59N Residual overvoltage protection, two steps 0-2
OEXPVPH 24 Overexcitation protection 0-1
VDCPTDV 87V Voltage differential protection 0-2
LOVPTUV 27 Loss of voltage check 2
PAPGAPC 27 Radial feeder protection 0-1
Frequency protection
SAPTUF 81 Underfrequency protection 0-10
SAPTOF 81 Overfrequency protection 0-6
SAPFRC 81 Rate-of-change of frequency protection 0-6
Multipurpose protection
CVGAPC General current and voltage protection 0-4
General calculation
SMAIHPAC Multipurpose filter 0-6
Table Note:
1) 67 requires voltage
2) 67N requires voltage
Analog input channels must be configured and set properly in order to get correct measurement results
and correct protection operations. For power measuring, all directional and differential functions, the
directions of the input currents must be defined in order to reflect the way the current transformers
are installed/connected in the field ( primary and secondary connections ). Measuring and protection
algorithms in the IED use primary system quantities. Setting values are in primary quantities as well and
it is important to set the data about the connected current and voltage transformers properly.
An AISVBAS reference PhaseAngleRef can be defined to facilitate service values reading. This analog
channel's phase angle will always be fixed to zero degrees and remaining analog channel's phase angle
information will be shown in relation to this analog input. During testing and commissioning of the IED,
the reference channel can be changed to facilitate testing and service values reading.
The IED has the ability to receive analog values from primary equipment, that are sampled
by Merging units (MU) connected to a process bus, via the IEC 61850-9-2 LE protocol.
The availability of VT inputs depends on the ordered transformer input module (TRM) type.
The hardware channels appear in the signal matrix tool (SMT) and in ACT when a TRM is
included in the configuration with the hardware configuration tool. In the SMT or the ACT,
they can be mapped to the desired virtual input (SMAI) of the IED and used internally in the
configuration.
4.3 Signals
PID-3920-OUTPUTSIGNALS v6
PID-3921-OUTPUTSIGNALS v7
4.4 Settings
SEMOD129840-4 v2
Dependent on ordered IED type.
PID-4153-SETTINGS v8
PID-3924-MONITOREDDATA v6
The direction of a measured current depends on the connection of the CT. The main CTs are typically
star (WYE) connected and can be connected with the Star (WYE) point towards the object or away from
the object. This information must be set in the IED.
Once the CT direction settings is correctly entered the internal IED convention of the directionality is
defined as follows:
• Positive value of current or power means that the quantity has the direction into the protected object.
• Negative value of current or power means that the quantity has the direction out from the protected
object.
For directional functions the directional conventions are defined as follows (see Figure 2)
Protected Object
Line, transformer, etc
e.g. P, Q, I e.g. P, Q, I
Measured quantity is Measured quantity is
positive when flowing positive when flowing
towards the object towards the object
en05000456-2.vsd
ANSI05000456 V2 EN-US
If the settings of the primary CT is correct, that is CTStarPoint set as FromObject or ToObject according
to the plant condition, then a positive quantity always flows towards the protected object, and a Forward
direction always looks towards the protected object.
The settings of the IED is performed in primary values. The ratios of the main CTs and VTs are,
therefore, basic data for the IED. The user has to set the rated secondary and primary currents and
voltages of the CTs and VTs to provide the IED with their rated ratios.
The CT and VT ratio and the name on respective channel is done under Main menu /Hardware /
Analog modules in the Parameter Settings tool or on the HMI.
M16988-1 v11
Table 32: TRM - Energizing quantities, rated values and limits for protection transformer
Description Value
Frequency
Rated frequency fr 50/60 Hz
Operating range fr ± 10%
Current inputs
Rated current Ir 1 or 5 A
Operating range (0-100) x Ir
Thermal withstand 100 × Ir for 1 s *)
30 × Ir for 10 s
10 × Ir for 1 min
4 × Ir continuously
Dynamic withstand 250 × Ir one half wave
Burden < 20 mVA at Ir = 1 A
< 150 mVA at Ir = 5 A
*) max. 350 A for 1 s when COMBITEST test switch is included.
Voltage inputs **)
Rated voltage Ur 110 or 220 V
Operating range 0 - 340 V
Thermal withstand 450 V for 10 s
420 V continuously
Burden < 20 mVA at 110 V
< 80 mVA at 220 V
**) all values for individual voltage inputs
Note! All current and voltage data are specified as RMS values at rated frequency
Table 33: TRM - Energizing quantities, rated values and limits for measuring transformer
Description Value
Frequency
Rated frequency fr 50/60 Hz
Operating range fr ± 10%
Current inputs
Rated current Ir 1A 5A
Operating range (0-1.8) × Ir (0-1.6) × Ir
Thermal withstand 80 × Ir for 1 s 65 × Ir for 1 s
25 × Ir for 10 s 20 × Ir for 10 s
10 × Ir for 1 min 8 × Ir for 1 min
1.8 × Ir for 30 min 1.6 × Ir for 30 min
1.1 × Ir continuously 1.1 × Ir continuously
Burden < 200 mVA at Ir < 350 mVA at Ir
Voltage inputs *)
Rated voltage Ur 110 or 220 V
Operating range 0 - 340 V
Table continues on next page
Description Value
Thermal withstand 450 V for 10 s
420 V continuously
Burden < 20 mVA at 110 V
< 80 mVA at 220 V
*) all values for individual voltage inputs
Note! All current and voltage data are specified as RMS values at rated frequency
SEMOD53376-2 v7
Connector type Rated voltage and current Maximum conductor area Tightening torque
Screw compression type 250 V AC, 20 A 4 mm2 (AWG12) 0.6 Nm
2 x 2.5 mm2 (2 x AWG14)
Ring lug type 250 V AC, 20 A 4 mm 2 (AWG12) 1.5 Nm
The debounce filter eliminates bounces and short disturbances on a binary input.
A time counter is used for filtering. The time counter is increased once in a millisecond when a binary
input is high, or decreased when a binary input is low. A new debounced binary input signal is forwarded
when the time counter reaches the set DebounceTime value and the debounced input value is high
or when the time counter reaches 0 and the debounced input value is low. The default setting of
DebounceTime is 1 ms.
The binary input ON-event gets the time stamp of the first rising edge, after which the counter does not
reach 0 again. The same happens when the signal goes down to 0 again.
Binary input wiring can be very long in substations and there are electromagnetic fields from for example
nearby breakers. An oscillation filter is used to reduce the disturbance from the system when a binary
input starts oscillating.
An oscillation counter counts the debounced signal state changes during 1 s. If the counter value is
greater than the set value OscBlock, the input signal is blocked. The input signal is ignored until the
oscillation counter value during 1 s is below the set value OscRelease.
5.1.3 Settings
GUID-07348953-4A72-444B-A31A-030ABEA8E0C4 v1
OscBlock must always be set to a value greater than OscRelease. If this is not done,
oscillation detection will not function correctly, and the resulting behaviour will be undefined.
Instead of the LHMI the Remote IED Access tool, RIA600, can be used and perform all of the
actions that a physical LHMI can.
Information about LHMI working procedures is also valid when the operation is performed
through RIA600. For more information on RIA600 operations, see manual Remote HMI client
RIA600 user guide (1MRK 511 619-UEN).
6.1.1 Identification
GUID-84392EFF-4D3F-4A67-A6ED-34C6E98574D6 v2
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Local HMI screen behaviour SCREEN - -
6.1.2 Settings
PID-7989-SETTINGS v1
6.2.1 Identification
GUID-03AB7AEE-87D3-4F3C-B6B9-B1EB1B538E38 v2
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Local HMI signals LHMICTRL - -
LHMICTRL
CLRLEDS HMI-ON
RED-S
YELLOW-S
YELLOW-F
CLRPULSE
LEDSCLRD
IEC09000320-1-en.vsd
IEC09000320 V1 EN-US
6.2.3 Signals
PID-3992-INPUTSIGNALS v6
6.3.1 Identification
GUID-6E36C0BC-F284-4C88-A4A8-9535D3BE8B14 v3
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Basic part for LED indication LEDGEN - -
module
Basic part for LED indication GRP1_LED1 - - -
HW module GRP1_LED15
GRP2_LED1 -
GRP2_LED15
GRP3_LED1 -
GRP3_LED15
LEDGEN
BLOCK NEWIND
RESET ACK
IEC09000321-1-en.vsd
IEC09000321 V1 EN-US
GRP1_LED1
^HM1L01R
^HM1L01Y
^HM1L01G
IEC09000322 V1 EN-US
The GRP1_LED1 function block is an example. The 15 LEDs in each of the three groups have a similar
function block.
6.3.3 Signals
PID-4114-INPUTSIGNALS v5
6.3.4 Settings
PID-4114-SETTINGS v6
6.4 LCD part for HMI function keys control module GUID-EECAE7FA-7078-472C-A429-F7607DB884EB v2
6.4.1 Identification
GUID-E6611022-5EA3-420D-ADCD-9D1E7604EFEB v2
FNKEYMD1
ENABLE ^FKEYOUT1
^LEDCTL1
IEC09000327 V2 EN-US
Only the function block for the first button is shown above. There is a similar block for every function key
button.
6.4.3 Signals
PID-7424-INPUTSIGNALS v1
6.4.4 Settings
PID-7424-SETTINGS v1
PID-7990-SETTINGS v1
For setting ReqAuthority, when users are configured through local or central account
management, the default behavior of the function keys are to only operate if a user is logged
in, and the user have the required rights. This authentication check can be configured to
be bypassed per function key by changing the ReqAuthority from ON to OFF. To be able to
change this, the user changing it have to have the Security advanced right.
MenuShortcut values are product dependent and created dynamically depending on the product main
menu.
ANSI13000239 V3 EN-US
• Keypad
• Display (LCD)
• LED indicators
• Communication port for PCM600
The LHMI keypad contains push-buttons which are used to navigate in different views or menus. The
push-buttons are also used to acknowledge alarms, reset indications, provide help and switch between
local and remote control mode.
The keypad also contains programmable push-buttons that can be configured either as menu shortcut or
control buttons.
ANSI15000157 V2 EN-US
Figure 8: LHMI keypad with object control, navigation and command push-buttons and RJ-45 communication port
The LHMI includes a graphical monochrome liquid crystal display (LCD) with a resolution of 320 x 240
pixels. The character size can vary.
IEC15000270-1-en.vsdx
IEC15000270 V1 EN-US
1 Path
2 Content
3 Status
4 Scroll bar (appears when needed)
• The path shows the current location in the menu structure. If the path is too long to be shown, it is
truncated from the beginning, and the truncation is indicated with three dots.
• The content area shows the menu content.
• The status area shows the current IED time, the user that is currently logged in and the object
identification string which is settable via the LHMI or with PCM600.
• If text, pictures or other items do not fit in the display, a vertical scroll bar appears on the right. The text
in content area is truncated from the beginning if it does not fit in the display horizontally. Truncation is
indicated with three dots.
IEC15000138-1-en.vsdx
IEC15000138 V1 EN-US
The number after : (colon sign) at the end of the function instance, for example, 1 in SMAI1:1, indicates
the number of that function instance.
The function key button panel shows on request what actions are possible with the function buttons.
Each function button has a LED indication that can be used as a feedback signal for the function button
control action. The LED is connected to the required signal with PCM600.
IEC13000281-1-en.vsd
GUID-C98D972D-D1D8-4734-B419-161DBC0DC97B V1 EN-US
The indication LED panel shows on request the alarm text labels for the indication LEDs. Three
indication LED pages are available.
IEC13000240-1-en.vsd
GUID-5157100F-E8C0-4FAB-B979-FD4A971475E3 V1 EN-US
The function button and indication LED panels are not visible at the same time. Each panel is shown by
pressing one of the function buttons or the Multipage button. Pressing the ESC button clears the panel
from the display. Both panels have a dynamic width that depends on the label string length.
The LHMI includes three protection status LEDs above the display: Normal, Pickup and Trip.
There are 15 programmable indication LEDs on the front of the LHMI. Each LED can indicate three
states with the colors: green, yellow and red. The texts related to each three-color LED are divided into
three panels.
There are 3 separate panels of LEDs available. The 15 physical three-color LEDs in one LED group
can indicate 45 different signals. Altogether, 135 signals can be indicated since there are three LED
groups. The LEDs are lit according to priority, with red being the highest and green the lowest priority.
For example, if on one panel there is an indication that requires the green LED to be lit, and on another
panel there is an indication that requires the red LED to be lit, the red LED takes priority and is lit.
The LEDs can be configured with PCM600 and the operation mode can be selected with the LHMI or
PCM600.
Information panels for the indication LEDs are shown by pressing the Multipage button. Pressing that
button cycles through the three pages. A lit or un-acknowledged LED is indicated with a highlight. Such
lines can be selected by using the Up/Down arrow buttons. Pressing the Enter key shows details about
the selected LED. Pressing the ESC button exits from information pop-ups as well as from the LED
panel as such.
The Multipage button has a LED. This LED is lit whenever any LED on any panel is lit. If there are
un-acknowledged indication LEDs, then the Multipage LED Flashes. To acknowledge LEDs, press the
Clear button to enter the Reset menu (refer to description of this menu for details).
There are two additional LEDs which are next to the control buttons and . These LEDs
can indicate the status of two arbitrary binary signals by configuring the OPENCLOSE_LED function
block. For instance, OPENCLOSE_LED can be connected to a circuit breaker to indicate the breaker
open/close status on the LEDs.
IEC16000076-1-en.vsd
IEC16000076 V1 EN-US
The function blocks LEDGEN and GRP1_LEDx, GRP2_LEDx and GRP3_LEDx (x=1-15) controls and
supplies information about the status of the indication LEDs. The input and output signals of the function
blocks are configured with PCM600. The input signal for each LED is selected individually using SMT or
ACT. Each LED is controlled by the GRPn_LEDx (n=1-3) function block that controls the color and the
operating mode.
Each indication LED on local HMI can be set individually to operate in 6 different sequences; two as
follow type and four as latch type. Two of the latching sequence types are intended to be used as a
protection indication system, either in collecting or restarting mode, with reset functionality. The other
two are intended to be used as signalling system in collecting mode with acknowledgment functionality.
There are three status LEDs above the LCD in front of the IED: green, yellow and red.
The green LED has a fixed function that presents the healthy status of the IED. The yellow and red
LEDs are user configured. The yellow LED can be used to indicate that a disturbance report is triggered
(steady) or that the IED is in test mode (flashing). The red LED can be used to indicate a trip command.
• Green LED: unlit > no power; blinking > startup or abnormal situation (IED is not in service); steady >
IED is in service
• Yellow LED: unlit > no attention required; blinking > IED is in Testmode (IED is not in normal service),
or IED is in simulation mode or IED IEC 61850 mod value is set other than its normal value; steady >
at least one of the signals configured to turn the yellow LED on has been active
• Red LED: unlit > no attention required; blinking > user performs a common write from PCM600; steady
> at least one of the signals configured to turn the red LED on has been active
The yellow and red status LEDs are configured in the disturbance recorder function, DRPRDRE, by
connecting a pickup or trip signal from the actual function to a BxRBDR binary input function block using
the PCM600, and configuring the setting to Off,Pickup or Trip for that particular signal.
Collecting mode
• LEDs that are used in the collecting mode of operation are accumulated continuously until the unit is
acknowledged manually. This mode is suitable when the LEDs are used as a simplified alarm system.
When all three inputs (red, yellow and green) are connected to different sources of events for the
same function block, collecting mode shows the highest priority LED color that was activated since
the latest acknowledgment was made. If a number of different indications were made since the latest
acknowledgment, it is not possible to get a clear view of what triggered the latest event without looking
at the sequence of events list. A condition for getting the sequence of events is that the signals have
been engineered in the disturbance recorder.
Re-starting mode
• In the re-starting mode of operation each new pickup resets all previous active LEDs and activates
only those which appear during one disturbance. Only LEDs defined for re-starting mode with the
latched sequence type 6 (LatchedReset-S) will initiate a reset and a restart at a new disturbance. A
disturbance is defined to end a settable time after the reset of the activated input signals or when
the maximum time limit has elapsed. In sequence 6, the restarting or reset mode means that upon
occurrence of any new event, all previous indications will be reset. This facilitates that only the LED
indications related to the latest event is shown.
Acknowledgment/reset GUID-E6727E8F-C28B-4295-AE21-BC5643363805 v3
• Automatic reset
• The automatic reset can only be performed for LED indications defined for re-starting mode with
the latched sequence type 6 (LatchedReset-S). When the automatic reset of the LEDs has been
performed, still persisting indications will be indicated with a steady light.
The sequences can be of type Follow or Latched. For the Follow type, the LED follows the input signal
completely. For the Latched type, each LED latches to the corresponding input signal until it is reset.
The figures below show the function of available sequences selectable for each LED separately. The
following 6 sequences are available:
• Sequence 1: Follow-S
• Sequence 2: Follow-F
• Sequence 3: LatchedAck-F-S
• Sequence 4: LatchedAck-S-F
• Sequence 5: LatchedColl-S
• Sequence 6: LatchedReset-S
For sequence 1 and 2, which are of the Follow type, the acknowledgment (Ack ) /reset function is not
applicable because the indication shown by the LED follows its input signal. Sequence 3 and 4, which
are of the Latched type with acknowledgement, are only working in collecting (Coll) mode. Sequence
5 is working according to Latched type and collecting mode while Sequence 6 is working according
to Latched type and re-starting (Reset) mode. The letters S and F in the sequence names have the
meaning S = Steady and F = Flash.
At the activation of the input signal to any LED, the indication on the corresponding LED obtains a
color that corresponds to the activated input, and operates according to the selected sequence diagrams
shown below.
In the sequence diagrams the different statuses of the LEDs are shown using the following symbols:
This sequence follows the corresponding input signals all the time with a steady light. It does not react
on acknowledgment or reset. Every LED is independent of the other LEDs in its operation.
Activating
signal
LED
IEC01000228_2_en.vsd
IEC01000228 V2 EN-US
Activating
signal GREEN
Activating
signal RED
LED G G R G
IEC09000312_1_en.vsd
IEC09000312 V1 EN-US
This sequence is the same as Sequence 1, Follow-S, but the LEDs are flashing instead of showing
steady light.
This sequence has a latched function and works in collecting mode. Every LED is independent of the
other LEDs in its operation. At the activation of the input signal, the indication starts flashing. After
acknowledgment the indication disappears if the signal is not present any more. If the signal is still
present after acknowledgment it gets a steady light.
Activating
signal
LED
Acknow.
en01000231.vsd
IEC01000231 V1 EN-US
The sequence described below is valid only if the same function block is used for all three
colour LEDs.
When an acknowledgment is performed, all indications that appear before the indication with higher
priority has been reset, will be acknowledged, independent of if the low priority indication appeared
before or after acknowledgment. In figure 18 it is shown the sequence when a signal of lower priority
becomes activated after acknowledgment has been performed on a higher priority signal. The low
priority signal will be shown as acknowledged when the high priority signal resets.
Activating
signal GREEN
Activating
signal RED
R R G
LED
Acknow
IEC09000313_1_en.vsd
IEC09000313 V1 EN-US
Activating
signal GREEN
Activating
signal YELLOW
Activating
signal RED
LED G Y R R Y
Acknow.
IEC09000314-1-en.vsd
IEC09000314 V1 EN-US
Activating
signal GREEN
Activating
signal YELLOW
Activating
signal RED
LED G G R R Y
Acknow.
IEC09000315-1-en.vsd
IEC09000315 V1 EN-US
This sequence has the same functionality as sequence 3, but steady and flashing light have been
alternated.
This sequence has a latched function and works in collecting mode. At the activation of the input signal,
the indication will light up with a steady light. The difference to sequence 3 and 4 is that indications that
are still activated will not be affected by the reset that is, immediately after the positive edge of the reset
has been executed a new reading and storing of active signals is performed. Every LED is independent
of the other LEDs in its operation.
Activating
signal
LED
Reset
IEC01000235_2_en.vsd
IEC01000235 V2 EN-US
Activating
signal GREEN
Activating
signal RED
R G
LED
Reset
IEC09000316_1_en.vsd
IEC09000316 V1 EN-US
In this mode all activated LEDs, which are set to Sequence 6 (LatchedReset-S), are automatically reset
at a new disturbance when activating any input signal for other LEDs set to Sequence 6 LatchedReset-
S. Also in this case indications that are still activated will not be affected by manual reset, that is,
immediately after the positive edge of that the manual reset has been executed a new reading and
storing of active signals is performed. LEDs set for sequence 6 are completely independent in its
operation of LEDs set for other sequences.
Figure 23 shows the timing diagram for two indications within one disturbance.
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000239_2-en.vsd
IEC01000239 V2 EN-US
Figure 23: Operating sequence 6 (LatchedReset-S), two indications within same disturbance
Figure 24 shows the timing diagram for a new indication after tRestart time has elapsed.
Disturbance Disturbance
tRestart tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000240_2_en.vsd
IEC01000240 V2 EN-US
Figure 25 shows the timing diagram when a new indication appears after the first one has reset but
before tRestart has elapsed.
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000241_2_en.vsd
IEC01000241 V2 EN-US
Figure 25: Operating sequence 6 (LatchedReset-S), two indications within same disturbance but with reset of activating
signal between
Disturbance
tRestart
Activating
signal 1
Activating
signal 2
LED 1
LED 2
Automatic
reset
Manual
reset
IEC01000242_2_en.vsd
IEC01000242 V2 EN-US
Local Human-Machine-Interface (LHMI) has five function buttons, directly to the left of the LCD, that can
be configured either as menu shortcut or control buttons. Each button has an indication LED that can be
configured in the application configuration.
When used as a menu shortcut, a function button provides a fast way to navigate between default nodes
in the menu tree. When used as a control, the button can control a binary signal.
Each output on the FNKEYMD1 - FNKEYMD5 function blocks can be controlled from the LHMI function
keys. By pressing a function button on the LHMI, the output status of the actual function block will
change. These binary outputs can in turn be used to control other function blocks, for example, switch
control blocks, binary I/O outputs etc.
FNKEYMD1 - FNKEYMD5 function block also has a number of settings and parameters that control the
behavior of the function block. These settings and parameters are normally set using the PST.
The operation mode is set individually for each output, either OFF, TOGGLE or PULSED.
Setting OFF
Input value
Output value
IEC09000330-2-en.vsd
IEC09000330 V2 EN-US
Setting TOGGLE
In this mode the output toggles each time the function key has been pressed for more than 500ms. Note
that the input attribute is reset each time the function block executes. The function block execution is
marked with a dotted line below.
Input value
500ms 500ms 500ms
Output value
IEC09000331_1_en.vsd
IEC09000331 V2 EN-US
Setting PULSED
In this mode the output sets high (1) when the function key has been pressed for more than 500ms and
remains high according to set pulse time. After this time the output will go back to 0. The input attribute
is reset when the function block detects it being high and there is no output pulse.
Note that the third positive edge on the input attribute does not cause a pulse, since the edge was
applied during pulse output. A new pulse can only begin when the output is zero; else the trigger edge is
lost.
Input value
500ms 500ms 500ms 500ms
IEC09000332_2_en.vsd
IEC09000332 V2 EN-US
All function keys work the same way: When the LHMI is configured so that a certain function button is
of type CONTROL, then the corresponding input on this function block becomes active, and will light the
yellow function button LED when high. This functionality is active even if the function block operation
setting is set to off. It has been implemented this way for safety reasons; the idea is that the function key
LEDs should always reflect the actual status of any primary equipment monitored by these LEDs.
When users are configured through local or central account management, the default behavior of the
function keys are to only operate if a user is logged in, and the user have the required rights. This
authentication check can be configured to be bypassed per function key by changing the ReqAuthority
from ON to OFF. To be able to change this, the user changing it have to have the Security advanced
right.
Authority can be disabled using parameter Authority. Each function key has the parameter Authority,
which can be enabled or disabled using LHMI or PCM 600. User must have Security Advanced rights to
configure the Authority parameter of the function key.
7.1.1 Identification
GUID-1E140EA0-D198-443A-B445-47CEFD2E6134 v2
PMUCONF contains the PMU configuration parameters for both IEC/IEEE 60255-118 (C37.118) and
IEEE 1344 protocols. This means all the required settings and parameters in order to establish and
define a number of TCP and/or UDP connections with one or more PDC clients (synchrophasor client).
This includes port numbers, TCP/UDP IP addresses, and specific settings for IEC/IEEE 60255-118
(C37.118) as well as IEEE 1344 protocols.
The Figure 30 demonstrates the communication configuration diagram. As can be seen, the IED
can support communication with maximum 8 TCP clients and 6 UDP client groups, simultaneously.
Every client can communicate with only one instance of the two available PMUREPORT function
block instances at a time. It means that one client cannot communicate with both PMUREPORT:1 and
PMUREPORT:2 at the same time. However, multiple clients can communicate with the same instance of
PMUREPORT function block at the same time. For TCP clients, each client can decide to communicate
with an existing instance of PMUREPORT by knowing the corresponding PMU ID for that PMUREPORT
instance. Whereas, for UDP clients, the PMUREPORT instance for each UDP channel is defined by the
user in the PMU and the client has to know the PMU ID corresponding to that instance in order to be
able to communicate. More information is available in the sections Short guidance for the use of TCP
and Short guidance for the use of UDP.
IED
PMU ID
1344/C37.118
PMUREPORT: 1 PMUREPORT: 2 TCP Client_1
1344/C37.118
TCP Client_2
1344/C37.118
TCP Client_3
PMU ID: X
1344/C37.118
TCP IP TCP Client_4
PMU ID: Y 1344/C37.118
TCP Port TCP Client_5
1344/C37.118 TCP Client_6
1344/C37.118 TCP Client_7
1344/C37.118 TCP Client_8
PMU ID
IEC140000117-1.en.vsd
IEC140000117 V2 EN-US
Four message types are defined in IEEE C37.118 standard: data, configuration, header, and command
frames. The first three message types are transmitted from the PMU/PDC that serves as the data
source, and the last one (command frame) is received by the PMU/PDC.
These four message types are defined in IEEE C37.118 standard as follows:
There is a default header file, named "ieee1344header.txt", located in the "tools" folder in the IED. The
user is allowed to access and update this text file and write it back to the IED using a FTP client (e.g.
Filezilla).
If the user-defined (updated) header file is larger than 1400 bytes, then it will be truncated to 1400 bytes
in both IEEE C37.118 and IEEE1344 protocols.
Both PMU reporting instances are using the same header file (ieee1344header.txt) and this header file is
used for both IEEE C37.118 and IEEE1344 protocols.
• Commands are machine-readable codes sent to the PMU/PDC for control or configuration.
Port 7001 is used by the SPA on TCP/IP (field service tool). If the port is used for any other
protocol, for example C37.118, the SPA on TCP/IP stops working.
The IED supports 8 concurrent TCP connections using IEEE1344 and/or C37.118 protocol. The
following parameters are used to define the TCP connection between the IED and the TCP clients:
1. 1344TCPport– TCP port for control of IEEE 1344 data for TCP clients
2. C37.118TCPport – TCP port for control of IEEE C37.118 data for TCP clients
As can be seen, there are two separate parameters in the IED for selecting port numbers for TCP
connections; one for IEEE1344 protocol (1344TCPport) and another one for C37.118 protocol (C37.118
TCPport). Client can communicate with the IED over IEEE1344 protocol using the selected TCP port
defined in 1344TCPport, and can communicate with the IED over IEEE C37.118 protocol using the
selected TCP port number in C37.118TCPport.
All the frames (the header frame, configuration frame, command frame and data frame) are
communicated over the same TCP port. The client can request (by sending a command frame) a
configuration and/or header via the TCP channel and the requested configuration and/or header will be
sent back to the client (as Configuration frame/Header frame) over the same TCP channel.
Once the TCP client connects to the IED, the client has to necessarily send a command frame to
start a communication. As shown in Figure 30, the IED can support 2 PMUREPORT instances and
the client has to specify the PMU ID Code in order to know which PMUREPORT data needs to be
sent out to that client. In this figure, X and Y are referring to the user-defined PMU ID Codes for
PMUREPORT instances 1 or 2, respectively. It is up to the TCP client to decide which PMUREPORT
function block shall communicate with that client. Upon successful reception of the first command
by the IED, the PMU ID will be extracted out of the command; if there is a PMUREPORT instance
configured in the IED with matching PMU ID, then the client connection over TCP with the IED will
be established and further communication will take place. Otherwise, the connection will be terminated
and the TCPCtrlCfgErrCnt is incremented in the PMU Diagnostics on the Local HMI under Main menu /
Diagnostics /Communication /PMU diagnostics /PMUSTATUS:1
It is possible to turn off/on the TCP data communication by sending a IEEE1344 or C37.118 command
frame remotely from the client to the PMU containing RTDOFF/RTDON command.
At any given point of time maximum of 8 TCP clients can be connected to the IED for IEEE1344/
C37.118 protocol. If there is an attempt made by the 9th client, the connection to the new client
will be terminated without influencing the connection of the other clients already connected. A list of
active clients can be seen on the Local HMI in the diagnostics menu under Main menu /Diagnostics /
Communication /PMU diagnostics /PMUSTATUS:1
The IED supports maximum of 6 concurrent UDP streams. They can be individually configured to send
IEEE1344 or C37.118 data frames as unicast / multicast. Note that [x] at the end of each parameter is
referring to the UDP stream number (UDP client group) and is a number between 1 and 6. Each of the 6
UDP groups in the IED has the following settings:
It is possible to turn off/on the UDP data communication either by setting the parameter
SendDataUDP[x] to Disable/Enable locally in the PMU or by sending a C37.118 or IEEE1344 command
frame (RTDOFF/RTDON) remotely from the client to the PMU as defined in IEEE 1344/C37.118
standard.
However, such a remote control to stop the streams from the client is only possible when the parameter
SendDataUDP[x] is set to SetByProtocol. The command RTDOFF/RTDON sent by the client is stored in
the IED, i.e. if the IED is rebooted for some reason, the state of the stream will remain the same.
If the parameter SendDataUDP[x] is set toEnable the RTDOFF/RTDON commands received from the
clients are ignored in the IED.
The UDP implementation in the IED is a UDP_TCP. This means that by default, only the data frames are
sent out on UDP stream and the header frame, configuration frame and command frame are sent over
TCP. This makes the communication more reliable especially since commands are sent over TCP which
performs request/acknowledgment exchange to ensure that no data (command in this case) is lost.
However, by setting the parameter SendCfgOnUDP[x] to Enable, the configuration frame 2 (CFG-2) of
IEEEC37.118 data stream is cyclically sent on the corresponding UDP stream (UDP client group[x])
once per minute. This is useful in case of multicast UDP data stream when a lot of PMU clients are
receiving the same UDP stream from the same UDP group (UDP client group[x]).
As shown in Figure 30, there are maximum 2 instances of PMUREPORT function blocks available in the
IED. Each UDP client group[x] can only connect to one of the PMUREPORT instances at the same time.
This is defined in the PMU by the parameter PMUReportUDP[x] which is used to define the instance
number of PMUREPORT function block that must send data on this UDP stream (UDP client group[x]).
The data streams in the IED can be sent as unicast or as multicast. The user-defined IP address set
in the parameter UDPDestAddress[x] for each UDP stream defines if it is a Unicast or Multicast. The
address range 224.0.0.0 to 239.255.255.255 (Class D IP addresses) is treated as multicast. Any other
IP address outside this range is treated as unicast and the UDP data will be only sent to that specific
unicast IP address. In addition to UDPDestAddress[x] parameter, UDPDestPort[x] parameter is used to
define the UDP destination port number for UDP client group[x].
In case of multicast IP, it will be the network switches and routers that take care of replicating the packet
to reach multiple receivers. Multicast mechanism uses network infrastructure efficiently by requiring the
IED to send a packet only once, even if it needs to be delivered to a large number of receivers.
If there are more than one UDP client group defined as multicast, the user shall set different multicast IP
addresses for each UDP group.
The PMU clients receiving the UDP frames can also connect to the IED to request (command frame)
config frame 1, config frame 2, config frame 3, or header frame, and to disable/enable real time data.
This can be done by connecting to the TCP port selected in TCPportUDPdataCtrl[x] for each UDP
group. This connection is done using TCP. The IED allows 4 concurrent client connections for every
TCPportUDPdataCtrl[x] port (for each UDP client group[x]).
If the client tries to connect on TCPportUDPdataCtrl[x] port using a PMU-ID other than what
is configured for that PMUREPORT instance (PMUReportUDP[x]), then that client is immediately
disconnected and the UDPCtrlCfgErrCnt is incremented in PMU Diagnostics on LHMI at Main menu /
Diagnostics /Communication /PMU diagnostics /PMUSTATUS:1
Even if the parameter SendDataUDP[x] is set to Disable it is still possible for the clients to connect on
the TCP port and request the configuration frames.
PID-6710-SETTINGS v4
7.2.1 Identification
GUID-0090956B-48F1-4E8B-9A40-90044C71DF20 v1
The phasor measurement reporting block moves the phasor calculations into an IEC/IEEE 60255-118
(C37.118) and/or IEEE 1344 synchrophasor frame format. The PMUREPORT block contains parameters
for PMU performance class and reporting rate, the IDCODE and Global PMU ID, format of the data
streamed through the protocol, the type of reported synchrophasors, as well as settings for reporting
analog and digital signals.
The message generated by the PMUREPORT function block is set in accordance with the IEC/IEEE
60255-118 (C37.118) and/or IEEE 1344 standards.
There are settings for Phasor type (positive sequence, negative sequence or zero sequence in case
of 3-phase phasor and A, B or C in case of single phase phasor), PMU's Service class (Protection or
Measurement), Phasor representation (polar or rectangular) and the data types for phasor data, analog
data and frequency data.
Synchrophasor data can be reported to up to 8 clients over TCP and/or 6 UDP group clients for multicast
or unicast transmission of phasor data from the IED. More information regarding synchrophasor
communication structure and TCP/UDP configuration is available in section IEC/IEEE 60255-118
(C37.118) Phasor Measurement Data Streaming Protocol Configuration.
Multiple PMU functionality can be configured in the IED, which can stream out same or different
data at different reporting rates or different performance (service) classes. There are 2 instances of
PMU functionality available in the IED. Each instance of PMU functionality includes a set of PMU
reporting function blocks tagged by the same instance number (1 or 2). As shown in the following
figures, each set of PMU reporting function blocks includes PMUREPORT, PHASORREPORT1-4,
ANALOGREPORT1-3, and BINARYREPORT1-3 function blocks. In general, each instance of
PMU functionality has 32 configurable phasor channels (PHASORREPORT1–4 blocks), 24 analog
channels (ANALOGREPORT1-3 blocks), and 28 digital channels (24 digital-report channels in
BINARYREPORT1-3 and 4 trigger-report channels in PMUREPORT function block). Special rules shall
be taken into account in PCM600 for Application Configuration and Parameter Settings of multiple
PMUREPORT blocks. These rules are explained in the Application Manual in section PMU Report
Function Blocks Connection Rules.
Figure 31 shows both instances of the PMUREPORT function block. As seen, each PMUREPORT
instance has 4 predefined binary input signals corresponding to the Bits 03-00: Trigger Reason defined
in STAT field of the Data frame in IEC/IEEE 60255-118 (C37.118) standard. These are predefined
inputs for Frequency Trigger, Rate of Change of Frequency trigger, Magnitude High and Magnitude Low
triggers.
IEC140000118-2-en.vsd
IEC140000118 V2 EN-US
Figure 32 shows both instances of the PHASORREPORT function blocks. The instance number
is visible in the bottom of each function block. For each instance, there are four separate
PHASORREPORT blocks including 32 configurable phasor channels (8 phasor channels in each
PHASORREPORT block). Each phasor channel can be configured as a 3-phase (symmetrical
components positive/negative/zero) or single-phase phasor (A/B/C).
IEC140000119-2-en.vsd
IEC140000119 V2 EN-US
Figure 33 shows both instances of ANALOGREPORT function blocks. The instance number is visible in
the bottom of each function block. For each instance, there are three separate ANALOGREPORT blocks
capable of reporting up to 24 Analog signals (8 Analog signals in each ANALOGREPORT block). These
can include for example transfer of active and reactive power or reporting the milliampere input signals
to the PDC clients as defined in IEEE IEC/IEEE 60255-118 (C37.118) data frame format.
IEC140000120-2-en.vsd
IEC140000120 V2 EN-US
Figure 34 shows both instances of BINARYREPORT function blocks. The instance number is visible in
the bottom of each function block. For each instance, there are three separate BINARYREPORT blocks
capable of reporting up to 24 Binary signals (8 Binary signals in each BINARYREPORT block). These
binary signals can be for example dis-connector or breaker position indications or internal/external
protection alarm signals.
IEC140000121-2-en.vsd
IEC140000121 V2 EN-US
PMUREPORT
BLOCK TIMESTAT
^FREQTRIG
^DFDTTRIG
^MAGHIGHTRIG
^MAGLOWTRIG
ANSI14000301.vsd
ANSI14000301 V1 EN-US
ANALOGREPORT1
^ANALOG1
^ANALOG2
^ANALOG3
^ANALOG4
^ANALOG5
^ANALOG6
^ANALOG7
^ANALOG8
ANSI14000302.vsd
ANSI14000302 V1 EN-US
ANALOGREPORT2
^ANALOG9
^ANALOG10
^ANALOG11
^ANALOG12
^ANALOG13
^ANALOG14
^ANALOG15
^ANALOG16
ANSI14000303.vsd
ANSI14000303 V1 EN-US
ANALOGREPORT3
^ANALOG17
^ANALOG18
^ANALOG19
^ANALOG20
^ANALOG21
^ANALOG22
^ANALOG23
^ANALOG24
ANSI14000304.vsd
ANSI14000304 V1 EN-US
BINARYREPORT1
^BINARY1
^BINARY2
^BINARY3
^BINARY4
^BINARY5
^BINARY6
^BINARY7
^BINARY8
ANSI14000305.vsd
ANSI14000305 V1 EN-US
BINARYREPORT2
^BINARY9
^BINARY10
^BINARY11
^BINARY12
^BINARY13
^BINARY14
^BINARY15
^BINARY16
ANSI14000306.vsd
ANSI14000306 V1 EN-US
BINARYREPORT3
^BINARY17
^BINARY18
^BINARY19
^BINARY20
^BINARY21
^BINARY22
^BINARY23
^BINARY24
ANSI14000307.vsd
ANSI14000307 V1 EN-US
PHASORREPORT1
^PHASOR1
^PHASOR2
^PHASOR3
^PHASOR4
^PHASOR5
^PHASOR6
^PHASOR7
^PHASOR8
ANSI14000308.vsd
ANSI14000308 V1 EN-US
PHASORREPORT2
^PHASOR9
^PHASOR10
^PHASOR11
^PHASOR12
^PHASOR13
^PHASOR14
^PHASOR15
^PHASOR16
ANSI14000309.vsd
ANSI14000309 V1 EN-US
PHASORREPORT3
^PHASOR17
^PHASOR18
^PHASOR19
^PHASOR20
^PHASOR21
^PHASOR22
^PHASOR23
^PHASOR24
ANSI14000310.vsd
ANSI14000310 V1 EN-US
PHASORREPORT4
^PHASOR25
^PHASOR26
^PHASOR27
^PHASOR28
^PHASOR29
^PHASOR30
^PHASOR31
^PHASOR32
ANSI14000311.vsd
ANSI14000311 V1 EN-US
PID-8200-INPUTSIGNALS v1
PID-6238-INPUTSIGNALS v2
PID-6242-INPUTSIGNALS v2
PID-8200-SETTINGS v1
PID-6253-SETTINGS v3
PID-6255-SETTINGS v2
PID-6239-MONITOREDDATA v2
PID-6243-MONITOREDDATA v2
PID-6254-MONITOREDDATA v2
The Phasor Measurement Unit (PMU) features three main functional principles:
• To measure the power system related AC quantities (voltage, current) and to calculate the phasor
representation of these quantities.
• To synchronize the calculated phasors with the UTC by time-tagging, in order to make synchrophasors
(time is reference).
• To publish all phasor-related data by means of TCP/IP or UDP/IP, following the standard IEEE
C37.118 protocol.
The C37.118 standard imposes requirements on the devices and describes the communication message
structure and data. The PMU complies with all the standard requirements with a specific attention to the
Total Vector Error (TVE) requirement. The TVE is calculated using the following equation:
2
( X r ( n ) - X r )2 + ( X i ( n ) - X i )
TVE =
X r2 + X i2
GUID-80D9B1EA-A770-4F50-9530-61644B4DEBBE V1 EN-US (Equation 1)
where,
In order to comply with TVE requirements, special calibration is done in the factory on the analog input
channels of the PMU, resulting in increased accuracy of the measurements. The IEEE C37.118 standard
also imposes a variety of steady state and dynamic requirements which are fulfilled in the IED with the
help of high accuracy measurements and advanced filtering techniques.
Figure 35 shows an overview of the PMU functionality and operation. In this figure, only one
instance of PMUREPORT (PMUREPORT1) is shown. Note that connection of different signals to the
PMUREPORT, in this figure, is only an example and the actual connections and reported signals on the
IEEEC37.118/1344 can be defined by the user.
U/I samples
PMUREPORT1
MU PHASOR1
PHASOR2 8 TCP
U IEEEC37.118 / 1344
TRM SMAI messages NUM
I
U 6 UDC
TRM PHASOR32
I
ANALOG1
I/P MIM SMMI ANALOG2
MEAS. ANALOG24
BINARY1
BINARY2
BIM
OR
BINARY24
PROTECTION
GPS / OP
IRIG-B FREQTRIG
UP
DFDTTRIG
OC
PPS time data MAGHIGHTRIG
MAGLOWTRIG
UV
IEC140000146-1-en.vsd
IEC140000146 V2 EN-US
The TRM modules are individually AC-calibrated in the factory. The calibration data is stored in the
prepared area of the TRM EEProm. The pre-processor block is extended with calibration compensation
and a new angle reference method based on timestamps. The AI3P output of the preprocessor block
is used to provide the required information for each respective PMUREPORT phasor channel. More
information about preprocessor block is available in the section Signal matrix for analog inputs SMAI.
By using patented algorithm the IED can track the power system frequency in quite wide range from 9
Hz to 95 Hz. In order to do that, the three-phase voltage signal shall be connected to the IED. Then IED
can adapt its filtering algorithm in order to properly measure phasors of all current and voltage signals
connected to the IED. This feature is essential for proper operation of the PMUREPORT function or for
protection during generator start-up and shut-down procedure.
This adaptive filtering is ensured by proper configuration and settings of all relevant pre-processing
blocks, see Signal matrix for analog inputs in the Application manual. Note that in all preconfigured IEDs
such configuration and settings are already made and the three-phase voltage are used as master for
frequency tracking. With such settings the IED will be able to properly estimate the magnitude and the
phase angle of measured current and voltage phasors in this wide frequency range.
One of the important functions of a PMU is reporting a very accurate system frequency to the PDC
client. In the IED, each of the PMUREPORT instances is able to report an accurate frequency. Each
voltage-connected preprocessor block (SMAI block) delivers the frequency data, derived from the analog
input AC voltage values, to the respective voltage phasor channel. Every phasor channel has a user-
settable parameter (PhasorXUseFreqSrc) to be used as a source of frequency data for reporting to the
PDC client. It is very important to set this parameter to On for the voltage-connected phasor channels.
There is an automatic frequency source selection logic to ensure an uninterrupted reporting of the
system frequency to the PDC client. In this frequency source selection logic, the following general rules
are applied:
As a result, the first voltage phasor is always the one delivering the system frequency to the PDC
client and if, by any reason, this voltage gets disconnected then the next available voltage phasor
is automatically used as the frequency source and so on. If the first voltage phasor comes back,
since it has a higher priority compare to the currently selected phasor channel, after 500 ms it will
be automatically selected again as the frequency source. There is also an output available on the
component which shows if the reference frequency is good, error or reference channel unavailable.
It is possible to monitor the status of the frequency reference channel (frequency source) for the
respective PMUREPORT instance on Local HMI under Test /Function status /Communication /
Station Communication /PMU Report /PMUREPORT:1 /Outputs , where the FREQREFCHSEL
output shows the selected channel as the reference for frequency and FREQREFCHERR output states
if the reference frequency is good, or if there is an error or if the reference channel is unavailable. For
more information refer to the table PMUREPORT monitored data.
PID-8200-MONITOREDDATA v1
The PMUREPORT function block implements the reporting filters designed to avoid aliasing as the
reporting frequency is lower than the sample/calculation frequency. This means, the synchrophasor and
frequency data which are included in the C37.118 synchrophasor streaming data are filtered in order
to suppress aliasing effects, as the rate of the C37.118 data is slower than the data rate for internal
processing. For this purpose, there is an anti-aliasing filter designed for each reporting rate. The correct
anti-aliasing filter will be automatically selected based on the reporting rate and the performance class
(P/M) settings. The filters are designed to attenuate all aliasing frequencies to at least -40 dB (a gain of
0.01) at M class.
For example, when the synchrophasor measurement follows the fundamental frequency beyond the
fixed Nyquist limits in C37.118 standard, the anti-aliasing filter stopband moves with the measured
fundamental frequency. This has to be considered in connection with C37.118, where the passband is
defined relative to a fixed nominal frequency as shown in the equation 2.
Fs
f0 ±
2
IECEQUATION2418 V1 EN-US (Equation 2)
where,
The internal calculation of analog values in the IED is based on 32 bit floating point. Therefore, if the
user selects to report the analog data (AnalogDataType) as Integer, there will be a down-conversion of a
32 bit floating value to a new 16 bit integer value. In such a case, in order to optimize the resolution of
the reported analog data, the user-defined analog scaling is implemented in the IED.
The analog scaling in the IED is automatically calculated by use of the user-defined parameters
AnalogXRange for the respective analog channel X. The analog data value on the input X will have
a range between -AnalogXRange and +AnalogXRange. The resulting scale factor will be applied to the
reported analog data where applicable.
AnalogXRange ´ 2
S calefactor =
65535.0
offset = 0.0
65535.0 = 16 bit integer range
IECEQUATION2443 V1 EN-US
According to the IEEE C37.118.2 standard, the scale factors (conversion factor) for analog channels are
defined in configuration frame 2 (CFG-2) and configuration frame 3 (CFG-3) frames as follows:
• CFG-2 frame: The field ANUNIT (4 bytes) specifies the conversion factor as a signed 24 bit word for
user defined scaling. Since it is a 24 bit integer, in order to support the floating point scale factor, the
scale factor itself is multiplied in 10, so that a minimum of 0.1 scale factor can be sent over the CFG-2
frame. The resulting scale factor is rounded to the nearest decimal value. The clients receiving the
Analog scale factor over CFG-2 should divide the received scale factor by 10 and then apply it to the
corresponding analog data value.
• CFG-3 frame: The field ANSCALE (8 bytes) specifies the conversion factor as X’ = M * X + B where;
M is magnitude scaling in 32 bit floating point (first 4 bytes) and B is the offset in 32 bit floating point
(last 4 bytes).
The server uses CFG-3 scale factor to scale the analog data values. As a result, the clients which use
scale factors in CFG-3 in order to recalculate analog values, will get a better resolution than using the
scale factors in CFG-2.
Example 1:
AnalogXRange = 3277.0
IECEQUATION2446 V1 EN-US
(3277.0 ´ 2.0 )
sc alefactor = = 0.1 a nd offset = 0.0
65535.0
IECEQUATION2447 V1 EN-US
The scale factor will be sent as 1 on configuration frame 2, and 0.1 on configuration frame 3. The range
of analog values that can be transmitted in this case is -0.1 to -3276.8 and +0.1 to +3276.7.
Example 2:
AnalogXRange = 4915.5
IECEQUATION2448 V1 EN-US
(4915.5 ´ 2.0 )
sc alefac tor = = 0.15 a nd offse t = 0.0
65535.0
IECEQUATION2449 V1 EN-US
The scale factor will be sent as 1 on configuration frame 2, and 0.15 on configuration frame 3. The range
of analog values that can be transmitted in this case is -0.15 to -4915.5 and +0.15 to +4915.5.
Example 3:
(10000000000 ´ 2.0)
sc alefac tor = = 305180.43 a nd offse t = 0.0
65535.5
IECEQUATION2451 V1 EN-US
The scale factor will be sent as 3051804 on configuration frame 2, and 305180.43 on configuration
frame 3. The range of analog values that can be transmitted in this case is -305181 to -10000000000
and +305181 to +10000000000.
GUID-F0BAEBD8-E361-4D50-9737-7DF8B043D66A v6
The IED is compliant with the synchrophasor measurement requirements of IEEE C37.118.1-2011,
including the amendment (IEEE C37.118.1a-2014) for both P and M performance classes. The IED
is also compliant with synchrophasor data transfer requirements of IEEE C37.118.2-2011. There are
two types of internal current transformer cores in the IED, protection and measuring cores. Using the
measuring cores, the IED is compliant with all the synchrophasor measurement requirements. If using
the protection core, for the “signal magnitude-current” steady state test (mentioned in Table 3 of IEEE
C37.118.1-2011 standard), the compliancy to the standard is limited to the current range between 50%
and 200% of rated current for both P and M classes of the standard. The reason is that protection cores
are not designed for accurate measurements on low current levels.
The compliancy to IEEE C37.118.1-2011 standard (including IEEE C37.118.1a-2014) is limited to the
reporting rates up to 60 frames per second which is required by the standard. This means 10, 25, and 50
frames per second for 50 Hz system frequency and 10, 12, 15, 20, 30, and 60 frames per second for 60
Hz system frequency.
SYMBOL-CC V2 EN-US
High impedance differential protection, single phase (HZPDIF) (87) functions can be used when the
involved CTs have the same turns ratio and similar magnetizing characteristics. It utilizes an external
CT secondary current summation by wiring. Actually all CT secondary circuits which are involved in the
differential scheme are connected in parallel. External series resistor, and a voltage dependent resistor
which are both mounted externally to the IED, are also required.
The external resistor unit shall be ordered under "" in the Product Guide.
HZPDIF (87) can be used to protect tee-feeders or busbars, reactors, motors, auto-transformers,
capacitor banks and so on. One such function block is used for a high-impedance restricted earth
fault protection. Three such function blocks are used to form three-phase, phase-segregated differential
protection.
HZPDIF (87)
ISI* TRIP
BLOCK ALARM
BLKTR MEASVOLT
ANSI05000363-2-en.vsd
ANSI05000363 V2 EN-US
PID-6990-INPUTSIGNALS v1
PID-6990-OUTPUTSIGNALS v1
PID-6990-SETTINGS v1
M13075-3 v11
High impedance protection system is a simple technique which requires that all CTs, used in the
protection scheme, have relatively high knee point voltage, similar magnetizing characteristic and the
same ratio. These CTs are installed in all ends of the protected object. In order to make a scheme
all CT secondary circuits belonging to one phase are connected in parallel. From the CT junction
points a measuring branch is connected. The measuring branch is a series connection of one variable
setting resistor (or series resistor) RS with high ohmic value and an over-current element. Thus, the
high impedance differential protection responds to the current flowing through the measuring branch.
However, this current is result of a differential voltage caused by this parallel CT connection across the
measuring branch. Non-linear resistor (that is, metrosil) is used in order to protect entire scheme from
high peak voltages which may appear during internal faults. Typical high impedance differential scheme
is shown in Figure 37. Note that only one phase is shown in this figure.
RS
3 V
I
1
I> (50) 5
GUID-C7509DA3-F6AA-4BA0-9D08-EAA376663AFA V1 EN-US
1. shows one main CT secondary winding connected in parallel with all other CTs, from the same
phase, connected to this scheme.
2. shows the scheme earthing point.
It is of utmost importance to insure that only one earthing point exists in such protection
scheme.
Due to the parallel CT connections the high impedance differential relay can only measure one current
and that is the relay operating quantity. That means that there is no any stabilizing quantity (that is,
bias) in high-impedance differential protection schemes. Therefore in order to guaranty the stability of
the differential relay during external faults the operating quantity must not exceed the set pickup value.
Thus, for external faults, even with severe saturation of some of the current transformers, the voltage
across the measuring branch shall not rise above the relay set pickup value. To achieve that a suitable
value for setting resistor RS is selected in such a way that the saturated CT secondary winding provides
a much lower impedance path for the false differential current than the measuring branch. In case of
an external fault causing current transformer saturation, the non-saturated current transformers drive
most of the spill differential current through the secondary winding of the saturated current transformer
and not through the measuring brunch of the relay. The voltage drop across the saturated current
transformer secondary winding appears also across the measuring brunch, however it will typically be
relatively small. Therefore, the pick-up value of the relay has to be set above this false operating voltage.
See the application manual for operating voltage and sensitivity calculation.
The logic diagram shows the operation principles for the 1Ph High impedance differential protection
function HZPDIF (87), see Figure 38.
The function utilizes the raw samples from the single phase current input connected to it. Thus the
twenty samples per fundamental power system cycle are available to the HZPDIF function. These
current samples are first multiplied with the set value for the used stabilizing resistor in order to get
voltage waveform across the measuring branch. The voltage waveform is then filtered in order to get its
RMS value. Note that used filtering is designed in such a way that it ensures complete removal of the
DC current component which may be present in the primary fault current. The voltage RMS value is then
compared with set Alarm and Trip thresholds. Note that the TRIP signal is intentionally delayed on drop
off for 30 ms within the function. The measured RMS voltage is available as a service value from the
function. The function has block and trip block inputs available as well.
AlarmPickup
0-tAlarm
0
AlarmPickup
0.03s
0
en05000301_ansi.vsd
ANSI05000301 V1 EN-US
Figure 38: Logic diagram for 1Ph High impedance differential protection HZPDIF (87)
M13081-1 v13
8.2.2 Identification
GUID-3081E62B-3E96-4615-97B8-2CCA92752658 v3
Additional security logic for differential protection (LDRGFC, 11) can help the security of the protection
especially when the communication system is in abnormal status or for example when there is
unspecified asymmetry in the communication link. It helps to reduce the probability for mal-operation of
the protection. LDRGFC (11) is more sensitive than the main protection logic to always release operation
for all faults detected by the differential function. LDRGFC (11) consists of four sub functions:
Phase-to-phase current variation takes the current samples as input and it calculates the variation using
the sampling value based algorithm. Phase-to-phase current variation function is a major one to fulfill the
objectives of the startup element.
Zero sequence criterion takes the zero sequence current as input. It increases the security of protection
during the high impedance fault conditions.
Low voltage criterion takes the phase voltages and phase-to-phase voltages as inputs. It increases the
security of protection when the three-phase fault occurred on the weak end side.
Low current criterion takes the phase currents as inputs and it increases the dependability during the
switch onto fault case of unloaded line.
The differential function can be allowed to trip as no load is fed through the line and protection is not
working correctly.
Features:
• Startup element is sensitive enough to detect the abnormal status of the protected system
• Startup element does not influence the operation speed of main protection
• Startup element would detect the evolving faults, high impedance faults and three phase fault on weak
side
• It is possible to block the each sub function of startup element
• Startup signal has a settable pulse time
LDRGFC (11REL)
I3P* BFI_3P
V3P* Pick Up VAB
BLOCK Pick Up VBC
BLKCV Pick Up VCA
BLUC PU_UC
BLK3I0 Pick Up 3I0
BLKUV 27 PU
REMSTEP
ANSI14000015-1-en.vsd
ANSI14000015 V2 EN-US
8.2.5 Signals
PID-8320-INPUTSIGNALS v1
8.2.6 Settings
PID-8320-SETTINGS v1
The additional security logic for differential protection (LDRGFC, 11) takes the current samples, current
RMS values, phase voltage values, phase-to-phase voltage values, zero sequence current and remote
side startup signals as inputs.
Startup signal becomes activated when any one of the current variation startup signal, zero sequence
current startup signal, voltage startup signal, and current startup signal is activated.
Phase-to-phase current variation takes current samples and generates the startup signal by comparing
with the pickup value.
If the zero sequence current value is greater than the pickup value of zero sequence current then the
zero sequence current startup signal will be activated.
Voltage startup signal becomes activated when the any of phase voltage and line voltage is less than the
voltage pickup value and the remote startup signal has to be activated.
Current startup signal becomes activated when the current value in all phases is less than current pickup
value.
The phase-to-phase current variation is the main startup element. It covers most of the abnormal
conditions of the system. The phase-to-phase current variation fails in high impedance faults, three-
phase faults on weak side and switch onto fault on unloaded line because of low sensitivity in these
cases.
Phase-to-phase current variation takes the current samples as input and the signal is evaluated using
the sampling value based algorithm.
Where:
ΔiФФ sampling value of phase-to-phase current variation
ΔIZD setting of fixed threshold, which corresponds to setting ICV>. The default value for the setting is
0.2·IBase, where IBase is the base current.
ΔIT float threshold
1 2T -1
DI T = å | DiFF (t - n) |
T n =T
EQUATION2256 V1 EN-US
Where:
T count of sample values in one cycle
Di (k ) = [i ( k ) - i (k - N )] - [i (k - N ) - i (k - 2 N )]
= i ( k ) - 2i ( k - N ) + i (k - 2 N )
EQUATION2257 V1 EN-US
Time Delay CV
Pick Up VAB
t
cont
OR STCV
cont
ANSI10000295-1-en.vsd
ANSI10000295 V1 EN-US
Time Delay CV is the time setting for the change of current criterion. Phase current samples are
included in input signal I3P.
Zero sequence criterion is mainly for detection of remote IED high resistance faults or some gradual
faults. The criterion takes the zero sequence current as input. Zero sequence current is compared with
PU 3I0 for the t3I0 time to generate the zero sequence current startup signal.
I3P a
a>b t3I0
PU 3I0 b Pick Up 3I0
AND t
BLK3I0
BLOCK OR
ANSI09000778-2-en.vsd
ANSI09000778 V2 EN-US
PU 3I0 is the setting of the maximum possible non-faulted zero sequence current for the protected line.
The default value for this setting is 0.1 · IBase where IBase is the rated current of the CT.
t3I0 is the time setting for the zero sequence current criterion.
The zero sequence current criterion can be blocked by activating the BLK3I0 input signal.
Low voltage criterion is mainly for detection of the three phase faults occurring on weak side with pre-
fault no load condition. The low voltage criterion takes the voltage phase values, voltage phase-to-phase
values and remote startup signals as inputs. The logic for low voltage criterion is shown below:
V3P (UPhN) a
a<b
V_Ph-N b
OR
V3P (UPhPh) a
a<b
V_Ph-Ph< b
tUV
REMSTEP (Recived) 27 PU
AND t
BLKUV
BLOCK OR
ANSI09000779-2-en.vsd
ANSI09000779 V2 EN-US
Voltage phase value is compared with the pickup value of voltage phase and voltage phase-to-phase
value is compared with the pickup value of voltage phase-to-phase. If any of the phase voltage
or phase-to-phase voltages is below the set voltage levels for some time duration (tUV) then the
low voltage PICKUP signal becomes activated after receiving the remote startup signal. Low voltage
criterion can be blocked by activating BLKUV input signal.
If there are more than one remote IED, all the startup signals of the remote ends are logically OR to
obtain the REMSTEP signal from the remote side as input.
The current in each phase is compared to the set current level. If all currents are below setting PU_37,
the STUC output is activated after the set delay tUC.
I3P
a
a<b tUC
PU_37 b PU_UC
AND t
BLUC
BLOCK OR
ANSI09000780-1-en.vsd
ANSI09000780 V1 EN-US
The configuration for the additional security logic for differential protection is shown in Figure 44. The
function will release tripping of the line differential protection up to the end of timer tStUpReset.
Phase-phase STCV
i
current variation
ANSI10000296-2-en.vsd
ANSI10000296 V2 EN-US
Figure 44: Additional security logic for differential protection. Logic diagram for start up element.
Z<->
IEC09000167 V1 EN-US
The line distance protection is an up to five (depending on product variant) zone full scheme protection
function with three fault loops for phase-to-phase faults and three fault loops for phase-to-ground faults
for each of the independent zones. Individual settings for each zone in resistive and reactive reach
gives flexibility for use as back-up protection for transformer connected to overhead lines and cables of
different types and lengths.
Distance measuring zone, quadrilateral characteristic (ZMQPDIS (21)) together with Phase selection
with load encroachment (FDPSPDIS (21)) has functionality for load encroachment, which increases the
possibility to detect high resistive faults on heavily loaded lines, as shown in figure45.
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
Figure 45: Typical quadrilateral distance protection zone with Phase selection with load encroachment function FDPSPDIS
(21) activated
The independent measurement of impedance for each fault loop together with a sensitive and reliable
built-in phase selection makes the function suitable in applications with single-phase autoreclosing.
Built-in adaptive load compensation algorithm prevents overreaching of zone 1 at load exporting end at
phase-to-ground faults on heavily loaded power lines.
The distance protection zones can operate independently of each other in directional (forward or
reverse) or non-directional mode. This makes them suitable, together with different communication
schemes, for the protection of power lines and cables in complex network configurations, such as
parallel lines, multi-terminal lines.
SEMOD115983-4 v8
ZMQPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
LOVBZ TR_C
BLKTR PICKUP
PHSEL PU_A
DIRCND PU_B
PU_C
PHPUND
ANSI06000256-2-en.vsd
ANSI06000256 V2 EN-US
ZMQAPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
LOVBZ TR_C
BLKTR PICKUP
PHSEL PU_A
DIRCND PU_B
PU_C
PHPUND
ANSI09000884-1-en.vsd
ANSI09000884 V1 EN-US
SEMOD54537-4 v5
ZDRDI R (21D)
I3P* STDI RCND
V3P*
ANSI10000007-1-en.vsdx
ANSI10000007 V1 EN-US
9.1.4 Signals
PID-3651-INPUTSIGNALS v6
PID-3650-OUTPUTSIGNALS v6
9.1.5 Settings
GUID-62142086-79A9-46FF-A14F-BA0CDD6B6466 v1
Signals and settings for ZMQPDIS are valid for zone 1 while signals and settings for
ZMQAPDIS are valid for zone 2 - 5
PID-3651-SETTINGS v6
PID-3545-SETTINGS v6
The execution of the different fault loops within the IED are of full scheme type, which means that
each fault loop for phase-to-ground faults and phase-to-phase faults for forward and reverse faults are
executed in parallel.
Figure 49 presents an outline of the different measuring loops for up to five, impedance-measuring
zones. There are 3 to 5 zones depending on product type and variant.
ANSI05000458‐3‐en‐us.vsdx
ANSI05000458 V3 EN-US
Figure 49: The different measuring loops at phase-to-ground fault and phase-to-phase fault.
The use of full scheme technique gives faster operation time compared to switched schemes which
mostly uses a pickup of an overreaching element to select correct voltages and current depending on
fault type. Each distance protection zone performs like one independent distance protection IED with six
measuring elements.
The distance measuring zone includes six impedance measuring loops; three intended for phase-to-
ground faults, and three intended for phase-to-phase as well as, three-phase faults.
The distance measuring zone will essentially operate according to the non-directional impedance
characteristics presented in figure 50 and figure 51. The phase-to-ground characteristic is illustrated
with the full loop reach while the phase-to-phase characteristic presents the per phase reach.
X (Ohm/loop)
X0-X1
Xn =
3
X1+Xn R0-R1
Rn =
3
jn jn
R (Ohm/loop)
RFPG RFPG
X1+Xn
ANSI05000661-3-en.vsd
ANSI05000661 V3 EN-US
X (Ohm/phase)
RFPP R1 RFPP
2 2
X 0 PE - X 1RVPE
XNRV =XX00PEPG--X31XRVPE
1RVPG
XNRV =
XNRV =
3 3
XX
X00PE
0PE
PG --1X
-X 11FWPE
XFWPE
FWPG
XNFW =
=
XNFW =
XNFW
X1 3
3 3
j j
R (Ohm/phase)
RFPP RFPP
2 2
X1
RFPP R1 RFPP
2 2
IEC11000428-1-en.vsd
IEC11000428 V1 EN-US
The fault loop reach with respect to each fault type may also be presented as in Figure. Note in
particular the difference in definition regarding the (fault) resistive reach for phase-to-phase faults and
three-phase faults.
Ip R1 + j X1
Phase-to-ground
VA
element
Phase-to-ground
fault in phase A RFPG
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IA R1 + j X1 Phase-to-phase
VA element A-B
Phase-to-phase
fault in phase A-B RFPP
IB
VB (Arc resistance)
R1 + j X1
IA R1 + j X1 0.5·RFPP Phase-to-phase
VA element A-C
Three-phase
fault
IC
VC
R1 + j X1 0.5·RFPP
ANSI05000181_2_en.vsd
ANSI05000181 V2 EN-US
The R1 and jX1 52 represents the positive sequence impedance from the measuring point to the fault
location. The settings RFPG and RFPP are the eventual fault resistances in the faulty place.
Regarding the illustration of three-phase fault in Figure 52, there is of course fault current flowing also in
the third phase during a three-phase fault. The illustration merely reflects the loop measurement, which
is made phase-to-phase.
The zone can be set to operate in Non-directional, Forward or Reverse direction through the setting
OperationDir . The result from respective set value is illustrated in Figure. The impedance reach is
symmetric, in the sense that it conforms for forward and reverse direction. Therefore, all reach settings
apply to both directions.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
The estimated impedance needs to be inside both characteristics for the zone to start or trip. (The non-
directional start STND is an exception however. It is only dependent on the quadrilateral characteristic.)
In the following figure, the zone with the shorter reactive reach follows the directional line (R∙tan(15⁰))
only up to X1PP, where the quadrilateral characteristic will start to limit the reach.
X (ohm)
X1PP’
X1PP
15° R (ohm)
RFPP/2
-X1PP
R· tan15°
-X1PP’
Line distance protection=IEC19000141=2=en-us=Original.vsdx
IEC19000141 V2 EN-US
The operation of Distance measuring zones, quadrilateral characteristic (ZMQPDIS,21) is blocked if the
magnitude of input currents fall below certain threshold values.
The phase-to-ground loop AG (BG or CG) is blocked if IA (IB or IC) < IMinPUPG.
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-ground loops
will be blocked when IN < IMinOpIR, regardless of the phase currents.
IA (IB or IC) is the RMS value of the current in phase IA (IB or IC). IN is the RMS value of the vector sum
of the three-phase currents, that is, residual current 3I0.
The phase-to-phase loop AB (BC or CA) is blocked if I AB (BC or CA) < IMinPUPP.
All three current limits IMinPUPG, IMinOpIR and IMinPUPP are automatically reduced
to 75% of regular set values if the zone is set to operate in reverse direction, that is,
OperationDir = Reverse.
Fault loop equations use the complex values of voltage, current, and changes in the current. Apparent
impedances are calculated and compared with the set limits. The apparent impedances at phase-to-
phase faults follow equation 3 (example for a phase A to phase B fault).
VA - VB
Zapp =
IA - IB
EQUATION1545 V1 EN-US (Equation 3)
Here V and I represent the corresponding voltage and current phasors in the respective phase Ln (n = 1,
2, 3)
The ground return compensation applies in a conventional manner to phase-to-ground faults (example
for a phase A to ground fault) according to equation 4.
V_A
Z app =
I _ A + IN × KN
EQUATION1546 V1 EN-US (Equation 4)
Where:
V_A, I_A and IN are the phase voltage, phase current and residual current present to the IED
KN
is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
X1 is setting of the reactive positive sequence reach
Here IN is a phasor of the residual current in IED point. This results in the same reach along the line for
all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation 4 is only valid for radial feeder application without load. When load is
considered in the case of single phase-to-ground fault, conventional distance protection might overreach
at exporting end and underreach at importing end. The IED has an adaptive load compensation which
increases the security in such applications.
Measuring elements receive current and voltage information from the A/D converter. The check sums
are calculated and compared, and the information is distributed into memory locations. For each of the
six supervised fault loops, sampled values of voltage (V), current (I), and changes in current between
samples (DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related to the loop impedance
according to equation 5,
X Di
V =R× i + ×
w0 Dt
EQUATION1547 V1 EN-US (Equation 5)
X D Re (I )
Re (V ) = R × Re (I ) + ×
w0 Dt
EQUATION1548 V1 EN-US (Equation 6)
X D Im (I )
Im (V ) = R × Im (I ) + ×
w0 Dt
EQUATION1549 V1 EN-US (Equation 7)
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 8)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real value of the voltage and
substitutes it in the equation for the imaginary part. The equation for the Xm measured reactance can
then be solved. The final result is equal to:
The calculated Rm and Xm values are updated each sample and compared with the set zone reach. The
adaptive tripping counter counts the number of permissive tripping results. This effectively removes any
influence of errors introduced by the capacitive voltage transformers or by other factors.
The directional evaluations are performed simultaneously in both forward and reverse directions, and in
all six fault loops. Positive sequence voltage and a phase locked positive sequence memory voltage are
used as a reference. This ensures unlimited directional sensitivity for faults close to the IED point.
The evaluation of the directionality takes place in Directional impedance quadrilateral function ZDRDIR
(21D). Equation 11 and equation 12 are used to classify that the fault is in forward direction for phase-to-
ground fault and phase-to-phase fault.
where:
AngDir is the setting for the lower boundary of the forward directional characteristic, by default set to 15 (= -15
degrees) and
AngNegRes is the setting for the upper boundary of the forward directional characteristic, by default set to 115 degrees,
see figure 55.
V1 A is positive sequence phase voltage in phase A
V1 AM is positive sequence memorized phase voltage in phase A
IA is phase current in phase A
V1 AB is voltage difference between phase A and B (B lagging A)
V1 ABM is memorized voltage difference between phase A and B (B lagging A)
IAB is current difference between phase A and B (B lagging A)
The setting of AngDir and AngNegRes is by default set to 15 (= -15) and 115 degrees respectively (as
shown in figure 55). It should not be changed unless system studies have shown the necessity.
ZDRDIR gives binary coded directional information per measuring loop on the output STDIRCND.
STDIR= FWD_A*1+FWD_B*2+FWD_C*4+FWD_AB*8+
+FWD_BC*16+FWD_CA*32+REV_A*64+REV_B*128+REV_C*256+
+REV_AB*512+REV_BC*1024+REV_CA*2048
AngNegRes
AngDir
R
en05000722_ansi.vsd
ANSI05000722 V1 EN-US
Figure 55: Setting angles for discrimination of forward and reverse fault in Directional impedance quadrilateral function
ZDRDIR (21D)
The reverse directional characteristic is equal to the forward characteristic rotated by 180 degrees.
The polarizing voltage is available as long as the positive sequence voltage exceeds 5% of the set base
voltage VBase. So the directional element can use it for all unsymmetrical faults including close-in faults.
For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence
voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is restored.
• If the current is still above the set value of the minimum operating current (between 10 and 30% of the
set IED rated current IBase), the condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element in the reverse direction
remains in operation.
• If the current decreases below the minimum operating value, the memory resets until the positive
sequence voltage exceeds 10% of its rated value.
The design of the distance protection zones are presented for all measuring loops: phase-to-ground as
well as phase-to-phase.
Phase-to-ground related signals are designated by AG, BG and CG. The phase-to-phase signals are
designated by AB, BC and CA.
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal for each
separate measuring loop:
• Zone measuring condition, which follows the operating equations described above.
• Group functional input signal (PHSEL), as presented in figure 56.
Two types of function block, ZMQPDIS (21) and ZMQAPDIS (21), are used in the IED. ZMQPDIS (21) is
used for zone 1 and ZMQAPDIS (21) for zone 2 - 5.
The PHSEL input signal represents a connection of six different integer values from Phase selection
with load encroachment, quadrilateral characteristic function FDPSPDIS (21) within the IED, which are
converted within the zone measuring function into corresponding boolean expressions for each condition
separately. Input signal PHSEL is connected to FDPSPDIS or FMPSPDIS (21) function output PHSELZ.
The input signal DIRCND is used to give condition for directionality for the distance measuring
zones. The signal contains binary coded information for both forward and reverse direction. The
zone measurement function filters out the relevant signals depending on the setting of the parameter
OperationDir. It must be configured to the STDIR output on ZDRDIR (21D) function.
PUZMPP
OR
PHSEL
AND NDIR_AB
AB
NDIR_BC
BC AND
CA AND NDIR_CA
AND NDIR_A
AG
AND NDIR_B
BG
NDIR_C
CG AND
OR STNDPE
OR
LOVBZ PHPUND
OR AND
BLOCK
BLK
BLOCFUNC
ANSI99000557-1-en.vsd
ANSI99000557 V2 EN-US
Figure 56: Conditioning by a group functional input signal PHSEL, external start condition
Composition of the phase pickup signals for a case, when the zone operates in a non-directional mode,
is presented in figure 57.
NDIR_A
OR
NDIR_B
PU_A
AND 0
NIDR_C 15ms
NDIR_AB OR PU_B
AND 0
15ms
NDIR_BC
PU_C
NDIR_CA AND 0
OR 15ms
PICKUP
AND 0
OR 15ms
BLK
ANSI09000889-1-en.vsd
ANSI09000889 V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone operates in directional
(forward or reverse) mode, as shown in figure 58.
NDIR_A
DIR_A AND
PU_ZMPG
OR
NDIR_B
DIR_B AND
NDIR_C OR PU_A
AND 0
DIR_C AND 15 ms
NDIR_AB
DIR_AB AND OR PU_B
AND 0
15 ms
NDIR_BC
DIR_BC AND
OR PU_C
NDIR_CA AND 0
AND 15 ms
DIR_CA
PU_ZMPP
OR
BLK
OR PICKUP
AND 0
15 ms
ANSI09000888-2-en.vsd
ANSI09000888 V2 EN-US
Tripping conditions for the distance protection zone one are symbolically presented in figure 59.
Timer tPP=enable
PUZMPP AND tPP
0-tPP AND
0
BLOCFUNC
OR OR
tPG
0-tPG
0 AND
Timer tPG=enable AND
PUZMPG
BLKTR AND 0 TRIP
15 ms
BLK OR
ANSI09000887-3-en.vsdx
ANSI09000887 V3 EN-US
M13842-1 v15
9.2.1 Identification
SYMBOL-DD V1 EN-US
The operation of transmission networks today is in many cases close to the stability limit. Due to
environmental considerations, the rate of expansion and reinforcement of the power system is reduced,
for example, difficulties to get permission to build new power lines. The ability to accurately and reliably
classify the different types of fault, so that single pole tripping and autoreclosing can be used plays an
important role in this matter. Phase selection, quadrilateral characteristic with fixed angle (FDPSPDIS) is
designed to accurately select the proper fault loop in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may make fault resistance
coverage difficult to achieve. Therefore, FDPSPDIS (21) has a built-in algorithm for load encroachment,
which gives the possibility to enlarge the resistive setting of both the phase selection and the measuring
zones without interfering with the load.
The extensive output signals from the phase selection gives also important information about faulty
phase(s), which can be used for fault analysis.
A current-based phase selection is also included. The measuring elements continuously measure three
phase currents and the residual current and, compare them with the set values.
FDPSPDIS (21)
I3P* TRIP
V3P* BFI
BLOCK FWD_A
DIRCND FWD_B
FWD_C
FWD_G
REV_A
REV_B
REV_C
REV_G
NDIR_A
NDIR_B
NDIR_C
NDIR_G
FWD_1PH
FWD_2PH
FWD_3PH
PHG_FLT
PHPH_FLT
PHSELZ
DLECND
ANSI14000047-1-en.vsd
ANSI10000047 V2 EN-US
9.2.4 Signals
PID-3642-INPUTSIGNALS v7
9.2.5 Settings
PID-3642-SETTINGS v7
The difference, compared to the distance zone measuring function, is in the combination of the
measuring quantities (currents and voltages) for different types of faults.
A current-based phase selection is also included. The measuring elements continuously measure three
phase currents and the residual current, and compare them with the set values. The current signals
are filtered by Fourier's recursive filter, and separate trip counter prevents too high overreaching of the
measuring elements.
The characteristic is basically non-directional, but FDPSPDIS (21) uses information from the directional
function to discriminate whether the fault is in forward or reverse direction.
1. Residual current criteria, that is, separation of faults with and without ground connection
2. Regular quadrilateral impedance characteristic or current based criteria
3. Load encroachment characteristics is always active but can be switched off by selecting a high
setting.
The DLECND output is non-directional. The directionality is determined by the distance zones directional
function. There are outputs from FDPSPDIS (21) that indicate whether a pickup is in forward or reverse
direction or non-directional, for example FWD_A, REV_A and NDIR_A.
These directional indications are based on the sector boundaries of the directional function and the
impedance setting of FDPSPDIS (21) function. Their operating characteristics are illustrated in figure 61.
X X X
60°
60° R
R R
60° 60°
en05000668_ansi.vsd
ANSI05000668 V1 EN-US
Figure 61: Characteristics for non-directional, forward and reverse operation of Phase selection with load encroachment,
quadrilateral characteristic FDPSPDIS (21)
The setting of the load encroachment function may influence the total operating characteristic, (for more
information, refer to section "Load encroachment").
The input DIRCND contains binary coded information about the directional coming from the directional
function . It shall be connected to the STDIR output on ZDRDIR, directional measuring block. This
information is also transferred to the input DIRCND on the distance measuring zones, that is, the
ZMQPDIS, distance measuring block.
STDIR= FWD_A*1+FWD_B*2+FWD_C*4+FWD_AB*8+
+FWD_BC*16+FWD_CA*32+REV_A*64+REV_B*128+REV_C*256+
+REV_AB*512+REV_BC*1024+REV_CA*2048
If the binary information is 1 then it will be considered that we have pickup in forward direction in phase
A. If the binary code is 3 then we have pickup in forward direction in phase A and B, binary code 192
means pickup in reverse direction in phase L1 and L2A and B etc.
The PHSELZ or DLECND output contains, in a similar way as DIRCND, binary coded information, in this
case information about the condition for opening correct fault loop in the distance measuring element. It
shall be connected to the PHSEL input on the ZMQPDIS, distance measuring block.
The code built up for release of the measuring fault loops is as follows:
PHSEL = AG*1+BG*2+CG*4+AB*8+BC*16+CA*32
Index PHS in images and equations reference settings for Phase selection with load
encroachment function FDPSPDIS (21).
VA( B , C )
ZPHSn =
IA( B , C )
EQUATION1554 V1 EN-US (Equation 13)
where:
n corresponds to the particular phase (n=1, 2 or 3)
The characteristic for FDPSPDIS (21) function at phase-to-ground fault is according to figure 62. The
characteristic has a fixed angle for the resistive boundary in the first quadrant of 60°.
The resistance RN and reactance XN are the impedance in the ground-return path defined according to
equation 14 and equation 15.
R0 - R1
RN =
3
EQUATION1256 V1 EN-US (Equation 14)
X 0 - X1
XN =
3
EQUATION1257 V1 EN-US (Equation 15)
X (ohm/loop)
Kr·(X1+XN)
RFItRevPG RFItFwdPG
X1+XN
60 deg
RFItFwdPG
RFItRevPG R (Ohm/loop)
60 deg
X1+XN
1
Kr =
tan(60 deg)
RFItRevPG RFItFwdPG
Kr·(X1+XN)
en06000396_ansi.vsd
ANSI06000396 V1 EN-US
Figure 62: Characteristic of FDPSPDIS (21) for phase-to-ground fault (setting parameters in italic), ohm/loop domain
(directional lines are drawn as "line-dot-dot-line")
Besides this, the 3I0 residual current must fulfil the conditions according to equation 16 and equation 17.
3 × I0 ³ 0.5 × IMinPUPG
EQUATION2108-ANSI V1 EN-US (Equation 16)
3I 0 Enable _ PG
3 × I0 ³ × Iph max
100
EQUATION1812-ANSI V1 EN-US (Equation 17)
where:
IMinPUPG is the minimum operation current for forward zones
3I0Enable_PG is the setting for the minimum residual current needed to enable operation in the phase-to-ground fault
loops (in %).
Iphmax is the maximum phase current in any of three phases.
For a phase-to-phase fault, the measured impedance by FDPSPDIS (21) will be according to
equation 18.
Vm - Vn
ZPHS =
-2 × In
EQUATION1813-ANSI V1 EN-US (Equation 18)
Vm is the leading phase voltage, Vn the lagging phase voltage and In the phase current in the lagging
phase n.
X (W / phase)
0.5·RFltRevPP 0.5·RFltFwdPP
Kr·X1
X1
0.5·RFltFwdPP
60 deg
R (W / phase)
60 deg
0.5·RFltRevPP X1
1
Kr =
tan(60 deg)
Kr·X1
0.5·RFltRevPP 0.5·RFltFwdPP
ANSI05000670-2-en.vsd
ANSI05000670 V2 EN-US
Figure 63: The operation characteristics for FDPSPDIS (21) at phase-to-phase fault (setting parameters in italic, directional
lines drawn as "line-dot-dot-line"), ohm/phase domain
In the same way as the condition for phase-to-ground fault, there are current conditions that have to be
fulfilled in order to release the phase-to-phase loop. Those are according to equation 19 or equation 20.
3I 0 < IMinPUPG
EQUATION2109-ANSI V1 EN-US (Equation 19)
INBlockPP
3I 0 < × Iph max
100
EQUATION2110-ANSI V1 EN-US (Equation 20)
where:
IMinPUPG is the minimum operation current for ground measuring loops,
3I0BLK_PP is 3I0 limit for blocking phase-to-phase measuring loop and
Iphmax is maximal magnitude of the phase currents.
The operation conditions for three-phase faults are the same as for phase-to-phase fault, that is
equation , equation and equation are used to release the operation of the function.
However, the reach is expanded by a factor 2/√3 (approximately 1.1547) in all directions. At the same
time the characteristic is rotated 30 degrees, counter-clockwise. The characteristic is shown in figure 64.
X (ohm/phase)
4 × X1
3
90 deg
0.5·RFltFwdPP·K3
X1·K3 2 × RFltFwdPP
3
R (ohm/phase)
0.5·RFltRevPP·K3
2
K3 =
3 30 deg
ANSI05000671-4-en.vsd
ANSI05000671 V4 EN-US
Figure 64: The characteristic of FDPSPDIS (21) for three-phase fault (setting parameters in italic)
Each of the six measuring loops has its own load encroachment characteristic based on the
corresponding loop impedance. The load encroachment functionality is always active, but can be
switched off by selecting a high setting.
The outline of the characteristic is presented in figure 65. As illustrated, the resistive blinders are
set individually in forward and reverse direction while the angle of the sector is the same in all four
quadrants.
RLdFwd
LdAngle LdAngle
R
LdAngle LdAngle
RLdRev
en05000196_ansi.vsd
ANSI05000196 V1 EN-US
The influence of load encroachment function on the operation characteristic is dependent on the chosen
operation mode of FDPSPDIS (21) function. When output signal PHSELZ is selected, the characteristic
for FDPSPDIS (21) (and also zone measurement depending on settings) will be reduced by the load
encroachment characteristic (see figure 66, left illustration).
When output signal DLECND is selected, the operation characteristic will be as the right illustration
in figure 66. The reach will in this case be limit by the minimum operation current and the distance
measuring zones.
X X
R R
PHSELZ DLECND
ANSI10000099-1-en.vsd
ANSI10000099 V1 EN-US
Figure 66: Difference in operating characteristic depending on operation mode when load encroachment is activated
When FDPSPDIS (21) is set to operate together with a distance measuring zone the resultant operate
characteristic could look like in figure 67. The figure shows a distance measuring zone operating in
forward direction. Thus, the operating area is highlighted in black.
"Phase selection"
"quadrilateral" zone
Load encroachment
characteristic
Directional line
en05000673.vsd
IEC05000673 V1 EN-US
Figure 67: Operating characteristic in forward direction when load encroachment is activated
Figure 67 is valid for phase-to-ground. During a three-phase fault, or load, when the quadrilateral
phase-to-phase characteristic is subject to enlargement and rotation the operate area is transformed
according to figure 68. Notice in particular what happens with the resistive blinders of the "phase
selection" "quadrilateral" zone. Due to the 30-degree rotation, the angle of the blinder in quadrant one is
now 90 degrees instead of the original 60 degrees. The blinder that is nominally located to quadrant four
will at the same time tilt outwards and increase the resistive reach around the R-axis. Consequently, it
will be more or less necessary to use the load encroachment characteristic in order to secure a margin
to the load impedance.
X (W / phase)
Phase selection
”Quadrilateral” zone
R (W / phase)
IEC09000049-1-en.vsd
IEC09000049 V1 EN-US
Figure 68: Operating characteristic for FDPSPDIS (21) in forward direction for three-phase fault, ohm/phase domain
The result from rotation of the load characteristic at a fault between two phases is presented in fig 69.
Since the load characteristic is based on the same measurement as the quadrilateral characteristic, it
will rotate with the quadrilateral characteristic clockwise by 30 degrees when subject to a pure phase-to-
phase fault. At the same time the characteristic will "shrink", divided by 2/√3, from the full RLdFw and
RLdRv reach, which is valid at load or three-phase fault.
IEC08000437.vsd
IEC08000437 V1 EN-US
Figure 69: Rotation of load characteristic for a fault between two phases
There is a gain in selectivity by using the same measurement as for the quadrilateral characteristic since
not all phase-to-phase loops will be fully affected by a fault between two phases. It should also provide
better fault resistive coverage in quadrant one. The relative loss of fault resistive coverage in quadrant
four should not be a problem even for applications on series compensated lines.
The operation of the Phase selection with load encroachment function (FDPSPDIS, 21) is blocked if the
magnitude of input currents falls below certain threshold values.
The phase-to-ground loop n is blocked if In<IMinPUPG, where In is the RMS value of the current in
phase n (A or B or C).
Figure 70 presents schematically the general logic diagram for phase-selection function.
Imin
I3P PP
PE STZPHLmn AND
PHSLmn
X
OR
V3P STZPHLm
R,X settings R
LEPHLm AND PHSLm
OR
Binary to word
LEPHLmn
21 enable Enable
b1 – b3
word
b4 – b6
IPELm
I_A IRELPE
Set level
Pickup Iph T
IRELPP PHSELZ
Pickup_N AND 63 F
R
mn = AB, BC, CA
ANSI18000010 V1 EN-US
Figure 71 presents schematically the creation of the phase-to-phase and phase-to-ground operating
conditions. Consider only the corresponding part of measuring and logic circuits, when only a phase-to-
ground or phase-to-phase measurement is available within the IED.
21 enable
AND
LDEblock
0 STPG
AND
3 I 0 Enable _ PG 15ms
3I 0 Iphmax
100 Bool to AND
DLECND
BLOCK integer
Figure 71: Phase-to-phase and phase-to-ground operating conditions (residual current criteria)
A special attention is paid to correct phase selection at evolving faults. A DLECND output signal is
created as a combination of the load encroachment characteristic and current criteria, refer to figure 71.
This signal can be configured to STCND functional input signals of the distance protection zone and
this way influence the operation of the phase-to-phase and phase-to-ground zone measuring elements,
residual current and the load encroachment characteristic.
Figure 72 presents schematically the composition of non-directional phase selective signals NDIR_A
(B or C). Internal signals ZMn and ZMmn (m and n change between A, B and C according to the
phase) represent the fulfilled operating criteria for each separate loop measuring element, that is,
within the impedance characteristic. These signals are released if the setting OperationZ< is set to
Enabled. Similarly, another group of internal signals ILm and ILn represent the fulfilled phase current
measurement criteria, which are released by setting the OperationI> parameter to Enabled.
INDIR_A
INDIR_B
INDIR_C
0
PHSEL_G
OR
15 ms
IRELPG
LDEblockA
I_A AND
OR PHSEL_A
ZMA OR 0
LDEblockB 15 ms
I_B AND
OR
ZMB PHSEL_B
LDEblockC OR 0
I_C AND 15 ms
OR
ZMC
LDEblockAB PHSEL_C
I_A & I_B AND OR 0
OR 15 ms
ZMAB
LDEblockBC
I_B & I_C AND INDIR_AB
OR
ZMBC INDIR_BC
LDEblockCA
I_C & I_A AND
OR INDIR_CA
ZMCA
IRELPP
0 PHSEL_PP
OR
15 ms
ANSI00000545-5-en.vsd
ANSI00000545 V5 EN-US
Composition of the directional (forward and reverse) phase selective signals is presented schematically
in figure 74 and figure 73. The directional criteria appears as a condition for the correct phase
selection in order to secure a high phase selectivity for simultaneous and evolving faults on lines within
the complex network configurations. Internal signals DFWn and DFWnm present the corresponding
directional signals for measuring loops with phases Ln and Lm. Designation FW (figure 74) represents
the forward direction as well as the designation RV (figure 73) represents the reverse direction. All
directional signals are derived within the corresponding digital signal processor.
Figure 73 presents additionally a composition of a PHSELZ output signal, which is created on the basis
of the continuation of the impedance measuring conditions and the load encroachment characteristic.
This signal can be configured to PHSEL functional input signals of the distance protection zone and this
way influence the operation of the phase-to-phase and phase-to-ground zone measuring elements and
their phase related pickup and tripping signals.
INDIR_A
AND
DRV_A
INDIR_AB
REV_A
AND OR 0
DRV_AB 15 ms
INDIR_CA
AND
DRV_CA
REV_G
OR 0
INDIR_B 15 ms
AND
DRV_B
INDIR_AB
REV_B
AND OR 0
15 ms
INDIR_BC INDIR_A
AND INDIR_B
DRV_BC
INDIR_C Bool to PHSELZ
INDIR_C INDIR_AB integer
AND INDIR_BC
DRV_C INDIR_CA
INDIR_BC
0
REV_C
AND OR
15 ms
INDIR_CA
AND REV_PP
OR 0
15 ms
ANSI00000546-3-en.vsd
ANSI00000546 V3 EN-US
AND
INDIR_A
AND FWD_IPH
DFW_A AND OR 15 ms 0
0 15 ms
INDIR_AB
0 FWD_A
AND OR
DFW_AB 15 ms
INDIR_CA
AND
AND
DFW_CA
0 FWD_G
INDIR_B OR
15 ms
AND
DFW_B
AND
INDIR_AB 0 FWD_B
AND OR 15 ms
INDIR_BC 15 ms 0 FWD_2PH
AND OR
AND 0 15 ms
DFW_BC
INDIR_C
AND AND
DFW_C FWD_C
0
INDIR_BC 15 ms
AND OR
INDIR_CA 0 FWD_3PH
AND
AND 15 ms
FWD_PP
OR 0
15 ms
ANSI05000201-3-en.vsd
ANSI05000201 V3 EN-US
Figure 75 presents the composition of output signals TRIP and PICKUP, where internal signals
NDIR_PP, FWD_PP and REV_PP are the equivalent to internal signals NDIR_G, FWD_G and REV_G,
but for the phase-to-phase loops.
TimerPP=Enable
AND AND
0-tPP
0 TRIP
OR OR
TimerPG=Enable
0-tPG
AND 0 AND
NDIR_PP
FWD_PP OR
REV_PP
RI
OR
NDIR_G
FWD_G OR
REV_G
ANSI08000441-3-en.vsd
ANSI08000441 V3 EN-US
9.3.1 Identification
SEMOD168165-2 v2
IEC09000167 V1 EN-US
The line distance protection is an up to five (depending on product variant) zone full scheme protection
with three fault loops for phase-to-phase faults and three fault loops for phase-to-ground fault for each
of the independent zones. Individual settings for each zone resistive and reactive reach give flexibility for
use on overhead lines and cables of different types and lengths.
Distance measuring zone, quadrilateral characteristic for series compensated lines (ZMCPDIS) (21)
function has functionality for load encroachment which increases the possibility to detect high resistive
faults on heavily loaded lines.
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
Figure 76: Typical quadrilateral distance protection zone with load encroachment function activated
The independent measurement of impedance for each fault loop together with a sensitive and reliable
built in phase selection makes the function suitable in applications with single phase auto-reclosing.
Built-in adaptive load compensation algorithm for the quadrilateral function prevents overreaching of
zone1 at load exporting end at phase to ground-faults on heavily loaded power lines.
The distance protection zones can operate, independent of each other, in directional (forward or reverse)
or non-directional mode. This makes them suitable, together with different communication schemes,
for the protection of power lines and cables in complex network configurations, such as parallel lines,
multi-terminal lines.
SEMOD168198-4 v2
ZMCPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
LOVBZ TR_C
BLKTR PICKUP
PHSEL PU_A
DIRCND PU_B
PU_C
PHPUND
ANSI07000036-2-en.vsd
ANSI07000036 V2 EN-US
ZMCAPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
LOVBZ TR_C
BLKTR PICKUP
PHSEL PU_A
DIRCND PU_B
PU_C
PHPUND
ANSI09000890-1-en.vsd
ANSI09000890 V1 EN-US
ZDSRDIR (21D)
I3P* PUFW
V3P* PUREV
STDIRCND
ANSI07000035-2-en.vsd
ANSI07000035 V2 EN-US
Input and output signals is shown for zone 1, zone 2 - 5 are equal.
PID-3639-INPUTSIGNALS v6
PID-3547-INPUTSIGNALS v6
Settings for ZMCPDIS (21) are valid for zone 1, while settings for ZMCAPDIS (21) are valid
for zone 2 - 5
PID-3639-SETTINGS v6
The execution of the different fault loops within the IED are of full scheme type, which means that
ground fault loop for phase-to-ground faults and phase-to-phase faults for forward and reverse faults are
executed in parallel.
Figure 80 presents an outline of the different measuring loops for the basic five, impedance-measuring
zones.
ANSI05000458‐3‐en‐us.vsdx
ANSI05000458 V3 EN-US
Figure 80: The different measuring loops at phase-to-ground fault and phase-to-phase fault
The use of full scheme technique gives faster operation time compared to switched schemes which
mostly uses a pickup of an overreaching element to select correct voltages and current depending on
fault type. Each distance protection zone performs like one independent distance protection IED with six
measuring elements.
Distance measuring zone, quadrilateral characteristic for series compensated lines (ZMCPDIS, 21)
include six impedance measuring loops; three intended for phase-to-ground faults, and three intended
for phase-to-phase as well as, three-phase faults.
The distance measuring zone operates according to the non-directional impedance characteristics
presented in figure 81 and figure 82. The phase-to-ground characteristic is illustrated with the full loop
reach while the phase-to-phase characteristic presents the per-phase reach.
X (Ohm/loop)
R1PG+RNFw
X 0 PG - X 1FwPG
RFRvPG RFFwPG XNFw =
3
PG- -
XX00PE 1XRVPE
1RVPGX 1RvPG
XNRV ==
XNRV XNRv = XXNFw
3
×
3 X 1FwPG
XX0 PE - X-1X
0 PG 1FWPG
FWPE
XNFW==
XNFW
X1FwPG+XNFw 3R 3 0 PG - R1PG
RNFw =
jN jN 3
R (Ohm/loop)
RFRvPG RFFwPG
X1RvPG+XNRv
jN
RFRvPG RFFwPG
ANSI09000625-1-en.vsd
ANSI09000625 V1 EN-US
Figure 81: Characteristic for the phase-to-ground measuring loops, ohm/loop domain
X (Ohm/phase)
j j
jN R (Ohm/phase)
RFRvPP RFFwPP
2 2
X1RvPP
jN
RFRvPP RFFwPP
2 2
IEC09000632-1-en.vsd
IEC09000632 V1 EN-US
The fault loop reach with respect to each fault type may also be presented as in figure 83. Note in
particular the difference in definition regarding the (fault) resistive reach for phase-to-phase faults and
three-phase faults.
Ip R1 + j X1
Phase-to-ground
VA
element
Phase-to-ground
fault in phase A RFPG
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IA R1 + j X1 Phase-to-phase
VA element A-B
Phase-to-phase
fault in phase A-B RFPP
IB
VB (Arc resistance)
R1 + j X1
IA R1 + j X1 0.5·RFPP Phase-to-phase
VA element A-C
Three-phase
fault
IC
VC
R1 + j X1 0.5·RFPP
ANSI05000181_2_en.vsd
ANSI05000181 V2 EN-US
The R1 and jX1 in figure 83 represents the positive sequence impedance from the measuring point to
the fault location. The RFPG and RFPP is the eventual fault resistance in the fault place.
Regarding the illustration of three-phase fault in figure 83, there is of course fault current flowing also in
the third phase during a three-phase fault. The illustration merely reflects the loop measurement, which
is made phase-to-phase.
The zone may be set to operate in Non-directional, Forward or Reverse direction through the setting
OperationDir. The result from respective set value is illustrated in figure 84. It may be convenient to
once again mention that the impedance reach is symmetric, forward and reverse direction. Therefore, all
reach settings apply to both directions.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
The operation of Distance measuring zone, quadrilateral characteristic for series compensated lines
(ZMCPDIS,ZMCAPDIS, 21) is blocked if the magnitude of input currents fall below certain threshold
values.
The phase-to-ground loop AG (BG or CG) is blocked if IA (IB or IC) < IMinPUPG.
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-ground loops
will be blocked when IN < IMinOpIR, regardless of the phase currents.
IA (IB or IC) is the RMS value of the current in phase IA (IB or IC). IN is the RMS value of the vector sum
of the three phase currents, that is, residual current 3I0.
The phase-to-phase loop AB (BC or CA) is blocked if IAB (BC or CA)< IMinPUPP.
All three current limits IMinPUPG, IMinOpIR and IMinPUPP are automatically reduced
to 75% of regular set values if the zone is set to operate in reverse direction, that is,
OperationDir=Reverse.
Fault loop equations use the complex values of voltage, current, and changes in the current.
Apparent impedances are calculated and compared with the set limits. The calculation of the apparent
impedances at ph-ph faults follows equation 21 (example for a phase A to phase B fault).
VA - VB
Zapp =
IA - IB
EQUATION1545 V1 EN-US (Equation 21)
Here V and I represent the corresponding voltage and current phasors in the respective phase.
The ground return compensation applies in a conventional manner to ph-g faults (example for a phase A
to ground fault) according to equation 22.
V_A
Z app =
I _ A + IN × KN
EQUATION1546 V1 EN-US (Equation 22)
Where:
V_A, I_A and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
X1 is setting of the reactive positive sequence reach
Here IN is a phasor of the residual current at the IED point. This results in the same reach along the line
for all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation 22 is only valid for no loaded radial feeder applications. When load is
considered in the case of single phase-to-ground fault, conventional distance protection might overreach
at exporting end and underreach at importing end. IED has an adaptive load compensation which
increases the security in such applications.
Measuring elements receive current and voltage information from the A/D converter. The check sums
are calculated and compared, and the information is distributed into memory locations. For each of the
six supervised fault loops, sampled values of voltage (V), current (I), and changes in current between
samples (DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related to the loop impedance
according to equation 23,
X Di
V =R× i + ×
w0 Dt
EQUATION1547 V1 EN-US (Equation 23)
X D Re (I )
Re (V ) = R × Re (I ) + ×
w0 Dt
EQUATION1548 V1 EN-US (Equation 24)
X D Im (I )
Im (V ) = R × Im (I ) + ×
w0 Dt
EQUATION1549 V1 EN-US (Equation 25)
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 26)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real value of the voltage and
substitute it in the equation for the imaginary part. The equation for the Xm measured reactance can
then be solved. The final result is equal to:
The calculated Rm and Xm values are updated each sample and compared with the set zone reach. The
adaptive tripping counter counts the number of permissive tripping results. This effectively removes any
influence of errors introduced by the capacitive voltage transformers or by other factors.
The directional evaluations are performed simultaneously in both forward and reverse directions, and in
all six fault loops. Positive sequence voltage and a phase locked positive sequence memory voltage are
used as a reference. This ensures unlimited directional sensitivity for faults close to the IED point.
In the basic distance protection function, the control of the memory for polarizing voltage is performed
by an undervoltage control. In case of series compensated line, a voltage reversal can occur with
a relatively high voltage also when the memory must be locked. Thus, a simple undervoltage type
of voltage memory control can not be used in case of voltage reversal. In the option for series
compensated network the polarizing quantity and memory are controlled by an impedance measurement
criterion.
The polarizing voltage is a memorized positive sequence voltage. The memory is continuously
synchronized via a positive sequence filter. The memory is starting to run freely instantaneously when a
voltage change is detected in any phase. A non-directional impedance measurement is used to detect a
fault and identify the faulty phase or phases.
At a three phase fault when no positive sequence voltage remains (all three phases are disconnected)
the memory is used for direction polarization during 100 ms.
The memory predicts the phase of the positive sequence voltage with the pre-fault frequency. This
extrapolation is made with a high accuracy and it is not the accuracy of the memory that limits the time
the memory can be used. The network is at a three phase fault under way to a new equilibrium and the
post-fault condition can only be predicted accurately for a limited time from the pre-fault condition.
In case of a three phase fault after 100 ms the phase of the memorized voltage can not be relied upon
and the directional measurement has to be blocked. The achieved direction criteria are sealed-in when
the directional measurement is blocked and kept until the impedance fault criteria is reset (the direction
is stored until the fault is cleared).
This memory control allows in the time domain unlimited correct directional measurement for all
unsymmetrical faults also at voltage reversal. Only at three phase fault within the range of the set
impedance reach of the criteria for control of the polarization voltage the memory has to be used and
the measurement is limited to 100 ms and thereafter the direction is sealed-in. The special impedance
measurement to control the polarization voltage is set separately and has only to cover (with some
margin) the impedance to fault that can cause the voltage reversal.
The evaluation of the directionality takes place in Directional impedance quadrilateral, including series
compensation (ZDSRDIR,21D) function. Equation 29 and equation 30 are used to classify that the fault
is in forward direction for phase-to-ground fault and phase-to-phase fault.
V 1AM
- AngDir < a n g < AngNeg Re s
IA
EQUATION2005 V2 EN-US (Equation 29)
V 1ABM
- AngDir < a n g < AngNeg Re s
I AB
EQUATION2007 V2 EN-US (Equation 30)
where:
AngDir is the setting for the lower boundary of the forward directional characteristic, by default set to 15 (= -15
degrees) and
AngNegRes is the setting for the upper boundary of the forward directional characteristic, by default set to 115 degrees,
see Figure 85.
V1 AM is positive sequence memorized phase voltage in phase A
IA is phase current in phase A
V1 ABM is memorized voltage difference between phase A and B (B lagging A)
IAB is current difference between phase A and B (B lagging A)
The setting of AngDir and AngNegRes is by default set to 15 (= -15) and 115 degrees respectively, see
Figure 85, and it should not be changed unless system studies have shown the necessity.
ZDSRDIR (21D) generates a binary coded signal on the output STDIR depending on the evaluation
where FWD_A=1 adds 1, REV_A=1 adds 2, FWD_B=1 adds 4.
AngNegRes
AngDir
R
en05000722_ansi.vsd
ANSI05000722 V1 EN-US
Figure 85: Setting angles for discrimination of forward and reverse fault
The reverse directional characteristic is equal to the forward characteristic rotated by 180 degrees.
The design of distance protection zones are presented for all measuring loops: phase-to-ground as well
as phase-to-phase.
Phase-to-ground related signals are designated by AG, BG and CG. The phase-to-phase signals are
designated by AB, BC and CA.
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal for each
separate measuring loop:
• Zone measuring condition, which follows the operating equations described above.
• Group functional input signal (PHSEL), as presented in figure 86.
Two types of function block, ZMCPDIS (21) and ZMCAPDIS (21), are used in the IED. ZMCPDIS (21) is
used for zone 1 and ZMCAPDIS (21) for zone 2 - 5.
The PHSEL input signal represents a connection of six different integer values from the phase selection
function within the IED, which are converted within the zone measuring function into corresponding
boolean expressions for each condition separately. It is connected to Phase selection with load
enchroachment, quadrilateral characteristic (FDPSPDIS, 21) function output PHSELZ.
The internal input signal DIRCND is used to give condition for directionality for the distance measuring
zones. The signal contains binary coded information for both forward and reverse direction. The zone
measurement function filter out the relevant signals on the STDIR input depending on the setting
of OperationDir. It must be configured to the STDIR output on Directional impedance quadrilateral,
including series compensation (ZDSRDIR, 21D) function.
PUZMPP
OR
PHSEL
AND NDIR_AB
AB
NDIR_BC
BC AND
CA AND NDIR_CA
AND NDIR_A
AG
AND NDIR_B
BG
NDIR_C
CG AND
OR STNDPE
OR
LOVBZ PHPUND
OR AND
BLOCK
BLK
BLOCFUNC
ANSI99000557-1-en.vsd
ANSI99000557 V2 EN-US
Composition of the phase pickup signals for a case, when the zone operates in a non-directional mode,
is presented in figure 87.
NDIR_A
OR
NDIR_B
PU_A
AND
NIDR_C
NDIR_AB OR PU_B
AND
NDIR_BC
PU_C
NDIR_CA AND
OR
PICKUP
AND
OR
BLK
en00000488-1_ansi.vsd
ANSI00000488 V2 EN-US
Results of the directional measurement enter the logic circuits, when the zone operates in directional
(forward or reverse) mode, as shown in figure 88.
NDIR_A
DIR_A AND
PU_ZMPG
OR
NDIR_B
DIR_B AND
NDIR_C OR PU_A
AND 0
DIR_C AND 15 ms
NDIR_AB
DIR_AB AND OR PU_B
AND 0
15 ms
NDIR_BC
DIR_BC AND
OR PU_C
NDIR_CA AND 0
AND 15 ms
DIR_CA
PU_ZMPP
OR
BLK
OR PICKUP
AND 0
15 ms
ANSI09000888-2-en.vsd
ANSI09000888 V2 EN-US
Tripping conditions for the distance protection zone one are symbolically presented in figure 89.
Timer tPP=enable
PUZMPP AND tPP
0-tPP AND
0
BLOCFUNC
OR OR
tPG
0-tPG
0 AND
Timer tPG=enable AND
PUZMPG
BLKTR AND 0 TRIP
15 ms
BLK OR
ANSI09000887-3-en.vsdx
ANSI09000887 V3 EN-US
Figure 89: Tripping logic for the distance protection zone one
SEMOD173239-2 v10
9.4.1 Identification
SEMOD154447-2 v2
Z
S00346 V2 EN-US
The numerical mho line distance protection is an up to five (depending on product variant) zone full
scheme protection of short circuit and ground faults.
The zones have fully independent measuring and settings, which gives high flexibility for all types of
lines. Each zone is an individual function block available for independent configuration in ACT.
The IED can be used up to the highest voltage levels. It is suitable for the protection of heavily loaded
lines and multi-terminal lines where the requirement for tripping is one-, two- and/or three-pole.
The independent measurement of impedance for each fault loop together with a sensitive and reliable
phase selection makes the function suitable in applications with single phase autoreclosing.
Load compensation algorithm prevents overreaching at phase-to-ground faults on heavily loaded power
lines, see Figure 90. This Load encroachment characteristic is taken from the FMPSPDIS function.
jX
Operation area
IEC07000117-2-en.vsd
IEC07000117 V2 EN-US
The distance protection zones can operate, independent of each other, in directional (forward or reverse)
or non-directional mode (offset). This makes them suitable, together with different communication
schemes, for the protection of power lines and cables in complex network configurations, such as
parallel lines, multi-terminal lines and so on.
The integrated control and monitoring functions offer effective solutions for operating and monitoring all
types of transmission and sub-transmission lines.
ZMHPDIS (21)
I3P* TRIP
V3P* TR_A
CURR_INP* TR_B
VOLT_INP* TR_C
POL_VOLT* TRPG
BLOCK TRPP
BLKZ PICKUP
BLKZMTD PU_A
BLKHSIR PU_B
BLKTRIP PU_C
BLKPG PHG_FLT
BLKPP PHPH_FLT
EXTNST PU_TIMER
INTRNST
DIRCND
PHSEL*
LDCND
ANSI06000423-2-en.vsd
ANSI06000423 V2 EN-US
PID-3552-INPUTSIGNALS v7
PID-3552-OUTPUTSIGNALS v7
PID-3552-SETTINGS v7
The execution of the different fault loops within the IED are of full scheme type, which means that each
fault loop for phase-to- ground faults and phase-to-phase faults are executed in parallel for all zones.
The use of full scheme technique gives faster operation time compared to switched schemes which
mostly uses a phase selector element to select correct voltages and current depending on fault type.
So each distance protection zone performs like one independent distance protection function with six
measuring elements.
The Mho distance function ZMHPDIS is present with five instances so that five separate zones could
be designed. Each instance can be selected to be either forward or reverse with positive sequence
polarized mho characteristic; alternatively self polarized offset mho characteristics is also available. One
example of the operating characteristic is shown in Figure 92 A) where zone 5 is selected offset mho.
The directional mho characteristic of Figure 92 B) has a dynamic expansion due to the source
impedance. Instead of mho characteristic crossing origin, which is only valid where the source
impedance is zero, the crossing point is moved to the coordinates of the negative source impedance
giving an expansion of the circle of Figure 92 B).
A B
jx X
Mho, zone4
Mho, zone2 R
Mho, zone1
Zs=Z1
Zs=2Z1
R
Offset mho, zone5
IEC09000143-3-en.vsd
IEC09000143 V3 EN-US
Figure 92: Mho, offset mho characteristic and the source impedance influence on the mho characteristic
The polarization quantities used for the mho circle are 100% memorized positive sequence voltages.
This will give a somewhat less dynamic expansion of the mho circle during faults than a plain cross
polarized characteristic. However, if the source impedance is high, the dynamic expansion of the
mho circle might lower the security of the function too much with high loading and mild power swing
conditions.
The mho distance element has a load encroachment function which cuts off a section of the
characteristic when enabled. The function is enabled by setting the setting parameter LoadEnchMode
to Enabled. Enabling of the load encroachment function increases the possibility to detect high resistive
faults without interfering with the load impedance. The algorithm for the load encroachment is located in
the Faulty phase identification with load encroachment for mho function FMPSPDIS (21), where also the
relevant settings can be found. Information about the load encroachment from FMPSPDIS (21) to the
zone measurement is given in binary format to the input signal LDCND.
Each impedance zone can be switched OnEnabled and OffDisabled by the setting parameter Operation.
Each zone can be set to Non-directional, Forward or Reverse by setting the parameter DirModeSel.
The mho characteristics can be classified into - Offset or Directional. The directional mho characteristics
can be set to Offset, Forward or Reverse by the setting parameter DirMode. The offset mho
characteristic can be set to Forward or Reverse or Non-Directional by the setting parameter
OffsetMhoDir.
The operation for phase-to- ground and phase-to-phase fault can be individually switched Enabled and
Disabled by the setting parameter OpModePG and OpModePP.
For critical applications such as for lines with high SIRs as well as CVTs, it is possible to improve the
security by setting the parameter ReachMode to Underreach. In this mode the reach for faults close
to the zone reach is reduced by 20% and the filtering is also introduced to increase the accuracy in
the measuring. If the ReachMode is set to Overreach no reduction of the reach is introduced and no
extra filtering introduced. The latter setting is recommended for overreaching pilot zone, zone 2 or zone
3 elements and reverse zone where overreaching on transients is not a major issue either because of
less likelihood of overreach with higher settings or the fact that these elements do not initiate tripping
unconditionally.
The offset Mho characteristic can be set in Non-directional, Forward or Reverse by the setting parameter
OffsetMhoDir. When Forward or Reverse is selected a directional line is introduced. Information about
the directional line is given from the directional element and given to the measuring element as binary
coded signal to the input DIRCND.
When DirMode is set to offset and offsetMhoDir is set as Non-Directional, ZDMRDIR does not have any
effect on the measurement loop and operation of the function. When DirMode is selected as Forward
or Reverse, a directional line is introduced. Information about the directional line is given from the
directional element (ZDMRDIR) and given to the measuring element as binary coded signal to the input
DIRCND.
The zone reach for phase-to- ground fault and phase-to-phase fault is set individually in polar
coordinates.
The impedance is set by the parameters ZPG and ZPP and the corresponding angles by the parameters
ZAngPG and ZAngPP.
Compensation for ground-return path for faults involving ground is done by setting the parameter KN
and KNAng where KN is the magnitude of the ground-return path and KNAng is the angle of the
ground-return path.
Z 0 - Z1
KN =
3 × Z1
IECEQUATION14023 V1 EN-US (Equation 31)
KNAng = ang
( Z 0 - Z1
3 × Z1
)
EQUATION1807-ANSI V1 EN-US (Equation 32)
where
Z0 is the complex zero sequence impedance of the line in Ω/phase
Z1 is the complex positive sequence impedance of the line in Ω/phase
The phase-to-ground and phase-to-phase measuring loops can be time delayed individually by setting
the parameter tPG and tPP respectively. To release the time delay, the operation mode for the timers,
OpModetPG and OpModetPP, has to be set to On. This is also the case for instantaneous operation. In
instantaneous case, the timers tPG and tPP need to be set as zero.
The operate timers triggering input depends on the parameter ZnTimerSel setting. The parameter
ZnTimerSel can be set to:
• Timers separated: Phase-to-ground and phase-to-phase timers are triggered by the respective
measuring loop pickup signals.
• Timers linked: Start of any of the phase-to-ground or phase-to-phase loops will trigger both the
phase-to-ground or phase-to-phase timers.
• Internal start: Phase-to-ground and phase-to-phase timers are triggered by the INTRNST input.
• Start from PhSel: The phase-to-ground and phase-to-phase timers are triggered by the STCND and
LDCND inputs. Each of the two inputs consist binary status information related to the six measuring
loops. Hence if any of the measuring loop status is high in both two inputs STCND and LDCND, then the
timers will be triggered. In case when LoadEnchMode is off then only STCND enables the timer.
It is not recommended to use this timer setting for the Zone instance where LoadEnchMode is
off.
• External start: Phase-to-ground and phase-to-phase timers are triggered by the EXTNST input.
The activation of input signal BLKZ can be made by external fuse failure function or from the loss of
voltage check in the Mho supervision logic (ZSMGAPC). In both cases the output BLKZ in the Mho
supervision logic shall be connected to the input BLKZ in the Mho distance function block (ZMHPDIS,
21)
The input signal BLKZMTD is activated during some ms after fault has been detected by ZSMGAPC
to avoid unwanted operations due to transients. It shall be connected to the BLKZMTD output signal of
ZSMGAPC function.
At SIR values >10, the use of electronic CVT might cause overreach due to the built-in resonance circuit
in the CVT, which reduce the secondary voltage for a while. The input BLKHSIR is connected to the
output signal HSIR on ZSMGAPC for increasing of the filtering and high SIR values. This is valid only
when permissive underreach scheme is selected by setting ReachMode=Underreach.
The mho algorithm is based on the phase comparison of an operating phasor and a polarizing phasor.
When the operating phasor leads the reference polarizing phasor by 90 degrees or more, the function
operates and gives a trip output.
Mho SEMOD154224-217 v5
The plain Mho circle has the characteristic as in Figure 93. The condition for deriving the angle β is
according to equation 33.
where
The polarized voltage consists of 100% memorized positive sequence voltage (VAB for phase A to B
fault). The memorized voltage will prevent collapse of the Mho circle for close in faults.
IAB·X
Vcomp=VAB - IAB × ZPP
I AB × ZPP
ß
V pol
V AB
IAB·R
en07000109_ansi.vsd
ANSI07000109 V1 EN-US
Figure 93: Simplified mho characteristic and vector diagram for phase A-to-B fault
The characteristic for offset mho is a circle where two points on the circle are the setting parameters
ZPP and ZRevPP. The vector ZPP in the impedance plane has the settable angle AngZPP and the
angle for ZRevPP is AngZPP+180°.
The condition for operation at phase-to-phase fault is that the angle β between the two compensated
voltages Vcomp1 and Vcomp2 is greater than or equal to 90° (figure 94). The angle will be 90° for fault
location on the boundary of the circle.
The angle β for A-to-B fault can be defined according to equation 34.
æ ö
V -IAB × ZPP
b = arg ç ÷
è V -(-IAB × ZRevPP) ø
EQUATION1792-ANSI V1 EN-US (Equation 34)
where
ZRevPP is the positive sequence impedance setting for phase-to-phase fault in reverse direction
IABjX
V ·
Vcomp2 = V =IF·ZF =VAB
IABR
- I AB • Z Re vPP
en07000110_ansi.vsd
ANSI07000110 V1 EN-US
Figure 94: Simplified offset mho characteristic and voltage vectors for phase A-to-B fault.
When forward direction has been selected for the offset mho, an extra criteria beside the one for offset
mho (90<β<270) is introduced, that is the angle φ between the voltage and the current must lie between
the blinders in second quadrant and fourth quadrant. See figure 95. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.
where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR (21D).
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR (21D).
β is calculated according to equation
The directional information is brought to the mho distance measurement from the mho directional
element as binary coded information to the input DIRCND. See Directional impedance element for mho
characteristic (ZDMRDIR ,21D) for information about the mho directional element.
IABjX
ZPP
VAB
ArgNegRes f
IAB
ArgDir
en07000111_ansi
ANSI07000111 V1 EN-US
Figure 95: Simplified offset mho characteristic in forward direction for phase A-to-B fault
The operation area for offset mho in reverse direction is according to figure 96. The operation area in
second quadrant is ArgNegRes+180°.
The β is derived according to equation for the mho circle and φ is the angle between the voltage and
current.
ZPP
ArgNegRes
ϕ
IAB
ArgDir R
VAB
ZRevPP
en06000469_ansi.ep
ANSI06000469 V1 EN-US
Mho SEMOD154224-120 v5
The measuring of ground faults uses ground-return compensation applied in a conventional way. The
compensation voltage is derived by considering the influence from the ground-return path.
For a ground fault in phase A, the compensation voltage Vcomp can be derived, as shown in Figure 97.
where
V pol is the polarizing voltage (memorized VA for Phase A-to- ground fault)
Zloop is the loop impedance, which in general terms can be expressed as
(
Z1+ZN = Z 1 × 1 + KN )
where
Z1 is the positive sequence impedance of the line (Ohm/phase)
KN is the zero-sequence compensator factor
The angle β between the Vcomp and the polarize voltage Vpol for a A-to-ground fault is
( )
b = arg é V A - I A + IN × KN × ZPE ù - arg(Vpol)
ë û
EQUATION1592 V1 EN-US (Equation 36)
where
VA is the phase voltage in faulty phase A
IA is the phase current in faulty phase A
IN is the zero-sequence current in faulty phase A (3I0)
KN Z0-Z1
3 × Z1
the setting parameter for the zero sequence compensation
consisting of the magnitude KN and the angle KNAng.
Vpol is the 100% of positive sequence memorized voltage VA
IA·X
IA·ZN
V comp
I A • Z loop
IA·ZPE
Vpol
f
IA (Ref) IA·R
en06000472_ansi.vsd
ANSI06000472 V1 EN-US
Figure 97: Simplified offset mho characteristic and vector diagram for phase A-to-ground fault
The characteristic for offset mho at ground fault is a circle containing the two vectors from the origin
ZPE and ZRevPE where ZPE and ZrevPE are the setting reach for the positive sequence impedance
in forward respective reverse direction. The vector ZPE in the impedance plane has the settable angle
AngZPE and the angle for ZRevPP is AngZPE+180°.
The condition for operation at phase-to-ground fault is that the angle β between the two compensated
voltages Vcomp1 and Vcomp2 is greater or equal to 90° see figure 98. The angle will be 90° for fault
location on the boundary of the circle.
IAB•jX
V comp1 = VA - IA • ZPE
IA • ZPE
VA
V comp2 = VA - (-IA • ZRevPE)
I AB • R
- IA • Z RevPe
en 06000465_ansi. vsd
ANSI06000465 V1 EN-US
Figure 98: Simplified offset mho characteristic and voltage vector for phase A-to-ground fault
In the same way as for phase-to-phase fault, selection of forward direction of offset mho will introduce
an extra criterion for operation. Beside the basic criteria for offset mho according to equation and
90≤β≤270, also the criteria that the angle φ between the voltage and the current must lie between
the blinders in second and fourth quadrant. See figure 99. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.
where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR (21D).
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR (21D).
β is calculated according to equation
IA jX
VA
ArgNegRes f
IA IA·R
ArgDir
en 06000466_ansi.vsd
ANSI06000466 V1 EN-US
Figure 99: Simplified characteristic for offset mho in forward direction for A-to-ground fault
In the same way as for offset in forward direction, the selection of offset mho in reverse direction will
introduce an extra criterion for operation compare to the normal offset mho. The extra is that the angle
between the fault voltage and the fault current shall lie between the blinders in second and fourth
quadrant. The operation area in second quadrant is limited by the blinder defined as 180° -ArgDir and in
fourth quadrant ArgNegRes+180°, see figure 100.
The conditions for operation of offset mho in reverse direction for A-to-ground fault is 90≤β≤270 and
180°-Argdir≤φ≤ArgNegRes+180°.
The β is derived according to equation for the offset mho circle and φ is the angle between the voltage
and current.
ZPE
ArgNegRes
ϕ
IA
ArgDir R
VA
ZRevPE
en06000470_ansi.ep
ANSI06000470 V1 EN-US
Figure 100: Simplified characteristic for offset mho in reverse direction for A-to-ground fault
Phase-to-ground related signals are designated by AG, BG and CG. The phase-to-phase signals are
designated by AB, BC and CA.
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal for each
separate measuring loop:
• Zone measuring condition, which follows the operating equations described above.
• Group functional input signal (PHSEL), as presented in figure 101.
The ZMHPDIS (21) function block is used in the IED for each zone.
The PHSEL input signal represents a connection of six different integer values from Phase selection
with load encroachment function FMPSPDIS (21) within the IED, which are converted within the zone
measuring function into corresponding boolean expressions for each condition separately. Input signal
PHSEL is connected from FMPSPDIS (21) function output signal PHSCND.
The input signal DIRCND is used to give condition for directionality for the distance measuring
zones. The signal contains binary coded information for both forward and reverse direction. The
zone measurement function filters out the relevant signals depending on the setting of the parameter
DirMode. Input signal DIRCND must be configured to the STDIRCND output signal on ZDMRDIR (21D)
function.
OffsetMhoDir=
Non-directional
AND AND
DirMode=Offset
PHSEL T
AND F
AND
LoadEnchMode=
On/Off
LDCND
T
True F
AND Release
DIRCND
OffsetMhoDir=
Forward/Reverse
AND
DirMode=
Forward/Reverse
BLKZ
BLOCK OR
ANSI11000216-1-en.vsd
ANSI11000216 V1 EN-US
When load encroachment mode is switched on (LoadEnchMode=On), start signal PHSEL is also
checked against LDCND signal.
Results of the directional measurement enter the logic circuits when the zone operates in directional
(forward or reverse) mode, as shown in figure 101.
Release PHG_FLT
OR
AND
PU_AG PU_A
OR
AND
PU_BG
AND
PU_CG
PU_B
OR
AND
PU_AB
AND
PU_BC
PU_C
OR
AND
PU_CA
PICKUP
OR
PHPH_FLT
OR
ANSI11000217-1-en.vsd
ANSI11000217 V1 EN-US
Tripping conditions for the distance protection zone one are symbolically presented in figure 103.
Timer tPP=On
AND 0-tPP
PHPH_FLT 0
OR
Timer tPG=On
AND 0-tPG
PHG_FLT 0
TR_A
PU_A AND
TR_B
PU_B AND
TR_C
PU_C AND
ANSI11000218-2-en.vsd
ANSI11000218 V2 EN-US
Zone timer logic for the distance protection is symbolically presented in figure 104.
STPE
BLOCK
TRPE
&
STPE 40ms
t
tON
& 1 t
Internal
a
a=b
start b STTIMER
&
Internal
a
a<b
start b
tON
STPP 1 t && TRPP
&
STPP
ZnTimerSel
1 2 timers linked
internalCommonStart
3 internal start
phSelStart 4 start from phSel
externalCommonStart
5 external start
IEC12000463 V3 EN-US
SEMOD173242-2 v14
9.5.1 Identification
SEMOD154542-2 v2
The line distance protection is an up to five (depending on product variant) zone full scheme protection
function with three fault loops for phase-to-ground fault for each of the independent zones. Individual
settings for each zone resistive and reactive reach give flexibility for use on overhead lines and cables of
different types and lengths.
The Full-scheme distance protection, quadrilateral for earth fault functions have functionality for load
encroachment, which increases the possibility to detect high resistive faults on heavily loaded lines , see
Figure 105.
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
Figure 105: Typical quadrilateral distance protection zone with Phase selection, quadrilateral characteristic with settable
angle function FRPSPDIS (21) activated
The independent measurement of impedance for each fault loop together with a sensitive and reliable
built in phase selection makes the function suitable in applications with single phase auto-reclosing.
Built-in adaptive load compensation algorithm prevents overreaching of zone1 at load exporting end at
phase to ground faults on heavily loaded power lines.
The distance protection zones can operate, independent of each other, in directional (forward or reverse)
or non-directional mode. This makes them suitable, together with different communication schemes,
for the protection of power lines and cables in complex network configurations, such as parallel lines,
multi-terminal lines.
ZMMPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
BLKZ TR_C
BLKTR PICKUP
PHSEL PU_A
DIRCND PU_B
PU_C
PHPUND
ANSI06000454-2-en.vsd
ANSI06000454 V2 EN-US
ZMMAPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
BLKZ TR_C
BLKTR PICKUP
PHSEL PU_A
DIRCND PU_B
PU_C
PHPUND
ANSI09000947-1-en.vsd
ANSI09000947 V1 EN-US
9.5.4 Signals
PID-3645-INPUTSIGNALS v6
9.5.5 Settings
PID-3645-SETTINGS v6
The different fault loops within the IED are operating in parallel in the same principle as a full scheme
measurement.
Figure 108 presents an outline of the different measuring loops for the basic five, impedance-measuring
zones l.
en07000080_ansi.vsd
ANSI07000080 V1 EN-US
Figure 108: The different measuring loops at line-ground fault and phase-phase fault.
The distance measuring zone include three impedance measuring loops; one fault loop for each phase.
The distance measuring zone will essentially operate according to the non-directional impedance
characteristics presented in Figure 109. The characteristic is illustrated with the full loop reach.
X (Ohm/loop)
X0-X1
Xn =
3
X1+Xn R0-R1
Rn =
3
jn jn
R (Ohm/loop)
RFPG RFPG
X1+Xn
ANSI05000661-3-en.vsd
ANSI05000661 V3 EN-US
Figure 109: Characteristic for the phase-to-ground measuring loops, ohm/loop domain.
IA R1 + j X1
Phase-to-ground
VA
element
Phase-to-ground
fault in phase A RFPG
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 ) en06000412_ansi.vsd
ANSI06000412 V1 EN-US
The R1 and jX1 in Figure 110 represent the positive sequence impedance from the measuring point to
the fault location. The RFPG is presented in order to “convey” the fault resistance reach.
The zone may be set to operate in , , Disabled or direction through the setting OperationDir. The result
from respective set value is illustrated in Figure 111. The impedance reach is symmetric, in the sense
that it is conform for forward and reverse direction. Therefore, all reach settings apply to both directions.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
The operation of the distance measuring zone is blocked if the magnitude of input currents fall below
certain threshold values.
The phase-to-ground loop AG (BG or CG) is blocked if IA (IB or IC) < IMinPUPG.
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-ground loops
will be blocked when IN < IMinOpIR, regardless of the phase currents.
IA (IB or IC) is the RMS value of the current in phase IA (IB or IC). IN is the RMS value of the vector sum
of the three phase currents, that is, residual current 3I0.
Both current limits IMinPUPG and IMinOpIR are automatically reduced to 75% of regular set
values if the zone is set to operate in reverse direction, that is, =.
Fault loop equations use the complex values of voltage, current, and changes in the current. Apparent
impedances are calculated and compared with the set limits.
Here V and I represent the corresponding voltage and current phasors in the respective phase A, B or C.
VA
Z app =
IA + I N × KN
EQUATION1811-ANSI V1 EN-US (Equation 38)
Where:
VA, IA and IN are the phase voltage, phase current and residual current present to the IED
KN is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
X1 is setting of the reactive positive sequence reach
Here IN is a phasor of the residual current in IED point. This results in the same reach along the line for
all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation 38 is only valid for no loaded radial feeder applications. When load is
considered in the case of single phase-to-ground fault, conventional distance protection might overreach
at exporting end and underreach at importing end. IED has an adaptive load compensation which
increases the security in such applications.
Measuring elements receive current and voltage information from the A/D converter. The check sums
are calculated and compared, and the information is distributed into memory locations. For each of the
six supervised fault loops, sampled values of voltage (V), current (I), and changes in current between
samples (DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related to the loop impedance
according to equation 39,
X Di
V =R× i + ×
w0 Dt
EQUATION1547 V1 EN-US (Equation 39)
X D Re (I )
Re (V ) = R × Re (I ) + ×
w0 Dt
EQUATION1548 V1 EN-US (Equation 40)
X D Im (I )
Im (V ) = R × Im (I ) + ×
w0 Dt
EQUATION1549 V1 EN-US (Equation 41)
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 42)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real value of the voltage and
substitute it in the equation for the imaginary part. The equation for the Xm measured reactance can then
be solved. The final result is equal to:
The calculated Rm and Xm values are updated each sample and compared with the set zone reach. The
adaptive tripping counter counts the number of permissive tripping results. This effectively removes any
influence of errors introduced by the capacitive voltage transformers or by other factors.
The directional evaluations are performed simultaneously in both forward and reverse directions, and in
all six fault loops. Positive sequence voltage and a phase locked positive sequence memory voltage are
used as a reference. This ensures unlimited directional sensitivity for faults close to the IED point.
The evaluation of the directionality takes place in the Directional impedance element for mho
characteristic ZDMRDIR (21D) function. Equation 45 is used to classify that the fault is in forward
direction for line-to-ground fault.
0.85 × V 1A + 0.15 × V 1 AM
- AngDir < Ang < AngNeg Re s
IA
EQUATION1618 V1 EN-US (Equation 45)
where:
AngDir is the setting for the lower boundary of the forward directional characteristic, by default set to 15 (= -15
degrees) and
AngNegRes is the setting for the upper boundary of the forward directional characteristic, by default set to 115 degrees,
see figure 112.
V1 A is positive sequence phase voltage in phase A
V1 AM is positive sequence memorized phase voltage in phase A
IA is phase current in phase A
The setting of AngDir and AngNegRes is by default set to 15 (= -15) and 115 degrees respectively (see
figure 112) and it should not be changed unless system studies have shown the necessity.
ZDMRDIR (21D) gives a binary coded signal on the output STDIRCND depending on the evaluation
where FWD_A=1 adds 1, REV_A=1 adds 2, FWD_B=1 adds 4 etc.
AngNegRes
AngDir
R
en05000722_ansi.vsd
ANSI05000722 V1 EN-US
Figure 112: Setting angles for discrimination of forward and reverse fault
The reverse directional characteristic is equal to the forward characteristic rotated by 180 degrees.
The polarizing voltage is available as long as the positive-sequence voltage exceeds 5% of the set base
voltage VBase. So the directional element can use it for all unsymmetrical faults including close-in faults.
For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence
voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is restored.
• If the current is still above the set value of the minimum operating current (between 10 and 30% of the
set IED rated current IBase), the condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element in the reverse direction
remains in operation.
• If the current decreases below the minimum operating value, the memory resets until the positive
sequence voltage exceeds 10% of its rated value.
The design of distance protection zone 1 is presented for all measuring phase-to-ground loops.
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal for each
separate measuring loop:
• Zone measuring condition, which follows the operating equations described above.
• Group functional input signal (PHSEL), as presented in figure 113.
The PHSEL input signal represents a connection of six different integer values from the phase selection
function within the IED, which are converted within the zone measuring function into corresponding
boolean expressions for each condition separately. It is connected to the Phase selection with load
enchroachment, quadrilateral characteristic (FDPSPDIS,21) function output STCNDZ.
The input signal DIRCND is used to give condition for directionality for the distance measuring
zones. The signal contains binary coded information for both forward and reverse direction. The zone
measurement function filter out the relevant signals on the DIRCND input depending on the setting of
the parameter OperationDir. It shall be configured to the DIRCND output on the Directional impedance
element for mho characteristic (ZDMRDIR,21D) function.
PHSEL
AND NDIR_A
AG
AND NDIR_B
BG
NDIR_C
CG AND
OR NDIR_G
OR
LOVBZ PHPUND
OR AND
BLOCK
BLK
en06000408_ansi.vsd
ANSI06000408 V1 EN-US
Composition of the phase pickup signals for a case, when the zone operates in a non-directional mode,
is presented in figure 114.
NDIR_A PU_A
AND 0
15 ms
NDIR_B
PU_B
AND 0
15 ms
NDIR_C PU_C
AND 0
15 ms
AND 0 PICKUP
OR 15 ms
BLK
en06000409_ansi.vsd
ANSI06000409 V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone operates in directional
(forward or reverse) mode, see figure 115.
NDIR_A
DIR_A AND
OR PU_2MPG
NDIR_B &
DIR_B AND
NDIR_C PU_A
& 0
DIR_C AND 15 ms
0
PU_B
&
15 ms
PU_C
& 0
15 ms
BLK
OR 0
PICKUP
&
15 ms
en07000081_ansi.vsd
ANSI07000081 V1 EN-US
Tripping conditions for the distance protection zone one are symbolically presented in figure 116.
Timer tPG=Enable
AND 0-tPG
PUZMPG 0
TRIP
BLKTR AND 0
15 ms
TR_A
PU_A AND
TR_B
PU_B AND
TR_C
PU_C AND
en07000082_ansi.vsd
ANSI07000082 V1 EN-US
Figure 116: Tripping logic for the distance protection zone one
9.6.1 Identification
SEMOD155886-2 v2
GUID-39299546-12A2-4D9D-86D0-A33F423944E4 v2
ZDMRDIR (21D)
I3P* DIR_CURR
V3P* DIR_VOLT
DIR_POL
PUFW
PUREV
STDIRCND
ANSI06000422-2-en.vsd
ANSI06000422 V2 EN-US
ZDARDIR
I3P* FWD_G
V3P* REV_G
I3PPOL* DIREFCND
DIRCND
ANSI06000425-2-en.vsd
ANSI06000425 V2 EN-US
9.6.4 Signals
PID-3546-INPUTSIGNALS v7
9.6.5 Settings
PID-3546-SETTINGS v7
9.6.7.1 Directional impedance element for mho characteristic ZDMRDIR (21D) SEMOD154817-5 v7
The evaluation of the directionality takes place in Directional impedance element for mho characteristic
(ZDMRDIR ,21D). Equation 46 and equation 47 are used to classify that the fault is in the forward
direction for phase-to-ground fault and phase-to-phase fault respectively.
0.85 × V 1A + 0.15 × V 1 AM
- AngDir < Ang < AngNeg Re s
IA
EQUATION1618 V1 EN-US (Equation 46)
Where:
AngDir Setting for the lower boundary of the forward directional characteristic, by default set to
15 (= -15 degrees)
AngNegRes Setting for the upper boundary of the forward directional characteristic, by default set to
115 degrees, see figure 119 for mho characteristics.
V1A Positive sequence phase voltage in phase A
V1AM Positive sequence memorized phase voltage in phase A
IA Phase current in phase A
V1AB Voltage difference between phase A and B (B lagging A)
V1ABM Memorized voltage difference between phase A and B (B lagging A)
IAB Current difference between phase A and B (B lagging A)
The default settings for AngDir and AngNegRes are 15 (= -15) and 115 degrees respectively (see figure
119) and they should not be changed unless system studies show the necessity.
If one sets DirEvalType to Comparator (which is recommended when using the mho characteristic)
then the directional lines are computed by means of a comparator-type calculation, meaning that the
directional lines are based on mho-circles (of infinite radius). The default setting value Impedance
otherwise means that the directional lines are implemented based on an impedance calculation
equivalent to the one used for the quadrilateral impedance characteristics.
When Directional impedance element for mho characteristic (ZDMRDIR) is used together
with Fullscheme distance protection, mho characteristic (ZMHPDIS) the following settings for
parameter DirEvalType is vital:
X
Zset reach point
AngNegRes
-AngDir R
-Zs
en06000416_ansi.vsd
ANSI06000416 V1 EN-US
The reverse directional characteristic is equal to the forward characteristic rotated by 180 degrees.
The code built up for release of the measuring fault loops is as follows: STDIRCND = AN*1 + BN*2 +
CN*4 + AB*8 + BC*16 + CA*32
Example: If only AN pickup, the value is 1, if pickup in AN and CN are detected, the value is 1+4=5.
The polarizing voltage is available as long as the positive-sequence voltage exceeds 5% of the set base
voltage VBase, thus the directional element can use it for all unsymmetrical faults including close-in
faults.
For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence
voltage, ensures correct directional discrimination.
The memory voltage is used for 100ms or until the positive sequence voltage is restored. After 100ms,
the following occurs:
• If the current is still above the set value of the minimum operating current the condition seals in.
• If the current decreases below the minimum operate value, no directional indications will be given until
the positive sequence voltage exceeds 10% of its rated value.
The Directional impedance element for mho characteristic (ZDMRDIR ,21D) function has the following
output signals:
The STDIRCND output provides an integer signal that depends on the evaluation and is derived from a
binary coded signal as follows:
The PUFW output is a logical signal with value 1 or 0. It is made up as an OR-function of all the forward
starting conditions, that is, FWD_A, FWD_B, FWD_C, FWD_AB, FWD_BC and RWD_CA. The PUREV
output is similar to the PUFW output, the only difference being that it is made up as an OR-function of all
the reverse starting conditions, that is, REV_A, REV_B, REV_C. REV_AB, REV_BC and REV_CA.
• The greatest amount of expansion for improved resistive coverage. These elements always expand
back to the source.
• Memory action for all fault types. This is very important for close-in three-phase faults.
• A common polarizing reference for all six distance-measuring loops. This is important for single-pole
tripping, during a pole-open period.
There are however some situations that can cause security problems like reverse phase to phase
faults and double phase-to-ground faults during high load periods. To solve these, additional directional
element is used.
For phase-to-ground faults, directional elements using sequence components are very reliable for
directional discrimination. The directional element can be based on one of following types of polarization:
• Zero-sequence voltage
• Negative-sequence voltage
• Zero-sequence current
These additional directional criteria are evaluated in the Additional distance protection directional
function for ground faults (ZDARDIR).
Zero-sequence voltage polarization is utilizing the phase relation between the zero-sequence voltage
and the zero-sequence current at the location of the protection. The measurement principle is illustrated
in figure 120.
- 3V 0
AngleOp
AngleRCA
3I0
en06000417_ansi.vsd
ANSI06000417 V1 EN-US
Figure 120: Principle for zero-sequence voltage polarized additional directional element
Negative-sequence voltage polarization is utilizing the phase relation between the negative-sequence
voltage and the negative-sequence current at the location of the protection.
Zero-sequence current polarization is utilizing the phase relation between the zero-sequence current at
the location of the protection and some reference zero-sequence current, for example, the current in the
neutral of a power transformer.
Z0 SA I0 I0
Z0 Line Z0SB
Characteristic
angle
V0 V0
K*I0
V0 + K*I0
IF
en06000418_ansi.vsd
ANSI06000418 V1 EN-US
Note that the sequence based additional directional element cannot give per phase information about
direction to fault. This is why it is an AND-function with the normal directional element that works on a
per phase base. The enable signals are per phase and to enable the measuring element in a specific
phase, both the additional directional element and the normal directional element, for that phase must
indicate correct direction.
These polarization quantities, voltage and current, are stabilized against minimum polarizing voltage
(UPOL>) and current (IPOL>). That means if polarizing voltage is greater than UPOL> setting, and if
polarizing current is greater than IPol>, then only they are used for direction determination.
Normal
directional Release of distance
element measuring element
A, B, C A, B, C
AND
Additional
directional AND per
element phase
en06000419_ansi.vsd
ANSI06000419 V1 EN-US
9.7.1 Identification
GUID-030C086A-8301-481E-BA0A-6550A9C1482E v2
The Mho impedance supervision logic (ZSMGAPC) includes features for fault inception detection and
high SIR detection. It also includes the functionality for loss of potential logic as well as for the pilot
channel blocking scheme.
ZSMGAPC
I3P* BLKZMTD
V3P* BLKCHST
BLOCK CHSTOP
REVSTART HSIR
BLOCKCS
CBOPEN
ANSI06000426-2-en.vsd
ANSI06000426 V2 EN-US
9.7.4 Signals
PID-6718-INPUTSIGNALS v1
9.7.5 Settings
PID-6718-SETTINGS v1
The aim for the fault inception detector is to quickly detect that a fault has occurred in the system. The
fault detector detects a fault when there is a sufficient change in at least one current and at the same
time there is a sufficient change in at least one voltage. A change is defined roughly by the difference
between the present instantaneous value and the one from one power system cycle before. The change
is sufficient if it exceeds the related threshold value. DeltaI and DeltaV for phase currents and voltages.
Delta3I0 and Delta3V0 for residual current and voltage.
If the setting is set to Enabled in blocking scheme and the fault inception function has detected a system
fault, a block signal BLKCHST is issued and send to remote end in order to block the overreaching
zones. Different criteria has to be fulfilled for sending the BLKCHST signal:
If it is later detected that it was an internal fault that made the function issue the BLKCHST signal, the
function issues a CHSTOP signal to unblock the remote end. The criteria that have to be fulfilled for this
are:
1. The function has to be in pilot mode, that is, the setting has to be set to Enabled
2. The carrier send signal should be blocked, that is, input signal BLOCKCS is On and,
3. A reverse fault should not have been detected while the carrier send signal was not blocked, that is,
input REVSTART should not have been activated before BLOCKCS.
If loss of voltage is detected, but not a fault inception, the distance protection function is blocked. This
is also the case if a fuse failure is detected by the external fuse failure function and activate the input
FUSEFAIL. Those blocks are generated by activating the output BLKZ, which are connected to the input
BLKZ on the distance Mho function block.
During fault inception a lot of transients are developed which in turn might cause the distance function
to overreach. The Mho supervision logic (ZSMGAPC) increases the filtering during the most transient
period of the fault. This is done by activating the output BLKZMTD, which is connected to the input
BLKZMTD on mho distance function block.
High SIR values increases the likelihood that CVT will introduce a prolonged and distorted transient,
increasing the risk for overreach of the distance function.
The SIR function calculates the SIR value as the source impedance divided by the setting Zreach and
activates the output signal HSIR if the calculated value for any of the six basic shunt faults exceed the
setting . The HSIR signal is intended to block the delta based mho impedance function.
9.8.1 Identification
SEMOD155879-2 v3
The ability to accurately and reliably classify different types of fault so that single phase tripping and
autoreclosing can be used plays an important roll in today's power systems.
The phase selection function is design to accurately select the proper fault loop(s) in the distance
function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may in some cases interfere
with the distance protection zone reach and cause unwanted operation. Therefore the function has a
built in algorithm for load encroachment, which gives the possibility to enlarge the resistive setting of the
measuring zones without interfering with the load.
The output signals from the phase selection function produce important information about faulty
phase(s), which can be used for fault analysis as well.
FMPSPDIS
I3P* PU_A
V3P* PU_B
BLOCK PU_C
ZSTART PHG_FLT
TR3PH PHSCND
1POLEAR PLECND
DLECND
PICKUP
ANSI06000429-2-en.vsd
ANSI06000429 V2 EN-US
9.8.4 Signals
PID-3541-INPUTSIGNALS v9
9.8.5 Settings
PID-3541-SETTINGS v9
Faulty phase identification with load encroachment for mho (FMPSPDIS, 21) function can be
decomposed into six different parts:
The delta based fault detection function uses adaptive technique and is based on patent US4409636.
The aim of the delta based phase selector is to provide very fast and reliable phase selection for
releasing of tripping from the high speed Mho measuring element and is essential to Directional
Comparison Blocking scheme (DCB), which uses Power Line Carrier (PLC) communication system
along the protected line.
The current and voltage samples for each phase passes through a notch filter that filters out the
fundamental components. Under steady state load conditions or when no fault is present, the output of
the filter is zero or close to zero. When a fault occurs, currents and voltages change resulting in sudden
changes in the currents and voltages resulting in non-fundamental waveforms being introduced on the
line. At this point the notch filter produces significant non-zero output. The filter output is processed by
the delta function. The algorithm uses an adaptive relationship between phases to determine if a fault
has occurred, and determines the faulty phases.
The current and voltage delta based phase selector gives a real output signal if the following criterion is
fulfilled (only phase A shown):
Max(ΔVA,ΔVB,ΔVC)>DeltaVMinOp
Max(ΔIA,ΔIB,ΔIC)>DeltaIMinOp
where:
ΔVA, ΔVB and ΔVC are the voltage change between sample t and sample t-1
DeltaVMinOp and DeltaIMinOp are the minimum harmonic level settings for the voltage and current
filters to decide that a fault has occurred. A slow evolving fault may
not produce sufficient harmonics to detect the fault; however, in such a
case speed is no longer the issue and the sequence components phase
selector will operate.
The delta voltages ΔVA(B,C) and delta current ΔIA(B,C) are the voltage and current between sample t
and sample t-1.
The delta phase selector employs adaptive techniques to determine the fault type. The logic determines
the fault type by summing up all phase values and dividing by the largest value. Both voltages and
currents are filtered out and evaluated. The condition for fault type classification for the voltages and
currents can be expressed as:
The output signal is 1 for single phase-to-ground fault, 2 for phase-to-phase fault and 3 for three-phase
fault. At this point the filter does not know if ground was involved or not.
Typically there are induced harmonics in the non-faulted lines that will affect the result. This method
allows for a significant tolerance in the evaluation of FaultType over its entire range.
When a single phase-to-ground fault has been detected, the logic determines the largest quantity, and
asserts that phase. If phase-to-phase fault is detected, the two largest phase quantities will be detected
and asserted as outputs.
The faults detected by the delta based phase selector are coordinated in a separate block. Different
phases of faults may be detected at slightly different times due to differences in the angles of incidence
of fault on the wave shape. Therefore the output is forced to wait a certain time by means of a timer.
If the timer expires, and a fault is detected in one phase only, the fault is deemed as phase-to-ground.
This way a premature single phase-to-ground fault detection is not released for a phase-to-phase fault.
If, however, ground current is detected before the timer expires, the phase-to-ground fault is released
sooner.
If another phase picks up during the time delay, the wait time is reduced by a certain amount. Each
detection of either phase-to-ground or additional phases further reduce the initial time delay and allow
the delta phase selector output to be faster. There is no time delay if all three phases are faulty.
The delta function is released if the input DELTAREL is activated at the same time as input DELTABLK
is not activated. Activating the DELTABLK input blocks the delta function. The release signal has an
internal pulse timer of 100 ms. When the DELTAREL signal has disappeared the delta logic is reset. In
order not to get too abrupt change, the reset is decayed in pre-defined steps.
The symmetrical component phase selector uses preprocessed calculated sequence voltages and
currents as inputs. It also uses sampled values of the phase currents. All the symmetrical quantities
mentioned further in this section are with reference to phase A.
This detection of ground fault is performed in two levels, first by evaluation of the magnitude of zero
sequence current, and secondly by the evaluation of the zero and negative sequence voltage. It is a
complement to the ground-fault signal built-in in the Symmetrical component based phase selector.
The complementary based zero-sequence current function evaluates the presence of ground fault by
calculating the 3I0 and comparing the result with the setting parameter INRelPE. The output signal
is used to release the ground-fault loop. It is a complement to the ground-fault signal built-in in the
sequence based phase selector. The condition for releasing the phase-to-ground loop is as follows:
The output from this detection is used to release the ground-fault loop.
|3I0|>maxIph × INRelPE
where:
|3I0| is the magnitude of the zero sequence current 3I0
maxIph is the maximum magnitude of the phase currents
INRelPE is a setting parameter for the relation between the magnitude of 3I0 and the
maximum phase current
The ground-fault loop is also released if the evaluation of the zero sequence current by the main
sequence function meets the following conditions:
|3I0|>IBase × 0.5
|3I0|>maxIph ×INRelPG
where:
maxIph is the maximal current magnitude found in any of the three phases
INRelPG is the setting of 3I0 limit for release of phase-to-ground measuring loop in % of IBase
IBase is the global setting of the base current (A)
In systems where the source impedance for zero sequence is high the change of zero sequence current
may not be significant and the above detection may fail. In those cases the detection enters the second
level, with evaluation of zero and negative sequence voltage. The release of the ground-fault loops can
then be achieved if all of the following conditions are fulfilled:
|3V0|>|V2| × 0.5
|3V0|>V1| × 0.2
and
3I0<0.1 × IBase
or
3I0<maxIph × INRelPG
where:
3V0 is the magnitude of the zero sequence voltage
V2 is the magnitude of the negative sequence voltage at the relay measuring point
k5 is design parameter
ILmax is the maximal phase current
IMinOp is the setting of minimum operate phase current in % of IBase
The detection of phase-to-phase fault is performed by evaluation of the angle difference between the
sequence voltages V2 and V1.
ANSI06000383-3-en.vsd
ANSI06000383 V3 EN-US
The phase-to-phase loop for the faulty phases will be determined if the angle between the sequence
voltages V2 and V1 lies within the sector defined according to figure 125 and the following conditions are
fulfilled:
|V1|>V1MinOP
|V2|>V2MinOp
where:
V1MinOP and V2MinOp are the setting parameters for positive sequence and negative sequence
minimum operate voltages
If there is a three-phase fault, there will not be any release of the individual phase signals, even if the
general conditions for V2 and V1 are fulfilled.
The detection of phase-to-ground and phase-to-phase-to-ground fault (US patent 5390067) is based on
two conditions:
The condition 1 determines faulty phase at single phase-to-ground fault by evaluating the angle between
V2 and I0.
80°
BG sector CG sector
V2A
(Ref)
200°
AG sector
320°
en06000384_ansi.vsd
ANSI06000384 V1 EN-US
Figure 126: Condition 1: Definition of faulty phase sector as angle between V2 and I0
The angle is calculated in a directional function block and gives the angle in radians as input to the V2
and I0 function block. The input angle is released only if the fault is in forward direction. This is done
by the directional element. The fault is classified as forward direction if the angle between V0 and I0 lies
between 20 to 200 degrees, see figure 127.
Forward 20°
200° Reverse
en06000385.vsd
IEC06000385 V1 EN-US
Figure 127: Directional element used to release the measured angle between Vo and I0
The input radians are summarized with an offset angle and the result evaluated. If the angle is within the
boundaries for a specific sector, the phase indication for that sector will be active see figure 126. Only
one sector signal is allowed to be activated at the same time.
The sector function for condition 1 has an internal release signal which is active if the main sequence
function has classified the angle between V0 and I0 as valid. The following conditions must be fulfilled for
activating the release signals:
|V2|>V2MinOp
|3I0|>maxIph · INRelPG
where:
V2 and IN are the magnitude of the negative sequence voltage and zero-
sequence current (3I0)
V2MinOp is the setting parameter for minimum operating negative sequence
voltage
maxIph is the maximum phase current
The angle difference is phase shifted by 180 degrees if the fault is in reverse direction.
The condition 2 looks at the angle relationship between the negative sequence voltage V2 and the
positive sequence voltage V1. Since this is a phase-to-phase voltage relationship, there is no need for
shifting phases if the fault is in reverse direction. A phase shift is introduced so that the fault sectors will
have the same angle boarders as for condition 1. If the calculated angle between V2 and V1 lies within
one sector, the corresponding phase for that sector will be activated. The condition 2 is released if both
the following conditions are fulfilled:
|V2|>V2MinOp
|V1|>V1MinOp
where:
|V1| and |V2| are the magnitude of the positive and negative sequence voltages.
V1MinOP and V2MinOP are the setting parameters for positive sequence and negative sequence
minimum operating voltages.
140°
CG sector
20°
V1A
(Ref)
AG sector
BG sector
260° en06000413_ansi.vsd
ANSI06000413 V1 EN-US
If both conditions are true and there is sector match, the fault is deemed as single phase-to-ground.
If the sectors, however, do not match the fault is determined to be the complement of the second
condition, that is, a phase-to-phase-to- ground fault.
The sequence phase selector is blocked when ground is not involved or if a three-phase fault is
detected.
Unless it has been categorized as a single or two-phase fault, the function classifies it as a three-phase
fault if the following conditions are fulfilled:
|V1|V1Level
and
|I1|>I1LowLevel
or
|I1|>IMaxLoad
where:
V1| and |I1| are the positive sequence voltage and current magnitude
V1Level , are the setting of limits for positive sequence voltage and current
I1LowLevel
IMaxLoad is the setting of the maximum load current
The output signal for detection of three-phase fault is only released if not ground fault and phase-to-
phase fault in the main sequence function is detected.
The conditions for not detecting ground fault are the inverse of equation 5 to 10.
The condition for not detecting phase-to-phase faults is determined by three conditions. Each of them
gives condition for not detecting phase-to-phase fault. Those are:
1:
ground fault is detected
or
|3I0|> 0.05 · IBase
and
|3I0|>maxIph ·INRelPG
2:
phase-to-ground and phase-to-phase faults are not fulfilled
and
maxIph<0.1 · IBase
and
|I2|<0.1 · maxIph
3:
|3I0|>maxIph · 3I0BLK_PP
or
|I2|<maxIph · I2ILmax
where:
maxIph is the maximum of the phase currents IA, IB and IC
INRelPG is the setting parameter for 3I0 limit for release of phase-to-ground fault loops
Table continues on next page
The phase selection logic has an evaluation procedure that can be simplified according to figure 129.
Only phase A is shown in the figure. If the internal signal 3 Phase fault is activated, all four outputs
PICKUP, PU_A, PU_B and PU_C gets activated.
a a>b FaultPriority
DeltaIA then c=a c Adaptive release
b else c=a dependent on result
from Delta logic
DeltaVA
Sequence based
function a<b
a
AB fault
then c=b c
OR b else c=a OR
AG fault
3 Phase fault
PU_A
IA Valid &
BLOCK
en06000386_ansi.vsd
ANSI06000386 V1 EN-US
Each of the six measuring loops has its own load (encroachment) characteristic based on the
corresponding loop impedance. The load encroachment functionality is always activated in faulty phase
identification with load encroachment for mho (FMPSPDIS, 21) function but the influence on the zone
measurement can be switched Enabled/Disabledin the respective impedance measuring function.
The outline of the characteristic is presented in figure 130. As illustrated, the resistive reach in forward
and reverse direction and the angle of the sector is the same in all four quadrants. The reach for the
phase selector will be reduced by the load encroachment function, as shown in figure 130.
Blinder
Blinder provides a mean to discriminate high load from a fault. The operating characteristic is illustrated
in figure 130. There are six individual measuring loops with the blinder functionality. Three phase-to-
ground loops which estimate the impedance according to
Zn = Vph / Iph
The start operations from respective loop are binary coded into one word and provides an output signal
PLECND.
X jX
RLd
LdAngle LdAngle
R
LdAngle LdAngle R
RLd
Operation area
en06000414_ansi.vsd
ANSI06000414 V1 EN-US
Outputs SEMOD153832-327 v7
The output of the sequence components based phase selector and the delta logic phase selector
activates the output signals PU_A, PU_B and PU_C. If a ground fault is detected the signal PHG_FLT
gets activated.
The phase selector also gives binary coded signals that are connected to the zone measuring element
for opening the correct measuring loop(s). This is done by the signal PHSCND. If only one phase is
started (A, B or C), the corresponding phase-to-ground element is enabled. PHG_FLT is expected to be
made available for two-phase and three-phase faults for the correct output to be selected. The fault loop
is indicated by one of the decimal numbers below.
The output PHSCND provides release information from the phase selection part only. DLECND provides
release information from the load encroachment part only. PLECND provides release information from
the phase selection part and the load encroachment part combined, that is, both parts have to issue
a release at the same time (this signal is normally not used in the zone measuring element). In these
signals, each fault type has an associated value, which represents the corresponding zone measuring
loop to be released. The values are presented in table 163.
0= no faulted phases
1= AG
2= BG
3= CG
4= -ABG
5= -BCG
6= -CAG
7= -ABCG
8= -AB
9= -BC
10= -CA
11= ABC
An additional logic is applied to handle the cases when phase-to-ground outputs are to be asserted
when the ground input G is not asserted.
The output signal PLECND is activated when the load encroachment is operating.
PLECNDis connected to the input STCND for selected quadrilateral impedance measuring zones to be
blocked. The signal must be connected to the input LDCND for selected mho impedance measuring
zones .
The load encroachment at the measuring zone must be activated to release the blocking
from the load encroachment function.
9.9.1 Identification
GUID-420DD49A-C65B-4F04-B317-9558DCCE7A52 v1
GUID-119120A5-8600-44C6-9C85-81136DBBE280 v1
The line distance protection is up to five zone full scheme protection with three fault loops for phase-to-
phase faults and three fault loops for phase-to-ground fault for each of the independent zones. Individual
settings for each zone in resistive and reactive reach gives flexibility for use as back-up protection for
transformer connected to overhead lines and cables of different types and lengths.
Distance protection zone, quadrilateral characteristic (ZMRPDIS (21)) together with Phase selection,
quadrilateral characteristic with settable angle (FRPSPDIS (21)) has functionality for load encroachment,
which increases the possibility to detect high resistive faults on heavily loaded lines, as shown in figure
131.
Forward
operation
Reverse
operation
en05000034.vsd
IEC05000034 V1 EN-US
Figure 131: Typical quadrilateral distance protection zone with Phase selection, quadrilateral characteristic with settable
angle function FRPSPDIS (21) activated
The independent measurement of impedance for each fault loop together with a sensitive and reliable
built-in phase selection makes the function suitable in applications with single pole tripping and
autoreclosing.
Built-in adaptive load compensation algorithm prevents overreaching of zone 1 at load exporting end at
phase-to-ground faults on heavily loaded power lines.
The distance protection zones can operate, independent of each other, in directional (forward or reverse)
or non-directional mode. This makes them suitable, together with different communication schemes,
for the protection of power lines and cables in complex network configurations, such as parallel lines,
multi-terminal lines and so on.
ZMRPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
BLKZ TR_C
BLKTR RI
PHSEL BFI_A
DIRCND BFI_B
PU_C
PHPUND
ANSI08000248-1-en.vsd
ANSI08000248 V1 EN-US
ZMRAPDIS (21)
I3P* TRIP
V3P* TR_A
BLOCK TR_B
BLKZ TR_C
BLKTR BFI
PHSEL PU_A
DIRCND BFI_B
PU_C
PHPUND
ANSI08000290_1_en.vsd
ANSI08000290 V1 EN-US
ZDRDI R (21D)
I3P* STDI RCND
V3P*
ANSI10000007-1-en.vsdx
ANSI10000007 V1 EN-US
9.9.4 Signals
PID-3649-INPUTSIGNALS v6
PID-3648-INPUTSIGNALS v6
9.9.5 Settings
PID-3649-SETTINGS v6
The execution of the different fault loops within the IED are of full scheme type, which means that
each fault loop for phase-to-ground faults and phase-to-phase faults for forward and reverse faults are
executed in parallel.
Figure 134 presents an outline of the different measuring loops for up to five, impedance-measuring
zones. There are 3 to 5 zones depending on product type and variant.
ANSI05000458‐3‐en‐us.vsdx
ANSI05000458 V3 EN-US
Figure 134: The different measuring loops at phase-to-ground fault and phase-to-phase fault.
The use of full scheme technique gives faster operation time compared to switched schemes which
mostly uses a pickup of an overreaching element to select correct voltages and current depending on
fault type. Each distance protection zone performs like one independent distance protection IED with six
measuring elements.
The distance measuring zone includes six impedance measuring loops; three intended for phase-to-
ground faults, and three intended for phase-to-phase as well as, three-phase faults.
The distance measuring zone will essentially operate according to the non-directional impedance
characteristics presented in figure 135 and figure 136. The phase-to-ground characteristic is illustrated
with the full loop reach while the phase-to-phase characteristic presents the per phase reach.
X (Ohm/loop)
X0-X1
Xn =
3
X1+Xn R0-R1
Rn =
3
jn jn
R (Ohm/loop)
RFPG RFPG
X1+Xn
ANSI05000661-3-en.vsd
ANSI05000661 V3 EN-US
X (Ohm/phase)
j j
R (Ohm/phase)
RFPP RFPP
2 2
X1PP
The fault loop reach with respect to each fault type may also be presented as in figure 137. Note in
particular the difference in definition regarding the (fault) resistive reach for phase-to-phase faults and
three-phase faults.
Ip R1 + j X1
Phase-to-ground
VA
element
Phase-to-ground
fault in phase A RFPG
(Arc + tower
resistance)
0
IN (R0-R1)/3 +
j (X0-X1)/3 )
IA R1 + j X1 Phase-to-phase
VA element A-B
Phase-to-phase
fault in phase A-B RFPP
IB
VB (Arc resistance)
R1 + j X1
IA R1 + j X1 0.5·RFPP Phase-to-phase
VA element A-C
Three-phase
fault
IC
VC
R1 + j X1 0.5·RFPP
ANSI05000181_2_en.vsd
ANSI05000181 V2 EN-US
The R1 and jX1 in figure 137 represents the positive sequence impedance from the measuring point to
the fault location. The settings RFPG and RFPP are the eventual fault resistances in the faulty place.
Regarding the illustration of three-phase fault in figure 137, there is of course fault current flowing also in
the third phase during a three-phase fault. The illustration merely reflects the loop measurement, which
is made phase-to-phase.
The zone can be set to operate in Non-directional, Forward or Reverse direction through the setting
OperationDir . The result from respective set value is illustrated in figure 138. The impedance reach is
symmetric, in the sense that it conforms for forward and reverse direction. Therefore, all reach settings
apply to both directions.
X X X
R R R
IEC05000182-2-en.vsdx
IEC05000182 V2 EN-US
The operation of Distance measuring zones, quadrilateral characteristic (ZMRPDIS, 21) is blocked if the
magnitude of input currents fall below certain threshold values.
The phase-to-ground loop AG (BG or CG) is blocked if IA (IB or IC) < IMinPUPG.
For zone 1 with load compensation feature the additional criterion applies, that all phase-to-ground loops
can be blocked when IN < IMinOpIR, regardless of the phase currents.
IA (IB or IC) is the RMS value of the current in phase IA (IB or IC). IN is the RMS value of the vector sum
of the three-phase currents, that is residual current 3I0.
The phase-to-phase loop AB (BC or CA) is blocked if I AB (BC or CA) < IMinPUPP.
All three current limits IMinPUPG, IMinOpIR and IMinPUPP are automatically reduced
to 75% of regular set values if the zone is set to operate in reverse direction, that is
OperationDir=Reverse
Fault loop equations use the complex values of voltage, current, and changes in the current. Apparent
impedances are calculated and compared with the set limits. The apparent impedances at phase-to-
phase faults follow equation 50 (example for a phase A to phase B fault).
VA - VB
Zapp =
IA - IB
EQUATION1545 V1 EN-US (Equation 50)
Here V and I represent the corresponding voltage and current phasors in the respective phase Ln (n = 1,
2, 3)
The ground return compensation applies in a conventional manner to phase-to-ground faults (example
for a phase A to ground fault) according to equation 51.
V_A
Z app =
I _ A + IN × KN
EQUATION1546 V1 EN-US (Equation 51)
Where:
V_A, I_A and IN are the phase voltage, phase current and residual current present to the IED
KN
is defined as:
Z 0 - Z1
KN =
3 × Z1
EQUATION-2105 V2 EN-US
Z 0 = R 0 + jX 0
EQUATION2106 V2 EN-US
Z 1 = R1 + jX 1
EQUATION2107 V2 EN-US
Where
R0 is setting of the resistive zero sequence reach
X0 is setting of the reactive zero sequence reach
R1 is setting of the resistive positive sequence reach
X1 is setting of the reactive positive sequence reach
Here IN is a phasor of the residual current in IED point. This results in the same reach along the line for
all types of faults.
The apparent impedance is considered as an impedance loop with resistance R and reactance X.
The formula given in equation 51 is only valid for radial feeder application without load. When load is
considered in the case of single phase-to-ground fault, conventional distance protection might overreach
at exporting end and underreach at importing end. The IED has an adaptive load compensation which
increases the security in such applications.
Measuring elements receive current and voltage information from the A/D converter. The check sums
are calculated and compared, and the information is distributed into memory locations. For each of the
six supervised fault loops, sampled values of voltage (V), current (I), and changes in current between
samples (DI) are brought from the input memory and fed to a recursive Fourier filter.
The filter provides two orthogonal values for each input. These values are related to the loop impedance
according to equation 52,
X Di
V =R× i + ×
w0 Dt
EQUATION1547 V1 EN-US (Equation 52)
X D Re (I )
Re (V ) = R × Re (I ) + ×
w0 Dt
EQUATION1548 V1 EN-US (Equation 53)
X D Im (I )
Im (V ) = R × Im (I ) + ×
w0 Dt
EQUATION1549 V1 EN-US (Equation 54)
with
w0 = 2 × p × f 0
EQUATION356 V1 EN-US (Equation 55)
where:
Re designates the real component of current and voltage,
Im designates the imaginary component of current and voltage and
f0 designates the rated system frequency
The algorithm calculates Rm measured resistance from the equation for the real value of the voltage and
substitutes it in the equation for the imaginary part. The equation for the Xm measured reactance can
then be solved. The final result is equal to:
The calculated Rm and Xm values are updated each sample and compared with the set zone reach. The
adaptive tripping counter counts the number of permissive tripping results. This effectively removes any
influence of errors introduced by the capacitive voltage transformers or by other factors.
The directional evaluations are performed simultaneously in both forward and reverse directions, and in
all six fault loops. Positive sequence voltage and a phase locked positive sequence memory voltage are
used as a reference. This ensures unlimited directional sensitivity for faults close to the IED point.
The evaluation of the directionality takes place in Directional impedance quadrilateral function ZDRDIR
(21D). Equation 58 and equation 59 are used to classify that the fault is in forward direction for phase-to-
ground fault and phase-to-phase fault.
where:
AngDir is the setting for the lower boundary of the forward directional characteristic, by default set to 15 (= -15
degrees) and
AngNegRes is the setting for the upper boundary of the forward directional characteristic, by default set to 115 degrees,
see figure 139.
V1 A is positive sequence phase voltage in phase A
V1 AM is positive sequence memorized phase voltage in phase A
IA is phase current in phase A
V1 AB is voltage difference between phase A and B (B lagging A)
V1 ABM is memorized voltage difference between phase A and B (B lagging A)
IAB is current difference between phase A and B (B lagging A)
The setting of AngDir and AngNegRes is by default set to 15 (= -15) and 115 degrees respectively (as
shown in figure 139). It should not be changed unless system studies have shown the necessity.
ZDRDIR gives binary coded directional information per measuring loop on the output STDIRCND.
STDIR= FWD_A*1+FWD_B*2+FWD_C*4+FWD_AB*8+
+FWD_BC*16+FWD_CA*32+REV_A*64+REV_B*128+REV_C*256+
+REV_AB*512+REV_BC*1024+REV_CA*2048
AngNegRes
AngDir
R
en05000722_ansi.vsd
ANSI05000722 V1 EN-US
Figure 139: Setting angles for discrimination of forward and reverse fault in Directional impedance quadrilateral function
ZDRDIR (21D)
The reverse directional characteristic is equal to the forward characteristic rotated by 180 degrees.
The polarizing voltage is available as long as the positive sequence voltage exceeds 5% of the set base
voltage VBase. So the directional element can use it for all unsymmetrical faults including close-in faults.
For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence
voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is restored.
• If the current is still above the set value of the minimum operating current (between 10 and 30% of the
set IED rated current IBase), the condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element in the reverse direction
remains in operation.
• If the current decreases below the minimum operating value, the memory resets until the positive
sequence voltage exceeds 10% of its rated value.
The design of the distance protection zones are presented for all measuring loops: phase-to-ground as
well as phase-to-phase.
Phase-to-ground related signals are designated by AG, BG and CG.. The phase-to-phase signals are
designated by AB, BC and CA.
Fulfillment of two different measuring conditions is necessary to obtain the one logical signal for each
separate measuring loop:
• Zone measuring condition, which follows the operating equations described above.
• Group functional input signal (PHSEL), as presented in figure 56.
The PHSEL input signal represents a connection of six different integer values from Phase selection
with load encroachment, quadrilateral characteristic function FRPSPDIS (21) within the IED, which are
converted within the zone measuring function into corresponding boolean expressions for each condition
separately. Input signal PHSEL is connected to FRPSPDIS (21) function output STCNDZ.
The input signal DIRCND is used to give condition for directionality for the distance measuring
zones. The signal contains binary coded information for both forward and reverse direction. The
zone measurement function filter out the relevant signals depending on the setting of the parameter
OperationDir. It must be configured to the STDIRCND output on directional function ZDRDIR (21D)
function.
PUZMPP
OR
PHSEL
AND NDIR_AB
AB
NDIR_BC
BC AND
CA AND NDIR_CA
AND NDIR_A
AG
AND NDIR_B
BG
NDIR_C
CG AND
OR STNDPE
OR
LOVBZ PHPUND
OR AND
BLOCK
BLK
BLOCFUNC
ANSI99000557-1-en.vsd
ANSI99000557 V2 EN-US
Figure 140: Conditioning by a group functional input signal PHSEL, external start condition
Composition of the phase pickup signals for a case, when the zone operates in a non-directional mode,
is presented in figure 57.
NDIR_A
OR
NDIR_B
PU_A
AND 0
NIDR_C 15ms
NDIR_AB OR PU_B
AND 0
15ms
NDIR_BC
PU_C
NDIR_CA AND 0
OR 15ms
PICKUP
AND 0
OR 15ms
BLK
ANSI09000889-1-en.vsd
ANSI09000889 V1 EN-US
Results of the directional measurement enter the logic circuits, when the zone operates in directional
(forward or reverse) mode, as shown in figure 58.
NDIR_A
DIR_A AND
PU_ZMPG
OR
NDIR_B
DIR_B AND
NDIR_C OR PU_A
AND 0
DIR_C AND 15 ms
NDIR_AB
DIR_AB AND OR PU_B
AND 0
15 ms
NDIR_BC
DIR_BC AND
OR PU_C
NDIR_CA AND 0
AND 15 ms
DIR_CA
PU_ZMPP
OR
BLK
OR PICKUP
AND 0
15 ms
ANSI09000888-2-en.vsd
ANSI09000888 V2 EN-US
Tripping conditions for the distance protection zone one are symbolically presented in figure 59.
Timer tPP=enable
PUZMPP AND tPP
0-tPP AND
0
BLOCFUNC
OR OR
tPG
0-tPG
0 AND
Timer tPG=enable AND
PUZMPG
BLKTR AND 0 TRIP
15 ms
BLK OR
ANSI09000887-3-en.vsdx
ANSI09000887 V3 EN-US
9.10.1 Identification
GUID-07DB9506-656C-4E5F-A043-3DAA624313C7 v2
SYMBOL-DD V1 EN-US
The ability to accurately and reliably classify the different types of fault, so that single pole tripping
and autoreclosing can be used plays an important role in today's power systems. Phase selection,
quadrilateral characteristic with settable angle FRPSPDIS (21) is designed to accurately select the
proper fault loop in the distance function dependent on the fault type.
The heavy load transfer that is common in many transmission networks may make fault resistance
coverage difficult to achieve. Therefore, FRPSPDIS (21) has a built-in algorithm for load encroachment,
which gives the possibility to enlarge the resistive setting of both the phase selection and the measuring
zones without interfering with the load.
The extensive output signals from the phase selection gives also important information about faulty
phase(s) which can be used for fault analysis.
A current-based phase selection is also included. The measuring elements continuously measure three
phase currents and the residual current and, compare them with the set values.
FRPSPDIS (21)
I3P* TRIP
V3P* BFI
BLOCK FWD_A
DIRCND FWD_B
FWD_C
FWD_G
REV_A
REV_B
REV_C
REV_G
NDIR_A
NDIR_B
NDIR_C
NDIR_G
FWD_1PH
FWD_2PH
FWD_3PH
PHG_FLT
PHPH_FLT
PHSELZ
DLECND
ANSI08000430-2-en.vsd
ANSI08000430 V2 EN-US
9.10.4 Signals
PID-3643-INPUTSIGNALS v7
9.10.5 Settings
PID-3643-SETTINGS v7
The basic impedance algorithm for the operation of the phase selection measuring elements is the same
as for the distance zone measuring function. Phase selection, quadrilateral characteristic with settable
angle (FRPSPDIS, 21) includes six impedance measuring loops; three intended for phase-to-ground
faults, and three intended for phase-to-phase as well as for three-phase faults.
The difference, compared to the distance zone measuring function, is in the combination of the
measuring quantities (currents and voltages) for different types of faults.
The characteristic is basically non-directional, but FRPSPDIS (21) uses information from the directional
function ZDRDIR to discriminate whether the fault is in forward or reverse direction.
• Residual current criteria, that is, separation of faults with and without ground connection
• Regular quadrilateral impedance characteristic
• Load encroachment characteristics is always active but can be switched off by selecting a high setting.
The PHSELI output is non-directional. The directionality is determined by the distance zones directional
function ZDRDIR.
There are output from FRPSPDIS (21) that indicate whether a pickup is in forward or reverse direction or
non-directional, for example FWD_A, REV_A and NDIR_A.
These directional indications are based on the sector boundaries of the directional function and
the impedance setting of FRPSPDIS (21) function. Their operating characteristics are illustrated in
figure 145.
X X X
60°
60° R
R R
60° 60°
en05000668_ansi.vsd
ANSI05000668 V1 EN-US
Figure 145: Characteristics for non-directional, forward and reverse operation of Phase selection, quadrilateral characteristic
with settable angle (FRPSPDIS, 21)
The setting of the load encroachment function may influence the total operating characteristic, for more
information, refer to section "Load encroachment".
The input DIRCND contains binary coded information about the directional coming from the directional
function ZDRDIR (21D). It shall be connected to the STDIR output on ZDRDIR (21D). This information is
also transferred to the input DIRCND on the distance measuring zones, that is, the ZMRPDIS (21) block.
STDIR= FWD_A*1+FWD_B*4+FWD_C*16+FWD_AB*64+
+FWD_BC*256+FWD_CA*1024+REV_A*2+REV_B*8+REV_C*32+
+REV_AB*128+REV_BC*512+REV_CA*2048
If the binary information is 1 then it will be considered that we have pickup in forward direction in phase
A. If the binary code is 3 then we have pickup in forward direction in phase A and B etc.
The or PHSEL output contains, in a similar way as DIRCND, binary coded information, in this case
information about the condition for opening correct fault loop in the distance measuring element. It shall
be connected to the PHSEL input on the ZMRPDIS distance measuring zones (21) block.
The code built up for release of the measuring fault loops is as follows:
PHSEL = AG*1+BG*2+CG*4+AB*8+BC*16+CA*32
Index PHS in images and equations reference settings for Phase selection, quadrilateral
characteristic with settable angle (FRPSPDIS, 21).
VA( B , C )
ZPHSn =
IA( B , C )
EQUATION1554 V1 EN-US (Equation 60)
where:
n corresponds to the particular phase (n=1, 2 or 3)
The characteristic for FRPSPDIS (21) function at phase-to-ground fault is according to figure 146. The
characteristic has a settable angle for the resistive boundary in the first quadrant of 70°.
The resistance RN and reactance XN are the impedance in the ground-return path defined according to
equation 63 and equation 64.
R 0 PE - R1PE
RN =
3
EQUATION-2125 V1 EN-US (Equation 61)
R0 - R1
RN =
3
EQUATION1256 V1 EN-US (Equation 61)
X 0 - X1
XN =
3
EQUATION1257 V1 EN-US (Equation 62)
X (ohm/loop)
R1PE+RN
RFRvPE RFFwPE
X1+XN
RFFwPE
RFRvPE R (Ohm/loop)
X1+XN
RFRvPE RFFwPE
R1PE+RN
IEC09000633-1-en.vsd
IEC09000633 V1 EN-US
Figure 146: Characteristic of FRPSPDIS (21) for phase to fault (directional lines are drawn as "line-dot-dot-line")
Besides this, the 3I0 residual current must fulfil the conditions according to equation 63 and equation 64.
3 × I0 ³ 0.5 × IMinOpPE
EQUATION2108 V1 EN-US (Equation 63)
3I 0 Enable _ PG
3 × I0 ³ × Iph max
100
EQUATION1812-ANSI V1 EN-US (Equation 64)
where:
IMinOpPE is the minimum operation current for forward zones
3I0Enable_PG is the setting for the minimum residual current needed to enable operation in the phase-to-ground fault
loops (in %).
Iphmax is the maximum phase current in any of three phases.
For a phase-to-phase fault, the measured impedance by FRPSPDIS (21) is according to equation 65.
Vm - Vn
ZPHS =
-2 × In
EQUATION1813-ANSI V1 EN-US (Equation 65)
Vm is the leading phase voltage, Vn the lagging phase voltage and In the phase current in the lagging
phase n.
X (ohm/phase)
0.5·FRvPP
R1PP 0.5·RFFwPP
X1
0.5·RFFwPP
R (ohm/phase)
0.5·RFRvPP
X1
R1PP
0.5·RFRvPP 0.5·RFFwPP
IEC09000634-1-en.vsd
IEC09000634 V1 EN-US
Figure 147: The operation characteristic for FRPSPDIS (21) at phase-to-phase fault (directional lines are drawn as "line-dot-
dot-line")
In the same way as the condition for phase-to-ground fault, there are current conditions that have to be
fulfilled in order to release the phase-to-phase loop. Those are according to equation 66 or equation 67.
3I 0 < 3I 0Enable _ PG
EQUATION1814-ANSI V1 EN-US (Equation 66)
3I 0 < 3I 0BLK _ PP
EQUATION1815-ANSI V1 EN-US (Equation 67)
where:
3I0Enable_PG is the minimum operation current for forward ground measuring loops,
3I0BLK_PP is 3I0 limit for blocking phase-to-phase measuring loop and
Iphmax is maximal magnitude of the phase currents.
The operation conditions for three-phase faults are the same as for phase-to-phase fault, that is
equation 65, equation 66 and equation 67 are used to release the operation of the function.
However, the reach is expanded by a factor 2/√3 (approximately 1.1547) in all directions. At the
same time the characteristic is rotated 30 degrees, counter-clockwise. The characteristic is shown in
figure 148.
X (ohm/phase)
4 × X1PP
3
0.5·RFFwPP·K3
X1·K3 30 deg 2
RFwPP ×
3
R (ohm/phase)
0.5·RFRvPP·K3
K3 = 2 / sqrt(3)
30 deg
IEC09000635-1-en.vsd
IEC09000635 V2 EN-US
Figure 148: The characteristic of FRPSPDIS (21) for three-phase fault (set angle 70°)
Each of the six measuring loops has its own load encroachment characteristic based on the
corresponding loop impedance. The load encroachment functionality is always active, but can be
switched off by selecting a high setting.
The outline of the characteristic is presented in figure 150. As illustrated, the resistive blinders are
set individually in forward and reverse direction while the angle of the sector is the same in all four
quadrants.
RLdFwd
LdAngle LdAngle
R
LdAngle LdAngle
RLdRev
en05000196_ansi.vsd
ANSI05000196 V1 EN-US
The influence of load encroachment function on the operation characteristic is dependent on the chosen
operation mode of FRPSPDIS (21) function. When output signal PHSELZ is selected, the characteristic
for FRPSPDIS (21) (and also zone measurement depending on settings) will be reduced by the load
encroachment characteristic, see figure 151.
When output signal PHSELI is selected, the operation characteristic will be as in figure 150. The reach
will in this case be limit by the minimum operation current and the distance measuring zones.
X X
R R
PHSELZ DLECND
ANSI10000099-1-en.vsd
ANSI10000099 V1 EN-US
Figure 150: Difference in operating characteristic depending on operation mode when load encroachment is activated
When FRPSPDIS (21) is set to operate together with a distance measuring zone the resultant operate
characteristic could look like in figure 151. The figure shows a distance measuring zone operating
in forward direction. Thus, the operating area of the zone together with the load encroachment is
highlighted in black.
"Phase selection"
"quadrilateral" zone
Load encroachment
characteristic
Directional line
en05000673.vsd
IEC05000673 V1 EN-US
Figure 151: Operating characteristic in forward direction when load encroachment is activated
Figure 151 is valid for phase-to-ground. During a three-phase fault, or load, when the quadrilateral
phase-to-phase characteristic is subject to enlargement and rotation the operate area is transformed
according to figure 152. Notice in particular what happens with the resistive blinders of the "phase
selection" "quadrilateral" zone. Due to the 30-degree rotation, the angle of the blinder in quadrant one
is now 100 degrees instead of the original 70 degrees (if the angle setting is 70 degrees). The blinder
that is nominally located to quadrant four will at the same time tilt outwards and increase the resistive
reach around the R-axis. Consequently, it will be more or less necessary to use the load encroachment
characteristic in order to secure a margin to the load impedance.
X (W / phase)
Phase selection
”Quadrilateral” zone
R (W / phase)
IEC09000049-1-en.vsd
IEC09000049 V1 EN-US
Figure 152: Operating characteristic for FRPSPDIS (21) in forward direction for three-phase fault, ohm/phase domain
The result from rotation of the load characteristic at a fault between two phases is presented in fig 153.
Since the load characteristic is based on the same measurement as the quadrilateral characteristic, it
will rotate with the quadrilateral characteristic clockwise by 30 degrees when subject to a pure phase-to-
phase fault. At the same time the characteristic will "shrink" by 2/√3, from the full RLdFw and RLdRv
reach, which is valid at load or three-phase fault.
IEC08000437.vsd
IEC08000437 V1 EN-US
Figure 153: Rotation of load characteristic for a fault between two phases
There is a gain in selectivity by using the same measurement as for the quadrilateral characteristic since
not all phase-to-phase loops will be fully affected by a fault between two phases. It should also provide
better fault resistive coverage in quadrant one. The relative loss of fault resistive coverage in quadrant
four should not be a problem even for applications on series compensated lines.
The operation of Phase selection, quadrilateral characteristic with settable angle (FRPSPDIS, 21) is
blocked if the magnitude of input currents falls below certain threshold values.
The phase-to-ground loop n is blocked if In<IMinPUPG, where In is the RMS value of the current in
phase n (A or B or C).
Figure 154 presents schematically the creation of the phase-to-phase and phase-to-ground operating
conditions. Consider only the corresponding part of measuring and logic circuits, when only a phase-to-
ground or phase-to-phase measurement is available within the IED.
21 enable
AND
LDEblock
0 STPG
AND
3 I 0 Enable _ PG 15ms
3I 0 Iphmax
100 Bool to AND
DLECND
BLOCK integer
Figure 154: Phase-to-phase and phase-to-ground operating conditions (residual current criteria)
A special attention is paid to correct phase selection at evolving faults. A PHSEL output signal is created
as a combination of the load encroachment characteristic and current criteria, refer to figure 154. This
signal can be configured to STCND functional input signals of the distance protection zone and this way
influence the operation of the phase-to-phase and phase-to-ground zone measuring elements and their
phase related pickup and tripping signals.
Figure 155 presents schematically the composition of non-directional phase selective signals NDIR_A (B
or C). Internal signals ZMn and ZMmn (m and n change between A, B and C according to the phase)
represent the fulfilled operating criteria for each separate loop measuring element, that is within the
characteristic.
INDIR_A
INDIR_B
INDIR_C
0
PHSEL_G
OR
15 ms
IRELPG
LDEblockA
I_A AND
OR PHSEL_A
ZMA OR 0
LDEblockB 15 ms
I_B AND
OR
ZMB PHSEL_B
LDEblockC OR 0
I_C AND 15 ms
OR
ZMC
LDEblockAB PHSEL_C
I_A & I_B AND OR 0
OR 15 ms
ZMAB
LDEblockBC
I_B & I_C AND INDIR_AB
OR
ZMBC INDIR_BC
LDEblockCA
I_C & I_A AND
OR INDIR_CA
ZMCA
IRELPP
0 PHSEL_PP
OR
15 ms
ANSI00000545-5-en.vsd
ANSI00000545 V5 EN-US
Composition of the directional (forward and reverse) phase selective signals is presented schematically
in figure 156 and figure 157. The directional criteria appears as a condition for the correct phase
selection in order to secure a high phase selectivity for simultaneous and evolving faults on lines within
the complex network configurations. Internal signals DFWLn and DFWLnLm present the corresponding
directional signals for measuring loops with phases Ln and Lm. Designation FW (figure 157) represents
the forward direction as well as the designation RV (figure 156) represents the reverse direction. All
directional signals are derived within the corresponding digital signal processor.
Figure 156 presents additionally a composition of a PHSELZ output signal, which is created on the
basis of impedance measuring conditions. This signal can be configured to PHSEL functional input
signals of the distance protection zone and this way influence the operation of the phase-to-phase and
phase-to-ground zone measuring elements and their phase related pickup and tripping signals.
INDIR_A
AND
DRV_A
INDIR_AB
REV_A
AND OR 0
DRV_AB 15 ms
INDIR_CA
AND
DRV_CA
REV_G
OR 0
INDIR_B 15 ms
AND
DRV_B
INDIR_AB
REV_B
AND OR 0
15 ms
INDIR_BC INDIR_A
AND INDIR_B
DRV_BC
INDIR_C Bool to PHSELZ
INDIR_C INDIR_AB integer
AND INDIR_BC
DRV_C INDIR_CA
INDIR_BC
0
REV_C
AND OR
15 ms
INDIR_CA
AND REV_PP
OR 0
15 ms
ANSI00000546-3-en.vsd
ANSI00000546 V3 EN-US
AND
INDIR_A
AND FWD_IPH
DFW_A AND OR 15 ms 0
0 15 ms
INDIR_AB
0 FWD_A
AND OR
DFW_AB 15 ms
INDIR_CA
AND
AND
DFW_CA
0 FWD_G
INDIR_B OR
15 ms
AND
DFW_B
AND
INDIR_AB 0 FWD_B
AND OR 15 ms
INDIR_BC 15 ms 0 FWD_2PH
AND OR
AND 0 15 ms
DFW_BC
INDIR_C
AND AND
DFW_C FWD_C
0
INDIR_BC 15 ms
AND OR
INDIR_CA 0 FWD_3PH
AND
AND 15 ms
FWD_PP
OR 0
15 ms
ANSI05000201-3-en.vsd
ANSI05000201 V3 EN-US
Figure158 presents the composition of output signals TRIP and START, where internal signals STNDPP,
STFWPP and STRVPP are the equivalent to internal signals STNDPE, STFWPE and STRVPE, but for
the phase-to-phase loops.
TimerPP=Disabled
tPP
AND AND
t
TRIP
OR OR
tPE
TimerPE=Disabled
t
AND AND
STNDPP
STFWPP OR
STRVPP
RI
OR
STNDPE
STFWPE OR
STRVPE
ANSI08000441 1-1-en.vsd
ANSI08000441-1 V1 EN-US
Z
S00346 V2 EN-US
The ZMFPDIS function is a seven zone full scheme protection with three fault loops for phase-to-phase
faults and three fault loops for phase-to-ground faults for each of the independent zones, which makes
the function suitable for applications with single-phase autoreclosing.
In each measurement zone, ZMFPDIS function is designed with the flexibility to operate in either
quadrilateral or mho characteristic mode for separate phase-to-earth or phase-to-phase loops.
A built-in adaptive load compensation algorithm prevents overreaching of the distance zones in the load
exporting end during phase-to-ground faults on heavily loaded power lines. It also reduces underreach in
the importing end.
The ZMFPDIS function block itself incorporates a phase-selection element and a directional element,
contrary to previous designs in the 600-series, where these elements were represented with separate
function-blocks.
The operation of the phase-selection element is primarily based on current change criteria (i.e. delta
quantities), with significantly increased dependability. There is also a phase selection criterion operating
in parallel which bases its operation only on voltage and current phasors.
The directional element utilizes a set of well-established quantities to provide fast and correct directional
decision during various power system operating conditions, including close-in three-phase faults,
simultaneous faults and faults with only zero-sequence in-feed.
The ZMFPDIS function is also equipped with the parallel line mutual coupling compensation feature
based on the parallel line residual current.
ZMFPDIS (21)
I3P* TRIP
V3P* TRZ1
INP TR_A_Z1
BLOCK TR_B_Z1
LOVBZ TR_C_Z1
BLKZ1 TRZ2
BLKZ2 TR_A_Z2
BLKZ3 TR_B_Z2
BLKZ4 TR_C_Z2
BLKZ5 TRZ3
BLKZRV TRZ4
BLKZBU TRZ5
BLKTRZ1 TRZRV
BLKTRZ2 TRZBU
BLKTRZ3 BFI_3P
BLKTRZ4 PU_Z1
BLKTRZ5 PU_ND_Z1
BLKTRZRV PU_Z2
BLKTRZBU PU_A_Z2
EXTN_PU PU_B_Z2
ORCND PU_C_Z2
RELCNDZ1 PU_ND_Z2
RELCNDZ2 PU_Z3
RELCNDZ3 PU_ND_Z3
RELCNDZ4 PU_Z4
RELCNDZ5 PU_ND_Z4
RELCNDZRV PU_Z5
RELCNDZBU PU_ND_Z5
PU_ZRV
PU_A_RV
PU_B_RV
PU_C_RV
PU_ND_RV
PUZBU
PUNDZBU
PHPUN D
NDIR_A
NDIR_B
NDIR_C
NDIR_G
FWD_A
FWD_B
FWD_C
FWD_G
REV_A
REV_B
REV_C
REV_G
FWD_1PH
FWD_2PH
FWD_3PH
PHG_FLT
PHPH_FLT
ANSI1 1000433-5-en.vsdx
ANSI11000433 V6 EN-US
9.11.5 Signals
PID-8227-INPUTSIGNALS v1
9.11.6 Settings
GUID-9E081C6B-4E31-4ED5-A4F9-9E4A80749741 v1
Settings, input and output names are sometimes mentioned in the following text without its
zone suffix (i.e. BLKZx instead of BLKZ3) when the description is equally valid for all zones.
Practically all voltage, current and impedance quantities used within the ZMFPDIS function are derived
from fundamental frequency phasors filtered by a half cycle filter.
The phasor filter is frequency adaptive in the sense that its coefficients are changed based on the
estimated power system frequency.
A half cycle filter will not be able to reject both even and odd harmonics. So, while odd harmonics will be
completely attenuated, accuracy will be affected by even harmonics. Even harmonics will not cause the
distance zones to overreach however; instead there will be a slightly variable underreach, on average in
the same order as the magnitude ratio between the harmonic and fundamental component.
The execution of the different fault loops within the IED are of full scheme type, which means that
ground fault loop for phase-to-ground faults and phase-to-phase faults for forward and reverse faults are
executed in parallel.
Figure 160 presents an outline of the different measuring loops for the seven distance zones.
ANSI05000458‐3‐en‐us.vsdx
ANSI05000458 V3 EN-US
Figure 160: The different measuring loops at phase-to-ground fault and phase-to-phase fault
Each distance protection zone performs like one independent distance protection function with seven
measuring elements.
Transients from CVTs may have a significant impact on the transient overreach of a distance protection.
At the same time these transients can be very diverse in nature from one type to the other; in fact,
more diverse than can be distinguished by the algorithm itself in the course of a few milliseconds. So,
a setting (CVTtype) is introduced in order to inform the algorithm about the type of CVT applied and
thus providing the advantage of knowing how performance should be optimized, even during the first
turbulent milliseconds of the fault period.
There are two types of CVTs from the function point of view, the passive and the active type, which
refers to the type of ferro-resonance suppression device that is employed. The active type requires
more rigorous filtering which will have a negative impact on operate times. However, this will be evident
primarily at higher source impedance ratios (SIRs), SIR 5 and above, or close to the reach limit.
The IEC 60044-5 transient classification is of little or no use in relation to this. It is not primarily the
damping of transients that is important; it is the frequency content of the transients that is decisive, i.e.
how difficult it is to filter out the specific frequency. So, even if two CVTs, one passive and the other
active type, comply with the same transient class, the active type requires more extensive filtering in
order to avoid transient overreach.
To avoid overreach and at the same time achieve fast operate times, a supplementary circular
characteristic is implemented. A circular characteristic exists for every measuring loop and
quadrilateral/mho characteristic. There are no specific reach settings for this circular zone. It uses the
normal quadrilateral/mho zone settings to determine a reach that will be appropriate. This implies that
the circular characteristic will always have somewhat shorter reach than the quadrilateral/mho zone.
The operation of the phase-selection element is primarily based on current change criteria (i.e. delta
quantities) with significantly increased dependability. To handle this, there is also a phase selection
criterion operating in parallel which bases its operation only on voltage sequence component phasors.
This continuous criteria will, in the vast majority of cases, operate in parallel and carry on the fault
indication after the current change phase has ended. Only in some particularly difficult faults on heavily
loaded lines, the continuous criteria might not be sufficient, for example, when the estimated fault
impedance resides within the load area defined by the load encroachment characteristic. In this case,
the indication will be restricted to a pulse lasting for one or two power system cycles.
The phase-selection element can, owing to the current change criteria, distinguish faults with minimum
influence from load and fault impedance. In other words, it is not restricted by a load encroachment
characteristic during the current change phase. This significantly improves performance for remote
phase-to-ground faults on heavily loaded lines. One exception, however, are three-phase faults to which
the load encroachment characteristic always has to be applied in order to distinguish fault from load.
Phase-to-phase-ground faults (also called double ground faults) will practically always activate phase-to-
phase zone measurements. Measurement in two phase-to-ground loops at the same time is associated
with so-called simultaneous faults: two ground faults at the same time, one each on the two circuits of a
double line, or when the zero sequence current is relatively high due to a source with low Z0/Z1 ratio. In
these situations zone measurement will be released both for the related phase-to-ground loops and the
phase-to-phase loop simultaneously. On the other hand, simultaneous faults closer to the remote bus
will gradually take on the properties of a phase-to-phase-ground fault and the function will eventually use
phase-to-phase zone measurements also here.
In cases where the fault current infeed is more or less completely of zero sequence nature (all phase
currents in phase), the measurement will be performed in the phase-to-ground loops only for a phase-to-
phase-ground fault.
AND
2-phase Fault
I3P detected by
Impedance/ current
2-phase fault
V3P PHSLy
based Phase AND
selection
PHSLxLy
AND
a
b
a>b
250%
OR
a
b a>b
50% AND OR
a
b
a<b
INMag
IAMag IN / Imax
IBMag
MAX
ICMag a ForcePE
b
a<b
INReleasePE
ANSI17000230-1-en.vsdx
ANSI17000230 V1 EN-US
Figure 161 explains the release of two-phase faults (including simultaneous faults as well as
cross-country faults for high impedance grounded networks. This is not valid for single-phase
faults.
However, should it be desirable to use phase-to-ground (and only phase-to-ground) zone measurement
for phase-to-phase-ground faults, there is a setting 3I0Enable_PG that can be lowered from its
excessive default value to the level above which phase-to-ground measurement should be activated.
Several criteria are employed when making the directional decision. The basis is provided by comparing
a positive sequence based polarizing voltage with phase currents. For extra security, especially in
making a very fast decision, this method is complemented with an equivalent comparison where, instead
of the phase current, the change in phase current is used. Moreover, a basic negative sequence
directional evaluation is taken into account as a reliable reference during high load condition. Finally, a
zero sequence directional evaluation is used whenever there is more or less exclusive zero sequence
in-feed.
The directional sectors that represent forward direction, one per measuring loop, are defined by the
following equations.
VPolA
ArgDir <arg ArgNegRes
IA
VPolAB
ArgDir <arg ArgNegRes
I AB
Where:
VPolA is the polarizing voltage for phase A.
IA is the phase current in phase A.
VPolAB is the polarizing voltage difference between phase A and B (B lagging A).
IAB is the current difference between phase A and B (B lagging A).
The corresponding reverse directional sectors range from (-ArgDir+180) to (ArgNegRes-180) degrees.
Since the polarizing voltage is also used for the Mho distance characteristics, the magnitude of the
voltage is just as interesting as the phase. If there are symmetrical conditions and the measured per
phase positive sequence voltage magnitude is above 75% of the base voltage before the fault, the
pre-fault magnitude will be memorized and used as long as there is a fault. The phase angle however
will only be memorized (locked) for 75 ms at a time, not to lose synchronism with the real system
voltage.
Should the positive sequence voltage drop below 2% of the base voltage, it will be considered invalid. In
this situation, directional signals and pickups from Mho elements will be sealed-in and kept static as long
as there is a fault.
For ZMFCPDIS, when option SeriesComp is chosen for OperationSC, the voltages of faulty phases will
be discarded in order not to affect the polarizing voltage with voltage reversal.
The ZMFPDIS function has to be blocked by an additional function like the Fuse failure supervision
(FUFSPVC) or an equivalent external device. Typically, the binary input VTSZ is used for this purpose.
A built-in supervision feature within high-speed distance protection itself, based on phase current
change, will ensure that the FUFSPVC blocking signal is received in time. Namely, an intentional time
delay will be introduced if no current magnitude change greater than 5% of IBase has been detected for
any of the three phase currents.
ZMFPDIS implements quadrilateral and mho characteristic in all the seven zones separately. Set
OpModePEZx or OpModePPZx to Quadrilateral, to choose particular measuring loop in a zone to work
as quadrilateral distance protection.
All ZMFPDIS zones operate according to the non-directional impedance characteristics presented in
figure 163 and figure 162. The phase-to-ground characteristic is given in ohms-per-loop domain while
the phase-to-phase characteristic is given in ohms-per-phase domain.
The voltage and current phasors after the half-cycle filter are used in fault loop equations.
For phase-to-phase faults (Figure 164, lower part), the calculated impedances from the relay to the fault
Z calc Rcalc j X calc follow Equation 70 (example is given for a phase L1 to phase L2 fault).
U L1 U L 2 I L1 I L 2 Z calc
IECEQUATION18003 V1 EN-US (Equation 70)
Where and represents the corresponding voltage and current phasors in the respective phase Ln
(n = 1, 2, 3).
The calculated Rcalc and Xcalc are compared with the non-directional phase-to-phase quadrilateral
characteristics. If is inside the non-directional phase-to-phase characteristic, the STNDZx output
is set to TRUE.
For phase-to-ground faults (Figure 164, upper part), the ground return compensation applies according
to Equation 71 (example for a phase L1 to ground fault).
U L1 I L1 K N 3I 0 p Z1 I F RF
IECEQUATION18007 V1 EN-US (Equation 71)
Where,
p is the fault location and RF is the calculated fault resistance. p and RF are unknown and needs to be
solved.
Z 0 Z1
KN
3 Z1
Z 0 R 0 Zx j X 0 Zx
Z1 R1Zx j X 1Zx
IECEQUATION18010 V1 EN-US
Where,
is the positive sequence reactance reach of the line in Ω/phase for phase-to-ground fault for zone
x (x = 1 to 5, BU or RV).
is the positive sequence resistive reach of the line in Ω/phase for phase-to-ground fault for zone x
(x = 1 to 5, BU or RV).
is the zero-sequence reactance reach of the line in Ω/phase for zone x (x = 1 to 5, BU or RV).
is the zero-sequence resistive reach of the line in Ω/phase for zone x (x = 1 to 5, BU or RV).
Table 190: Settings of positive and zero-sequence impedances for different zones
is the fault current. It is chosen among phase, zero or negative sequence currents automatically
by the built-in adaptive load compensation algorithm. If the system behind the relay cannot contribute
enough zero-sequence current, only phase or negative sequence current will be chosen.
The calculated impedances from the relay to the fault Z calc Rcalc j X calc can be represented as:
X calc p X 1Zx
IECEQUATION18017 V1 EN-US
Rcalc p R1Zx RF
IECEQUATION18018 V1 EN-US
When the two unknowns p and RF are solved from the equation 71 then the calculated Rcalc and Xcalc
values are compared with the non-directional phase-to-ground quadrilateral characteristics. If is
inside the non-directional phase-to-ground characteristic and the phase selection algorithm enables this
loop, the STNDZx output is set to TRUE.
The load compensation for zone 1 is achieved by estimating the impedance with three different values of
the IF current with:
• neutral current
• negative sequence current
• phase current.
Impedance estimation is based on the neutral current or negative sequence current essentially that
excludes the current component that causes the over-reach. The reactance values from all the
calculations shall effectively be within the zone reactive boundary in order to get the non-directional
start signal from the zone. This means that the under-reach, that is caused by the load import, is not
compensated.
For the other zones, it is enough in effect if the median value of the three is within the zone reach. If
the neutral current is not sufficient, then the negative sequence current based reactance will represent
the median value. If the negative sequence current is not sufficient, then the other reactance has to be
within the reach.
Zone 1 has individual positive sequence impedance settings for phase-to-phase and phase-to-earth
(X1PPZ1, R1PPZ1 and X1PEZ1, R1PEZ1). For the other zones, the positive sequence impedance
reach is common for phase-to-phase and phase-to-earth (X1Zx, R1Zx).
X (Ohm/phase)
X1Zx
R (Ohm/phase)
RFPPZx RFPPZx
2 2
X1Zx
X (Ohm/loop)
ϕN ϕN
(Ohm/loop)
ANSI11000415-1-en.vsd
ANSI11000415 V1 EN-US
The faulty loop in relation to the fault type can be presented as in figure 164. The main intention with this
illustration is to make clear how the fault resistive reach should be interpreted and set. Note in particular
that the setting RFPPZx always represents the total fault resistance of the loop, regardless the fact that
the fault resistance (arc) may be divided into parts like for three-phase or phase-to-phase faults. The
R1Zx + jX1Zx represent the positive sequence impedance from the measuring point to the fault location.
IA R1 + j X1
Phase-to-ground
VA
element
Phase-to-ground
RFPG
fault in phase A
(Arc + tower
resistance)
N
IG (R0-R1)/3 +
j (X0-X1)/3 )
IA R1 + j X1 Phase-to-phase
VA element A-B
Phase-to-phase
fault in phase RFPP
A-B IB
VB (Arc resistance)
R1 + j X1
IA R1 + j X1 0.5·RFPP Phase-to-phase
VA element A-C
Three-phase
fault or Phase-to-
phase-ground fault IC
VC
R1 + j X1 0.5·RFPP
ANSI11000419-3-en.vsd
ANSI11000419 V3 EN-US
The estimated impedance needs to be inside both characteristics for the zone to start or trip. (The
non-directional start STNDZx is an exception however. It is only dependent on the quadrilateral
characteristic.)
In the following figure, it is shown how the X1PP setting can influence the shape of the quadrilateral
characteristic in the fourth quadrant for short line applications.
X (ohm)
X1PP’
X1PP
15° R (ohm)
RFPP/2
-X1PP
R· tan15°
-X1PP’
Line distance protection=IEC19000141=2=en-us=Original.vsdx
IEC19000141 V2 EN-US
Figure 165: Influence of X1PP setting on the quadrilateral shape in the fourth quadrant
The quadrilateral phase-to-earth element is extended with the parallel line mutual coupling
compensation feature based on the parallel line residual current. The additional current signal must
be connected to the function through the INP group input. The parallel line residual current hardware
channel must be connected to the residual quantity input of the corresponding SMAI block. The
compensation feature can be switched On/Off with the EnPar setting.
When the parallel compensation is switched On (EnPar is On), the phase-to-ground loop Equation 71 is
modified according to Equation 72 (example is given for phase L1 to earth fault).
U L1 ( I L1 K N 3I 0 K Nm 3I 0 p ) p Z1 I F RF
IECEQUATION20296 V1 EN-US (Equation 72)
Z0m
K Nm =
3 Z1
IECEQUATION20299 V1 EN-US
Z 0 m = R0MZx + j X 0MZx
IECEQUATION20300 V1 EN-US
Where,
Z 0m is the set complex zero-sequence mutual impedance between parallel lines in Ω/phase.
is the zero-sequence resistance between parallel lines in Ω/phase for the phase-to-ground
fault in zone direction for zone x (where x = 1 to 2).
is the zero-sequence reactance between parallel lines in Ω/phase for the phase-to-ground fault
in zone direction for zone x (where x = 1 to 2).
The compensation feature will only be active when the parallel line residual current is not significantly
higher than the protected line residual current. The deactivation limit of this parallel line compensation
feature is set with the INPRatio setting. Compensation is deactivated when:
3I0p
INPRatio
3I0
IECEQUATION20302 V1 EN-US
The mutual compensation is also deactivated when the protected line residual current is less than 50%
of IMinOp according to the below relation:
3I 0 0.5 IMin0 p
IECEQUATION20303 V1 EN-US
ZMFPDIS implements quadrilateral and mho characteristic in all the seven zones separately. Set
OpModePEZx or OpModePPZx setting to Mho or Offset, to choose a particular measuring loop in a
zone to work as mho (or Offset Mho) distance protection.
Zones 2 to 5 and BU can be selected to be either forward or reverse with positive sequence polarized
mho characteristic; alternatively self polarized offset mho characteristics. The operating characteristic is
in accordance to figure 166 where zone 5 is selected offset mho.
X
ZBU X
Z4
Z3
ZS=0
Z2
Z1 R
Z5 R
ZS=Z1
ZRV
ZS=2Z1
IEC150000 56-2-en.vsdx
IEC15000056 V2 EN-US
Figure 166: Mho, offset mho characteristics and the source impedance influence on the mho characteristic
The mho characteristic has a dynamic expansion due to the source impedance. Instead of crossing
the origin, as for the mho to the left of figure 166, which is only valid where the source impedance
(Zs) is zero, the crossing point is moved to the coordinates of the negative source impedance given
an expansion of the circle shown to the right of figure 166. Z1 denotes the complex positive sequence
impedance.
The magnitude of the polarizing voltage is determined completely by the positive sequence voltage
magnitude from before the fault. This will give a somewhat less dynamic expansion of the mho circle
during faults. However, if the source impedance is high, the dynamic expansion of the mho circle might
lower the security of the function too much with high loading and mild power swing conditions.
In ZMFPDIS, each zone measurement loop characteristic can be set to mho characteristic or offset mho
characteristic by setting OpModePEZx or OpModePPZx (where x = 1 to 5, BU or RV depending on
selected zone).
ZMFPDIS fixes zone 1 in Forward mode and zone RV in Reverse mode. Zone 2 to 5 and BU can be
set to Non-directional, Forward or Reverse by setting the parameter DirModeZx (where x = 2 to 5 or BU
depending on selected zone).
X X X
(a) Rset (b) (c) Rset
Xset Xset
R R R
Xset
(a)-(f)
Rset For phase-to-phase fault
Rset = R1Zx
Forward Reverse Non-directional Xset = X1Zx
R R R
IEC15000055 V4 EN-US
For each zone, the impedance is set in cartesian coordinates (resistance and reactance) which is the
same as for quadrilateral characteristic.
The ZMFPDIS function has only one set of reach setting so the reverse will be the same as for
the forward reach, meaning that the non-directional offset mho characteristic will always be centered
around the origin. In detail, for Zone 1, the resistive and reactance reaches for phase-to-earth fault and
phase-to-phase fault are set individually using the settings R1PPZ1, X1PPZ1, R1PEZ1, X1PEZ1, X0Z1
and R0Z1. In Zone 2-5, BU and RV, the same zone reach settings are used for phase-to-earth fault and
phase-to-phase (R1Zx, X1Zx, X0Zx and R0Zx, x = 2 to 5, BU or RV).
The mho algorithm is based on the phase comparison of an operating phasor and a polarizing phasor.
When the operating phasor leads the reference polarizing phasor by 90 degrees or more, the function
operates and gives a trip output.
Mho GUID-D162893C-918A-4DDA-AAC2-0D0A814D85C1 v2
The plain Mho circle has the characteristic as in figure 168. The condition for deriving the angle β is
according to equation 73.
(
b = arg VAB - I AB × Z 1set - arg V pol ) ( )
ANSIEQUATION15027 V1 EN-US (Equation 73)
where
is the positive sequence impedance setting for phase-to-phase fault in zone direction
Z 1set
For Zone 1,
where
R1PPZ1 is the positive sequence resistive reach for phase-to-phase fault for zone 1
X1PPZ1 is the positive sequence reactance reach for phase-to-phase fault for zone 1
where
R1Zx is the positive sequence resistive reach for zone x (x = 2-5, BU and RV)
X1Zx is the positive sequence reactance reach for zone x (x = 2-5, BU and RV)
is the polarizing voltage
Vpol
Operation occurs if 90°≤β≤270°
I AB jX
I L1L 2 Z1set
Vcomp VAB I AB Z1set
VAB
V pol
I AB R
ANSI15000060-1-en.vsdx
ANSI15000060 V1 EN-US
Figure 168: Simplified mho characteristic and vector diagram for phase A-to-B fault
The characteristic for offset mho is a circle with origin as the center and magnitude of Z 1set as the
radius, where Z 1set is settable through the resistance and reactance settings.
The condition for operation at phase-to-phase fault is that the angle β between the two compensated
voltages is greater than or equal to 90° (figure 169). The angle will be 90° for fault location on the
boundary of the circle.
V − I ⋅ Z1
β = arg AB AB set
(
VAB − − I AB ⋅ Z 1RVset )
ANSIEQUATION15008 V1 EN-US (Equation 76)
I AB jX
I AB Z 1set
VAB
I AB Z 1RVset
I AB R
ANSI15000058-1-en.vsdx
ANSI15000058 V1 EN-US
Figure 169: Simplified offset mho characteristic and voltage vector for phase A to B fault
GUID-DB8CF641-0D3F-4F7A-A628-829F3DB0AC5B v3
The measuring of earth faults uses earth return compensation applied in a conventional way. The
compensation voltage is derived by considering the influence from the earth return path.
Compensation for earth return path for faults involving earth is done by setting the positive and zero
sequence impedance of the line. It is known that the ground compensation factor KN is,
Z 0set − Z 1set
KN =
3 ⋅ Z 1set
IECEQUATION15017 V1 EN-US
Z 0set = R 0Zx + j ⋅ X 0 Zx
IECEQUATION15018 V1 EN-US
For Zone 1,
Z 1set = R1PEZ 1 + j ⋅ X 1PEZ 1
IECEQUATION15019 V1 EN-US
where
is the complex zero sequence impedance of the line in Ω/phase
Z 0set
is the complex positive sequence impedance of the line in Ω/phase
Z 1set
R1PEZ1 is the positive sequence resistive reach of the line in Ω/phase for
phase-to-ground fault for zone 1
X1PEZ1 is the positive sequence reactance reach of the line in Ω/phase for
phase-to-ground fault for zone 1
R0Zx is the zero sequence resistive reach of the line in Ω/phase for zone x
(x=2 to 5, BU or RV)
X0Zx is the zero sequence reactance reach of the line in Ω/phase for zone
x (x=2 to 5, BU or RV)
For an earth fault in phase A, the angle β between the compensation voltage and the polarizing voltage
Vpol is,
where
is the phase voltage in faulty phase A
VA
is the phase current in faulty phase A
IA
3I 0 is the zero-sequence current in faulty phase A
is the complex positive sequence impedance of the line in Ω/phase
Z 1set for phase-to-ground fault in zone direction
is the polarizing voltage for phase A
Vpol
IA•jX
Vcomp VA ( I A 3I 0 K N ) Z1set
3I 0 K N Z1set
VA
I A Z1set
V pol
IA•R
ANSI15000059-1-en.vsdx
ANSI15000059 V1 EN-US
Figure 170: Simplified offset mho characteristic and vector diagram for phase A-to-ground fault
( ) {
β = arg VA − ( I A + 3I 0 ⋅ K N ) ⋅ Z 1set − arg VA − −( I A + 3I 0 ⋅ K N ⋅ Z 1RVset ] ) }
ANSIEQUATION15022 V1 EN-US (Equation 79)
IA• jX
Vcomp1 VA ( I A 3I 0 K N ) Z1set
( I A 3I 0 K N ) Z1set
VA
( I A 3I 0 K N ) Z1RVset
IA• R
ANSI15000057-1-en.vsdx
ANSI15000057 V1 EN-US
Figure 171: Simplified offset mho characteristic and voltage vector for phase A-to-ground fault
In some cases the measured load impedance might enter the set zone characteristic without any fault on
the protected line. This phenomenon is called load encroachment and it might occur when an external
fault is cleared and high emergency load is transferred onto the protected line. The effect of load
encroachment is illustrated on the left in figure 172. A load impedance within the characteristic would
cause an unwanted trip. The traditional way of avoiding this situation is to set the distance zone resistive
reach with a security margin to the minimum load impedance. The drawback with this approach is that
the sensitivity of the protection to detect resistive faults is reduced.
The IED has a built-in feature which shapes the under-impedance starting characteristic according to
the characteristic shown in figure 172. The load encroachment algorithm will increase the possibility to
detect high fault resistances, especially for phase-to-ground faults at remote line end. For example, for
a given setting of the load angle LdAngle, the resistive blinder for the zone measurement can be set
according to figure 172 affording higher fault resistance coverage without risk for unwanted operation
due to load encroachment. Separate resistive blinder settings are available in forward and reverse
direction.
The use of the load encroachment feature is essential for long heavily loaded lines, where there might
be a conflict between the necessary emergency load transfer and necessary sensitivity of the distance
protection. The function can also preferably be used on heavy loaded, medium long lines. For short
lines, the major concern is to get sufficient fault resistance coverage. Load encroachment is not a major
problem.
The built-in phase selection is based on current change criteria and has no user defined settings.
However, a traditional under-impedance-based phase selector is always working in parallel with it. This
under-impedance-based criterion is defined by the two setting parameters XStart and RStart, as shown
in Figure 172. These two settings are common for both Ph-Ph and Ph-Gnd measurement loops. In order
to ensure proper operation of the distance zones the under-impedance based starting element shall
be set in such a way to always cover (i.e. be larger than) all used distance zones for both Ph-Ph and
Ph-Gnd loops. Consequently, the following settings are recommended:
Parameter XStart shall be set to a value which is at least 20% bigger than the value obtained by formula
(2*X1FwPEZx+X0FwPEZx)/3 applied for the longest reaching zone.
It is recommended that the RStart setting shall not exceed the load impedance, which is typically defined
as UBase/sqrt(3)/IBase in primary ohms. It is recommended to reduce the RStart set value to maximum
80% of the above defined load impedance value. However, the RLdRvFactor and RLdFw settings can
be utilized to get an additional non-operation sector for emergency load, like for when a parallel line is
opened, as shown in Figure 172.
Zm Zm
ZL
ANSI05000495_2_en.vsd
ANSI05000495 V2 EN-US
[1]
When protecting a system with an alternative earthing method, other than direct earthing, there are
some things that need to be done differently in the ZMF. These adaptions are devised by the PPL2
function through its connections with ZMF. See Figure 173
So, besides its strong association with phase preference, the PPL2 will aid ZMF with an auxiliary phase
selection as well as adjustments related to the present earthing method (selected with PPL2 setting
SystemEarthing). This is done through the connection to the ORCND input.
The primary feature is the phase preference, which is fulfilled through the connection from PPL2-ZREL,
which transmits starts of preferred phases, to be released in the distance zones.
To avoid the situation where the ZMF is selecting PE loops but the PPL2 is not releasing them, it is
necessary to bring the internal loop selection inside ZMF in accordance with the PPL2 criterion.
[1] RLdRv=RLdRvFactor*RLdFw
Therefore, we are overriding the customary loop selection inside ZMF with the one decided by PPL2,
which is based mainly on the IN start level (IN>). This is realized by transmitting the IN start from PPL2
to ZMF, as composite data inside the PPL2-START signal.
There is nothing further in ZMF that influences this enforced loop selection. Even the INReleasePE
setting does not change this and may stay at its default value of 400%.
Also, through the connection to the PPL2-ZST output, the use of zero sequence quantities is restricted.
The fault current for a Fw/Rv Cross-country (CC) fault is going out on one line while coming back on
another. So, the standard calculation of earth-return current is not valid. Therefore, the earth return path
and the zero sequence current is removed from the phase-to-earth distance calculation.
Load compensation, which is normally based on the residual current, is disabled as well.
Zero sequence can only show one direction, while the CC fault is two faults, possibly one forward and
one reverse. In practice, the zero sequence direction will always go with the forward fault, while the
preferred fault and phase may be reverse. So, only direction based on phase current is used. When
the two CC faults are in the same direction, there is yet another situation. On un-faulted feeders (radial
especially), the zero sequence direction may show the wrong direction during the voltage asymmetry
because the current can be dominated by the load. ZMF will therefore use negative sequence-based
direction instead, when applicable.
The direction based on zero sequence quantities is directly affected by the neutral resistance, making
the direction resistive rather than inductive. So, with this setting value, the zero sequence direction
characteristic is automatically rotated by 70 degrees to better accommodate the direction. So, the
forward characteristic is rotated from its original 30 - 115 degrees, to -40 - 45 degrees. The reverse
characteristic is exactly 180 degrees behind, in both cases.
The IMinOpPEZx should be set high enough not to allow zones to start due to capacitive currents on
healthy feeders
PHSA, PHSB,...PHSCA are internal binary logical signals from the Phase-selection element. They
correspond directly to the six loops of the distance zones and determine which loops should be released
to possibly issue a pickup or a trip.
The ORCND input enables the use of external elements to supplement the internal phase selection
in specialized applications, like unblocking of the distance protection during power swings. Like with
the other CND signals, each bit of its binary encoded integer number corresponds to one of the six
measuring loops. The ORCND is primarily intended as a support to the internal phase selection, so
ultimately, the internal phase selection may make the final decision on enabling the PE or PP loops. See
Figure 173.
PPL2PHIZ ZMFPDIS
Automatic Phase selection
cross-country ZST
phase selection Internal
ORCND criteria Loop
Phase preference selection
Zone1
L1N L1N bitwise TRZ1
RELCNDZ1 release
AND
L2N L2N
ZREL Zone2
L3N bitwise TRZ2
L3N Bool to RELCNDZ2 release
Integer AND
L1L2 Zone3
bitwise TRZ3
L2L3 RELCNDZ3 release
AND
L3L1 Zone4
RELCNDZ4 bitwise TRZ4
TRUE AND
release
Zone5
RELCNDZ5 bitwise release
TRZ5
AND
ZoneRV
RELCNDZRV bitwise TRZRV
release
AND
ZoneBU
RELCNDZBU bitwise release
TRZBU
AND
IEC16000017 V2 EN-US
FWA, FWB,...FWCA and RVA, RVB,...RVCA are the internal binary signals from the Directional element.
An FW signal is activated if the criteria for a forward fault or load is fulfilled for its particular loop. The
equivalent applies to the reverse (RV) signals.
The internal input 'IN present' is activated if the residual current (3I0) exceeds 10% of the maximum
phase current magnitude and at the same time is above 5% of IBase. However, if current transformer
saturation is detected, this criterion is changed to residual voltage (3V0) exceeding 5% of VBase/sqrt(3)
instead.
DirModeZ3-5
TRUE (1) Non-directional
FWD(n & mn) Forward DIR(n & mn)Z3-5
REV(n & mn) Reverse
ANSI12000137-1-en.vsd
ANSI12000137 V1 EN-US
PGZx
OR
ZMAZx
PHSA AND
DIRAZx AND
ZMBZx
PHSB AND
DIRBZx AND
ZMCZx AZx
OR
PHSC AND
DIRCZx AND
ZMABZx BZx
OR
PHSAB AND
DIRABZx AND
ZMLBCZx CZx
PHSBC AND OR
DIRBCZx AND
ZMCAZx
PHSCA AND
DIRCAZx AND
PPZx
OR
NDZx
OR
ANSI12000140-1-en.vsd
ANSI12000140 V1 EN-US
TimerModeZx =
Enable PhPh or
Ph-G
PPZx AND tPPZx
OR AND
AND t
PGZx
AND tPGZx OR
TimerModeZx = OR
AND t
Enable Ph-G or AND
Ph-G PhPh
BLOCK
VTSZ
BLKZx OR
BLKTRZx
OR
TimerLinksZx
ZoneLinkStart
LoopLink (tPP-tPG)
Phase Selection
LoopLink & ZoneLink
1st pickup zone OR
No Links
LNKZ2
LNKZx
FALSE (0) AND
OR
LNKZ4
TimerLinksZx =
LNKZ5
LoopLink & ZoneLink
EXTNST
ANSI12000139-3-en.vsdx
ANSI12000139 V3 EN-US
TZx 0 TRIPZx
15 ms AND
BLKTRZx
TR_A_Zx
OR AND
BLOCK
LOVBZ TR_B_Zx
OR AND
BLKZx
TR_B_Zx
AND
AZx 0 PU_A_Zx
15 ms AND
BZx 0 PU_B_Zx
15 ms AND
CZx 0 PU_C_Zx
15 ms AND
PPZx
PGZx OR 0 PU_Zx
15 ms AND
NDZx 0 PU_ND_Zx
15 ms AND
ANSI12000138-1-en.vsd
ANSI12000138 V1 EN-US
OR 0 PHG_FLT
15 ms AND
PHSA
PHSB OR 0
15 ms AND
PHSC
OR 0
PHSAB 15 ms AND
PHSBC
OR 0
15 ms AND
PHSCA
OR 0 PHPH_FLT
15 ms AND
BLOCK PU_ND
OR
LOVBZ OR
PU_PHS
ANSI12000133-1-en.vsd
ANSI12000133 V1 EN-US
PHSA
FWA AND
PHSB
OR 0 FWD_A
FWB AND
15 ms AND
PHSC
FWC AND
OR 0 FWD_B
PHSAB 15 ms AND
FWAB AND
PHSBC
FWBC AND OR 0 FWD_C
PHSCA 15 ms AND
FWCA AND
OR
FWD_G
IN present AND
FWD_1PH
=1
BLOCK
LOVBZ OR
FWD_2PH
=2
FWD_3PH
=3
ANSI12000134-1-en.vsd
ANSI12000134 V1 EN-US
PHSA
RVA AND
PHSB
OR 0 REV_A
RVB AND
15 ms AND
PHSC
RVC AND
OR 0 REV_B
PHSAB 15 ms AND
RVAB AND
PHSBC
RVBC AND OR 0 REV_C
PHSCA 15 ms AND
RVCA AND
OR
REV_G
IN present AND
BLOCK
LOVBZ OR
ANSI12000141-1-en.vsd
ANSI12000141 V1 EN-US
9.11.8.10 Measurement
The protection, control, and monitoring IEDs have functionality to measure and further process
information for currents and voltages obtained from the pre-processing blocks. The number of processed
alternate measuring quantities depends on the type of IED and built-in options.
The information on measured quantities is available for the user at different locations:
Measured value below zero point clamping limit is forced to zero. This allows the noise in the input
signal to be ignored. The zero point clamping limit is a setting (XZeroDb where X equals Z).
Users can continuously monitor the measured quantity available in the function block by means of four
defined operating thresholds, see figure 181. The monitoring has two different modes of operating:
• Overfunction, when the measured quantity exceeds the High limit (XHiLim) or High-high limit
(XHiHiLim) pre-set values
• Underfunction, when the measured quantity decreases under the Low limit (XLowLim) or Low-low limit
(XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
IEC05000657 V4 EN-US
Each analog output has one corresponding supervision level output (X_RANGE). The output signal is an
integer in the interval 0-4 (0: Normal, 1: High limit exceeded, 3: High-high limit exceeded, 2: below Low
limit and 4: below Low-low limit).
The logical value of the functional output signals changes according to figure 181.
The user can set the hysteresis (XLimHyst), which determines the difference between the operating
and reset value at each operating point, in wide range for each measuring channel separately. The
hysteresis is common for all operating values within one channel.
The actual value of the measured quantity is available locally and remotely. The measurement is
continuous for each measured quantity separately, but the reporting of the value to the higher levels
depends on the selected reporting mode. The following basic reporting modes are available:
The cyclic reporting of measured value is performed according to chosen setting (XRepTyp). The
measuring channel reports the value independent of magnitude or integral dead-band reporting.
In addition to the normal cyclic reporting the IED also report spontaneously when measured value
passes any of the defined threshold limits.
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
(*)Set value for t: XDbRepInt
IEC05000500 V3 EN-US
If a measuring value is changed, compared to the last reported value, and the change is larger than
the ±ΔY pre-defined limits that are set by user (XDbRepInt), then the measuring channel reports the
new value to a higher level. This limits the information flow to a minimum necessary. Figure 183 shows
an example with the magnitude dead-band supervision. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle from each other.
Value Reported
Y
Value Reported Value Reported
Value Reported
(1st)
Y3 Y
Y
Y2 Y
Y
Y
Y
Y1
IEC99000529 V3 EN-US
After the new value is reported, the ±ΔY limits for dead-band are automatically set around it. The new
value is reported only if the measured quantity changes more than defined by the ±ΔY set limits.
The measured value is reported if the time integral of all changes exceeds the pre-set limit (XDbRepInt),
figure 184, where an example of reporting with integral dead-band supervision is shown. The picture
is simplified: the process is not continuous but the values are evaluated with a time interval of one
execution cycle from each other.
The last value reported, Y1 in figure 184 serves as a basic value for further measurement. A difference
is calculated between the last reported and the newly measured value and is multiplied by the time
increment (discrete integral). The absolute values of these integral values are added until the pre-set
value is exceeded. This occurs with the value Y2 that is reported and set as a new base for the following
measurements (as well as for the values Y3, Y4 and Y5).
The integral dead-band supervision is particularly suitable for monitoring signals with small variations
that can last for relatively long periods.
Y A1 >=
A >= pre-set value A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
(1st) Value
Value Reported Y5
A Reported Value
Reported Value
Y1 Reported
t
IEC99000530 V4 EN-US
In this mode of operation, the reporting interval will be cyclic like in reporting type cyclic and time will
reset on every report. This cyclic time has three options: 5sec, 30 sec and 1 min.
Additionally, if a measuring value has changed from the last reported value, and the change is larger
than ±ΔY predefined limits that are set by user (XDbRepInt), then the measuring channel reports the
new value to a higher level immediately irrespective of cyclic trigger. See Figure 185 for example.
Value
Value
Reported
Y5 Y6
+ΔY
-ΔY
Y”
Y’
Y1 Y2 Y7
Y4
Y3
Δt Δt Δt Δt Δt Δt
Time
IEC16000109-2-en.vsdx
IEC16000109 V2 EN-US
Figure 185: Example of value reporting in mode dead band and xx cyclic (xx : 5 sec , 30 sec, 1 min)
The purpose of dynamic deadband is to report values more frequently in the critical range. The
motivation is to keep the communication and processing load to a minimum in situations where no
imminent action is necessary.
The term <deadband> is used to describe the maximum deviation between the current value of a signal
and the last reported value.
The current value will be reported when the absolute value of the deviation is larger than the computed
deadband. The set value is entered in percent (as relative deadband), the absolute deadband is
calculated with the set value and the last reported value or actual measured value (dynamic deadband
computation).
Dynamic deadband computation will use smaller of the deadband computed from current value and
deadband computed from the last reported value. As a result, deadband of the last reported value will be
used for values moving away from the critical range, while the current value deadband will be used when
the measured value is approaching the critical range.
The effective deadband is always over 0.1% of the total range to prevent excessive reporting of values
close to the minimum value. It is restricted to dB*range using the setting ZdbRepInt, even if the input
value exceeds the configured maximum range value.
A minimum report interval of 250 milli-Seconds is applied to prevent high frequency noise with
amplitudes larger than computed deadband, in the most sensitive value range, from creating excessive
communication load.
Like other deadband profiles, a minimum report rate of 5, 30 or 60 seconds can be specified in the
parameter ZRepTyp. When this time has elapsed, since last report time, the new value will be reported
regardless of deadband or limits.
The applied minimum dead-band for all dead-band types is restricted to 0.1% of the range.
A deadband monitored value will also be reported if the limit value exceeds or when the value cross over
the configure range boundaries.
Rmin
IEC20000216 V1 EN-US
<Curr-Rep value> (dashed line) is the absolute value of the difference between current value and last
reported value.
IEC20000217 V1 EN-US
As the value moves away from critical range (rMin), the deadband increases in steps as a new value is
reported when delta exceeds the deadband calculated with the last reported value. This reported value
will then establish the new deadband.
IEC20000218 V1 EN-US
As the input value moves towards critical range, the deadband decreases with value and current value
will be reported when delta exceeds the deadband calculated with the current value.
IEC20000219 V1 EN-US
For values close to rMin the reported value will follow the input value closely, while more variation is
needed for values close to rMax.
IEC20000220 V1 EN-US
• When one signal belonging to a group triggers a sending, then all other signals in the group will be
sent together.
• All cyclic transmission time and dead bands will be reset at transmission.
• The event grouping is only used for IEC 61850 events.
The magnitude and angle of the impedance for each phase-to-ground and phase-to-phase loop are
available on local HMI, monitoring tools within PCM600 or to the station level, for example, via IEC
61850.
When the operating current is too low, the impedance measurement can be erroneous. To avoid such
error, minimum operating current will be checked. For phase-earth currents or phase-phase currents
lower than 2% of IBase, the resistance and reactance of the impedance are forced to 99 999 ohm,
corresponding to a magnitude at 141419 (99 999*√2) ohm and an angle at 45 degree.
High speed distance protection (ZMFCPDIS, 21) provides sub-cycle, down towards half-cycle, operate
time for basic faults within 60% of the line length and up to around SIR 5. At the same time, it is
specifically designed for extra care during difficult conditions in high voltage transmission networks,
like faults on long heavily loaded lines and faults generating heavily distorted signals. These faults are
handled with utmost security and dependability, although sometimes with reduced operating speed.
High speed distance protection ZMFCPDIS is fundamentally the same function as ZMFPDIS but
provides more flexibility in zone settings to suit more complex applications, such as series compensated
lines. In operation for series compensated networks, the parameters of the directional function are
altered to handle voltage reversal.
The ZMFCPDIS function is a seven-zone full scheme protection with three fault loops for phase-to-
phase faults and three fault loops for phase-to-ground faults for each of the independent zones, which
makes the function suitable in applications with single-phase autoreclosing.
In each measurement zone, ZMFCPDIS function is designed with the flexibility to operate in either
quadrilateral or mho characteristic mode for separate phase-to-earth or phase-to-phase loops.
A new built-in adaptive load compensation algorithm prevents overreaching of the distance zones in
the load exporting end during phase-to-ground faults on heavily loaded power lines. It also reduces
underreach in the importing end.
The ZMFCPDIS function block incorporates a phase-selection element and a directional element,
contrary to previous designs in the IED series, where these elements were represented with separate
function blocks.
The operation of the phase-selection element is primarily based on current change criteria, with
significant increased dependability. There is also an impedance based part operating as continuous
criteria in parallel.
The directional element utilizes a set of well-established quantities to provide fast and correct directional
evaluation during various conditions, including close-in three-phase faults, simultaneous faults and faults
with only zero-sequence in-feed.
The ZMFCPDIS function has another transient components based directional element with phase
segregated outputs STTDFwLx and STTDRVLx (where, x = 1-3), which are intended for permissive
overreaching transfer trip (POTT) scheme. It provides directionality with high speed, dependability
and security, which is also suitable for extra high voltage and series compensated lines where the
fundamental frequency signals are distorted.
The ZMFCPDIS function is also equipped with the parallel line mutual coupling compensation feature
based on the parallel line residual current.
ZMFCPDIS (21)
I3P* TRIP
V3P* TRZ1
INP TR_A_Z1
BLOCK TR_B_Z1
LOVBZ TR_C_Z1
BLKZ1 TRZ2
BLKZ2 TR_A_Z2
BLKZ3 TR_B_Z2
BLKZ4 TR_C_Z2
BLKZ5 TRZ3
BLKZRV TRZ4
BLKZBU TRZ5
BLKTRZ1 TRZRV
BLKTRZ2 TRZBU
BLKTRZ3 BFI_3P
BLKTRZ4 PU_Z1
BLKTRZ5 PU_ND_Z1
BLKTRZRV PU_Z2
BLKTRZBU PU_A_Z2
BLKTD PU_B_Z2
EXTN_PU PU_C_Z2
ORCND PU_ND_Z2
RELCNDZ1 PU_Z3
RELCNDZ2 PU_ND_Z3
RELCNDZ3 PU_Z4
RELCNDZ4 PU_ND_Z4
RELCNDZ5 PU_Z5
RELCNDZRV PU_ND_Z5
RELCNDZBU PU_ZRV
PU_A_RV
PU_B_RV
PU_C_RV
PU_ND_RV
PUZBU
PUNDZBU
PHPUN D
NDIR_A
NDIR_B
NDIR_C
NDIR_G
FWD_A
FWD_B
FWD_C
FWD_G
REV_A
REV_B
REV_C
REV_G
FWD_1PH
FWD_2PH
FWD_3PH
PHG_FLT
PHPH_FLT
PUTDFWA
PUTDFWB
PUTDFWC
PUTDRVA
PUTDRVB
PUTDRVC
ANSI1 1000422-7-en.vsdx
ANSI11000422 V6 EN-US
9.12.5 Signals
PID-8226-INPUTSIGNALS v1
9.12.6 Settings
PID-8226-SETTINGS v1
Settings, input and output names are sometimes mentioned in the following text without its
zone suffix (i.e. BLKZx instead of BLKZ3) when the description is equally valid for all zones.
Practically all voltage, current and impedance quantities used within the ZMFCPDIS function are derived
from fundamental frequency phasors filtered by a half-cycle filter.
The phasor filter is frequency adaptive in the sense that its coefficients are changed based on the
estimated power system frequency.
A half-cycle filter will not be able to reject both even and odd harmonics. While odd harmonics will be
completely attenuated, accuracy will be affected by even harmonics. Even harmonics will not cause the
distance zones to overreach; instead there will be a slightly variable underreach, on average in the same
order as the magnitude ratio between the harmonic and the fundamental component.
The different fault loops within the IED are of full scheme type, which means that ground fault loop for
phase-to-ground faults and phase-to-phase faults for forward and reverse faults are executed in parallel.
Figure 192 presents an outline of the different measuring loops for the seven distance zones.
ANSI05000458‐3‐en‐us.vsdx
ANSI05000458 V3 EN-US
Figure 192: The different measuring loops at phase-to-ground fault and phase-to-phase fault
Transients from CVTs may have a significant impact on the transient overreach of a distance protection.
At the same time these transients can be very diverse in nature from one type to the other; in fact, more
diverse than can be distinguished by the algorithm itself in the course of a few milliseconds. So, a setting
is introduced in order to inform the algorithm about the type of CVT applied and thus providing the
advantage of knowing how performance should be optimized, even during the first turbulent milliseconds
of the fault period.
There are two types of CVTs from the function point of view, the passive and the active type, which
refers to the type of ferro-resonance suppression device that is employed. The active type requires
more rigorous filtering which will have a negative impact on operate times. However, this will be evident
primarily at higher source impedance ratios (SIRs), SIR 5 and above, or close to the reach limit.
The IEC 60044-5 transient classification is of little or no use in relation to this. It is not primarily the
damping of transients that is important; it is the frequency content of the transients that is decisive, i.e.
how difficult it is to filter out the specific frequency. So, even if two CVTs, one passive and the other
active type, comply with the same transient class, the active type requires more extensive filtering in
order to avoid transient overreach.
To avoid overreach and at the same time achieve fast operate times, a supplementary circular
characteristic that includes some alternative processing is implemented. One such circular characteristic
exists for every measuring loop and quadrilateral/mho characteristic. There are no specific reach
settings for this circular zone. It uses the normal quadrilateral/mho zone settings to determine a reach
that will be appropriate. This implies that the circular characteristic will always have somewhat shorter
reach than the quadrilateral/mho zone.
The operation of the phase-selection element is primarily based on current change criteria. The current
change criteria itself can however only be relied on for a short period following the fault inception
(during what we will call the current change phase). Subsequent switching in the network may render
the change in current invalid. To handle this, the phase-selection element also operates on voltage
sequence components based continuous criteria.
The phase-selection element can, owing to the current change criteria, distinguish faults with minimum
influence from load and fault impedance. In other words, it is not restricted by a load encroachment
characteristic during the current change phase. This significantly improves performance for remote
phase-to-ground faults on heavily loaded lines. One exception, however, is three-phase faults, for which
the load encroachment characteristic always has to be applied, in order to distinguish fault from load.
The continuous criteria will in the vast majority of cases operate in parallel and carry on the fault
indication after the current change phase has ended. Only in some particularly difficult faults on heavily
loaded lines the continuous criteria might not be sufficient, for example, when the estimated fault
impedance resides within the load area defined by the load encroachment characteristic. In this case,
the indication will be restricted to a pulse lasting for one or two power system cycles.
Phase-to-phase-ground faults (also called double ground faults) will practically always activate phase-to-
phase zone measurements. Measurement in two phase-to-ground loops at the same time is associated
with so-called simultaneous faults: two ground faults at the same time, one each on the two circuits of a
double line, or when the zero sequence current is relatively high due to a source with low Z0/Z1 ratio. In
these situations zone measurement will be released both for the related phase-to-ground loops and the
phase-to-phase loop simultaneously. On the other hand, simultaneous faults closer to the remote bus
will gradually take on the properties of a phase-to-phase-ground fault and the function will eventually use
phase-to-phase zone measurements also here.
In cases where the fault current infeed is mostly of zero sequence nature (all phase currents in phase),
the measurement will be performed in the phase-to-ground loops only for a phase-to-phase-ground fault.
However, should it be desirable to use phase-to-ground (and only phase-to-ground) zone measurement
for phase-to-phase-ground faults, there is a setting INReleasePE that can be lowered from its excessive
default value to the level above which phase-to-ground measurement should be activated.
AND
2-phase Fault
I3P detected by
Impedance/ current
2-phase fault
V3P PHSLy
based Phase AND
selection
PHSLxLy
AND
a
b
a>b
250%
OR
a
b a>b
50% AND OR
a
b
a<b
INMag
IAMag IN / Imax
IBMag
MAX
ICMag a ForcePE
b
a<b
INReleasePE
ANSI17000230-1-en.vsdx
ANSI17000230 V1 EN-US
Several criteria are employed when making the directional decision. The basis is provided by comparing
a positive sequence based polarizing voltage with phase currents. For extra security, especially in
making a very fast decision, this method is complemented with an equivalent comparison where, instead
of the phase current, the change in phase current is used. Moreover, a basic negative sequence
directional evaluation is taken into account as a reliable reference during high load condition. Finally, a
zero sequence directional evaluation is used whenever there is more or less exclusive zero sequence
in-feed.
The directional sectors that represent forward direction, one per measuring loop, are defined by the
following equations.
VPolA
ArgDir <arg ArgNegRes
IA
VPolAB
ArgDir <arg ArgNegRes
I AB
Where:
VPolA is the polarizing voltage for phase A.
IA is the phase current in phase A.
VPolAB is the polarizing voltage difference between phase A and B (B lagging A).
IAB is the current difference between phase A and B (B lagging A).
The corresponding reverse directional sectors range from (-ArgDir+180) to (ArgNegRes-180) degrees.
Since the polarizing voltage is also used for the Mho distance characteristics, the magnitude of the
voltage is just as interesting as the phase. If there are symmetrical conditions and the measured per
phase positive sequence voltage magnitude is above 75% of the base voltage before the fault, the
pre-fault magnitude will be memorized and used as long as there is a fault. The phase angle however
will only be memorized (locked) for 75 ms at a time, not to lose synchronism with the real system
voltage.
Should the positive sequence voltage drop below 2% of the base voltage, it will be considered invalid. In
this situation, directional signals and pickups from Mho elements will be sealed-in and kept static as long
as there is a fault.
For ZMFCPDIS, when option SeriesComp is chosen for OperationSC, the voltages of faulty phases will
be discarded in order not to affect the polarizing voltage with voltage reversal.
The ZMFCPDIS (21) function has another directional element with phase segregated outputs
STTDFwLx and STTDRVLx (where, x=1-3), which are intended for the permissive overreaching transfer
trip (POTT) scheme. It provides directionality with high speed, dependability and security. It is also
suitable for extra high voltage and series compensated lines where the fundamental frequency signals
are distorted. The transient directional element is based on the changes in voltage and current signals
due to a fault. The changes can be calculated by subtracting the pre-fault voltage and current from the
measured quantiles due to a fault as shown below:
u t u t u p t
i t i t i p t
IECEQUATION18056 V1 EN-US (Equation 82)
Where,
∆u(t) and ∆i(t) are the changes in voltage and current due to the fault.
u(t) and i(t) are the measured voltage and current during the fault.
up(t) and ip(t) are the pre-fault voltage and pre-fault current.
When the power network is under stable operation, ∆u(t) and ∆i(t) are negligible. When a fault occurs,
∆u(t) and ∆i(t) become visible due to the changes in electrical state of the power network. According to
the superposition principle, after a forward fault, ∆u(t) and ∆i(t) are opposite in sign. While after a reverse
fault, ∆u(t) and ∆i(t) are of equal sign.
By inserting a proper replica impedance ZR into the measurement path, a replica delta voltage ΔuR(t),
which is approximately proportional to ∆i(t), is obtained by ΔuR(t) = Δi(t)*ZR. The replica impedance is
optimized in the design to make the relay characteristic angle at 60 degree. Δu(t)*ΔuR(t) is negative for a
forward fault, and positive for a reverse fault.
The operating quantity can be obtained using a simple waveform integration function:
N
2
F t u t u t dt
0
R
Where, Th– and Th+ are the thresholds for negative and positive polarities of F(t).
To enable good security, the reverse detector is more sensitive compared to the forward one by a much
lower magnitude of Th+ than Th–.
Due to the transient nature, directionality decisions are required to be made after a short duration
when the phase-selection element has detected a fault. Once the decision is made, it issues directional
indications with pulses of duration at about 3-4 cycles.
The transient element has a good sensitivity for the initial fault. In certain cases, for example, a fault with
extremely high fault resistance, where Δu(t) or Δi(t) are very low and the transient directional element
is not active, the fundamental frequency component based directional elements (see Section Directional
criteria) will be available after a certain delay.
The ZMFCPDIS function has to be blocked by an additional function like the Fuse failure supervision
(FUFSPVC) or an equivalent external device. Typically, the binary input VTSZ is used for this purpose.
However, to guarantee that also very fast operation is blocked in a fuse failure situation, there is a
built-in supervision based on change in current that will delay operation before the FUFSPVC blocking
signal is received. The delay will be introduced if no (vector) magnitude change greater than 5% of
IBase has been detected in any of the phase currents.
There is need for external blocking of the ZMFCPDIS function during power swings, either from the
Power Swing Blocking function (ZMRPSB) or an external device.
ZMFCPDIS implements quadrilateral and mho characteristic in all the seven zones separately. Set
OpModePEZx or OpModePPZx to Quadrilateral, to choose particular measuring loop in a zone to work
as quadrilateral distance protection.
All ZMFCPDIS zones operate according to the non-directional impedance characteristics presented in
figure 194 and figure 195. The phase-to-ground characteristic is illustrated with the full loop reach while
the phase-to-phase characteristic presents the per-phase reach.
The voltage and current phasors after the half-cycle filter are used in fault loop equations.
For phase-to-phase faults (Figure 196, lower part), the calculated impedances from the relay to the fault
Z calc Rcalc j X calc follow Equation 84 (example is given for a phase L1 to phase L2 fault).
U L1 U L 2 I L1 I L 2 Z calc
IECEQUATION18003 V1 EN-US (Equation 84)
Where and represents the corresponding voltage and current phasors in the respective phase Ln
(n = 1, 2, 3).
The calculated Rcalc and Xcalc are compared with the non-directional phase-to-phase quadrilateral
characteristics. If is inside the non-directional phase-to-phase characteristic, the STNDZx output
is set to TRUE.
For phase-to-ground faults (Figure 196, upper part), the ground return compensation applies according
to Equation 85 (example for a phase L1 to ground fault).
U L1 I L1 K N 3I 0 p Z1 I F RF
IECEQUATION18007 V1 EN-US (Equation 85)
Where,
p is the fault location and RF is the calculated fault resistance. p and RF are unknown and needs to be
solved.
Z 0 Z1
KN
3 Z1
Z 0 R0 FwPEZx j X 0 FwPEZx
Z1 R1FwPEZx j X 1FwPEZx
IECEQUATION18020 V1 EN-US
Where,
R1FwPEZx is the positive sequence resistive reach of the line in Ω/phase for phase-to-ground fault in
zone direction for zone x (x = 1 to 5, BU or RV).
X1FwPEZx is the positive sequence reactance reach of the line in Ω/phase for phase-to-ground fault in
zone direction for zone x (x = 1 to 5, BU or RV).
R0FwPEZx is the zero-sequence resistive reach of the line in Ω/phase for phase-to-ground fault in zone
direction for zone x (x = 1 to 5, BU or RV).
X0FwPEZx is the zero-sequence reactance reach of the line in Ω/phase for phase-to-ground fault in
zone direction for zone x (x = 1 to 5, BU or RV).
is the fault current. It is chosen among phase, zero or negative sequence currents automatically
by the built-in adaptive load compensation algorithm. If the system behind the relay cannot contribute
enough zero-sequence current, only phase or negative sequence current will be chosen.
The calculated impedances from the relay to the fault Z calc Rcalc j X calc can be represented as:
X calc p X 1FwPEZx
Rcalc p R1FwPEZx RF
IECEQUATION18021 V1 EN-US
When the two unknowns p and RF are solved from the Equation 84 then the calculated Rcalc and Xcalc
values are compared with the non-directional phase-to-ground quadrilateral characteristics. If is
inside the non-directional phase-to-ground characteristic, the STNDZx output is set to TRUE.
The load compensation for zone 1 is achieved by estimating the impedance with three different values of
the IF current with:
• neutral current
• negative sequence current
• phase current.
Impedance estimation is based on the neutral current or negative sequence current essentially that
excludes the current component that causes the over-reach. The reactance values from all the
calculations shall effectively be within the zone reactive boundary in order to get the non-directional
start signal from the zone. This means that the under-reach, that is caused by the load import, is not
compensated.
For the other zones, it is enough in effect if the median value of the three is within the zone reach. If
the neutral current is not sufficient, then the negative sequence current based reactance will represent
the median value. If the negative sequence current is not sufficient, then the other reactance has to be
within the reach.
X (Ohm/loop)
X0FwPGZx , X1FwPGZx
XNFwZx <
R1FwPGZx+RNFwZx 3
X1RvPGZx
XNRvZx < XNFwZx √
RFRvPGZx RFFwPGZx X1FwPGZx
R0FwPGZx,R1FwPGZx
RNFwZx <
3
X1RvPGZx
RNRvZx < RNFwZx √
X1FwPGZx
X1RvPGZx
X1FwPGZx+XNFwZx R1RvPGZx < R1FwPGZx √
X1FwPGZx
ιN ιN
R (Ohm/loop)
1) 1)
RFRvPGZx RFFwPGZx
X1RvPGZx+XNRvZx
ιN
RFRvPGZx RFFwPGZx
Figure 194: ZMFCPDIS Characteristic for phase-to-ground measuring loops, ohm/loop domain
R1FwPPZx
X (Ohm/phase)
RFRvPPZx RFFwPPZx
2 2
X1FwPPZx
ιN
R (Ohm/phase)
1) 1)
RFRvPPZx RFFwPPZx
2 2
X1RvPPZx
ιN
RFRvPPZx RFFwPPZx
2 2
X1RvPPZx IEC11000418-3-en.vsd
R1FwPPZx √
X1FwPPZx
Figure 195: ZMFCPDIS Characteristic for the phase-to-phase measuring loops, ohm/phase domain
Note that for ZMFCPDIS, the reverse zone ZRV, as well as any of zones 3-5, that are
set to DirMode=Reverse will get their operating impedances inverted (rotated 180 degrees)
internally in order to make use of the main settings, which are the settings designated ‘Fw’.
Therefore, a reverse zone will have its Fw-settings (RFFwPPZRV, X1FwPGZ3, and so on)
applied in the third quadrant, that is, towards the busbar instead of the line.
The fault loop reach in relation to each fault type may also be presented as in figure 196. The main
intension with this illustration is to make clear how the fault resistive reach should be interpreted. Note
in particular that the setting RFPP always represents the total fault resistance of the loop, even while
the fault resistance (arc) may be divided into parts like for three-phase or phase-to-phase-to-ground
faults. R1Zx and jX1Zx represent the positive sequence impedance from the measuring point to the fault
location.
IA R1 + j X1
Phase-to-ground
VA
element
Phase-to-ground
RFPG
fault in phase A
(Arc + tower
resistance)
N
IG (R0-R1)/3 +
j (X0-X1)/3 )
IA R1 + j X1 Phase-to-phase
VA element A-B
Phase-to-phase
fault in phase RFPP
A-B IB
VB (Arc resistance)
R1 + j X1
IA R1 + j X1 0.5·RFPP Phase-to-phase
VA element A-C
Three-phase
fault or Phase-to-
phase-ground fault IC
VC
R1 + j X1 0.5·RFPP
ANSI11000419-3-en.vsd
ANSI11000419 V3 EN-US
The estimated impedance needs to be inside both characteristics for the zone to start or trip. (The
non-directional start STNDZx is an exception however. It is only dependent on the quadrilateral
characteristic.)
In the following figure, it is shown how the X1PP setting can influence the shape of the quadrilateral
characteristic in the fourth quadrant for short line applications.
X (ohm)
X1PP’
X1PP
15° R (ohm)
RFPP/2
-X1PP
R· tan15°
-X1PP’
Line distance protection=IEC19000141=2=en-us=Original.vsdx
IEC19000141 V2 EN-US
Figure 197: Influence of X1PP setting on the quadrilateral shape in the fourth quadrant
The quadrilateral phase-to-earth element is extended with the parallel line mutual coupling
compensation feature based on the parallel line residual current. The additional current signal must
be connected to the function through the INP group input. The parallel line residual current hardware
channel must be connected to the residual quantity input of the corresponding SMAI block. The
compensation feature can be switched On/Off with the EnPar setting.
When the parallel compensation is switched On (EnPar is On), the phase-to-ground loop Equation 85 is
modified according to Equation 86 (example is given for phase L1 to earth fault).
U L1 ( I L1 K N 3I 0 K Nm 3I 0 p ) p Z1 I F RF
IECEQUATION20296 V1 EN-US (Equation 86)
Z0m
K Nm =
3 Z1
IECEQUATION20299 V1 EN-US
Z 0 m = R0MZx + j X 0MZx
IECEQUATION20300 V1 EN-US
Where,
Z 0m is the set complex zero-sequence mutual impedance between parallel lines in Ω/phase.
is the zero-sequence resistance between parallel lines in Ω/phase for the phase-to-ground
fault in zone direction for zone x (where x = 1 to 2).
is the zero-sequence reactance between parallel lines in Ω/phase for the phase-to-ground fault
in zone direction for zone x (where x = 1 to 2).
The compensation feature will only be active when the parallel line residual current is not significantly
higher than the protected line residual current. The deactivation limit of this parallel line compensation
feature is set with the INPRatio setting. Compensation is deactivated when:
3I0p
INPRatio
3I0
IECEQUATION20302 V1 EN-US
The mutual compensation is also deactivated when the protected line residual current is less than 50%
of IMinOp according to the below relation:
3I 0 0.5 IMin0 p
IECEQUATION20303 V1 EN-US
ZMFCPDIS implements quadrilateral and mho characteristic in all the seven zones separately. Set
OpModePEZx or OpModePPZx setting to Mho or Offset, to choose a particular measuring loop in a zone
to work as mho (or Offset Mho) distance protection.
Zones 2 to 5 and BU can be selected to be either forward or reverse with positive sequence polarized
mho characteristic; alternatively self polarized offset mho characteristics. The operating characteristic is
in accordance to figure 198 where zone 5 is selected offset mho.
X
ZBU X
Z4
Z3
ZS=0
Z2
Z1 R
Z5 R
ZS=Z1
ZRV
ZS=2Z1
IEC150000 56-2-en.vsdx
IEC15000056 V2 EN-US
Figure 198: Mho, offset mho characteristics and the source impedance influence on the mho characteristic
The mho characteristic has a dynamic expansion due to the source impedance. Instead of crossing
the origin, as for the mho to the left of figure 198, which is only valid where the source impedance
(Zs) is zero, the crossing point is moved to the coordinates of the negative source impedance given
an expansion of the circle shown to the right of figure 198. Z1 denotes the complex positive sequence
impedance.
The magnitude of the polarized voltage is determined completely by the positive sequence voltage
magnitude from before the fault. This will give a somewhat less dynamic expansion of the mho circle
during faults. However, if the source impedance is high, the dynamic expansion of the mho circle might
lower the security of the function too much with high loading and mild power swing conditions.
In ZMFCPDIS, each zone measurement loop characteristic can be set to mho characteristic or offset
mho characteristic by setting OpModePEZx or OpModePPZx (where x = 1 to 5, BU or RV depending on
selected zone).
ZMFCPDIS fixes zone 1 in Forward mode and zone RV in Reverse mode. Zone 2 to 5 and BU can be
set to Non-directional, Forward or Reverse by setting the parameter DirModeZx (where x = 2 to 5 or BU
depending on selected zone).
X X
(a) Rset
X (c)
(b) Rset
Rset
Mho Characteristics
(a) and (d) are for Zone 1, Zone 2 and Zone 3-5 when DirModeZ2-BU = Forward
(b) and (e) are for ZoneRV and Zone 3-5 when DirModeZ2-BU = Reverse
(c) and (f) are for Zone 3-5 when DirModeZ2-BU = Non-Directional
X=2 to 5 or BU IEC150000 65-4-en-us.vsdx
IEC15000065 V4 EN-US
For each zone, the impedance is set in cartesian coordinates (resistance and reactance) which is the
same as for quadrilateral characteristic.
ZMFCPDIS function uses separate sets of reach settings in forward and reverse directions for
phase-to-earth fault and phase-to-phase fault. These settings are R1FwPPZx, X1FwPPZx, X1RvPPZx,
R1FwPEZx, X1FwPEZx, X1RvPEZx, R0FWPEZx, X0FwPPZx (x= 1 to 5, BU or RV). Thus, the center of
the Non-directional offset mho circle can be arbitrarily located in the circle (figure 199).
Note that the reverse ZoneRV, as well as any of zones 3 to 5 and BU, that are set to
DirModeZx=Reverse will get their operating impedances inverted (rotated 180 degrees) internally in
order to make use of the main settings, which are the settings designated ‘Fw’. Therefore, a reverse
zone will have its Fw-settings (R1FwPPZRV, X1FwPEZ3, and so on) applied in the third quadrant, that
is, towards the busbar instead of the line.
In Non-directional mode, for both Mho and Quad, the reach settings are equal to Forward mode in this
respect. The ‘Fw’ settings apply in the first quadrant and the ‘Rv’ settings apply in the third quadrant.
The mho algorithm is based on the phase comparison of an operating phasor and a polarizing phasor.
When the operating phasor leads the reference polarizing phasor by 90 degrees or more, the function
operates and gives a trip output.
(
b = arg VAB - I AB × Z 1set - arg V pol ) ( )
ANSIEQUATION15027 V1 EN-US (Equation 87)
where
is the positive sequence impedance setting for phase-to-phase fault in zone direction
Z 1set
is the polarizing voltage
Vpol
where:
R1FwPPZx is the positive sequence resistive reach for phase-to-phase fault in zone direction for zone x (x=1 to 5, BU and
RV)
X1FwPPZx is the positive sequence reactance reach for phase-to-phase fault in zone direction for zone x (x=1 to 5 BU
and RV)
The polarized voltage consists of 100% memorized positive sequence voltage (VAB for phase A to B
fault). The memorized voltage will prevent collapse of the mho circle for close in faults.
I AB jX
I L1L 2 Z1set
Vcomp VAB I AB Z1set
VAB
V pol
I AB R
ANSI15000060-1-en.vsdx
ANSI15000060 V1 EN-US
Figure 200: Simplified mho characteristic and vector diagram for phase A-to-B fault
The condition for operation at phase-to-phase fault is that the angle β between the two compensated
voltages is greater than or equal to 90° (figure 201). The angle will be 90° for fault location on the
boundary of the circle.
V − I ⋅ Z1
β = arg AB AB set
(
VAB − − I AB ⋅ Z 1RVset )
ANSIEQUATION15008 V1 EN-US (Equation 90)
where
is the positive sequence impedance setting for phase-to-phase fault
Z 1RVset opposite to zone direction and is defined as
where
X1RvPPZx is the positive sequence reactance reach for phase-to-phase fault
opposite to zone direction for zone x (x=1 to 5, BU or RV)
R1RvPPZx is the positive sequence resistive reach for phase-to-phase fault
opposite to zone direction for zone x (x=1 to 5, BU or RV) and is
internally calculated according to the equation below,
R1FwPPZx
R1RvPPZx = X 1RvPPZx ⋅
X 1FwPPZx
IECEQUATION15014 V1 EN-US (Equation 92)
I AB jX
I AB Z 1set
VAB
I AB Z 1RVset
I AB R
ANSI15000058-1-en.vsdx
ANSI15000058 V1 EN-US
Figure 201: Simplified offset mho characteristic and voltage vector for phase A to B fault
Compensation for earth return path for faults involving earth is done by setting the positive and zero
sequence impedance of the line. It is known that the ground compensation factor KN is,
Z 0set − Z 1set
KN =
3 ⋅ Z 1set
IECEQUATION15017 V1 EN-US
where
For an earth fault in phase A, the angle β between the compensation voltage and the polarizing voltage
Vpol is,
where
is the phase voltage in faulty phase A
VA
is the phase current in faulty phase A
IA
3I 0 is the zero-sequence current in faulty phase A
is the complex positive sequence impedance of the line in Ω/phase
Z 1set for phase-to-ground fault in zone direction
is the polarizing voltage in phase A
Vpol
IA•jX
Vcomp VA ( I A 3I 0 K N ) Z1set
3I 0 K N Z1set
VA
I A Z1set
V pol
IA•R
ANSI15000059-1-en.vsdx
ANSI15000059 V1 EN-US
Figure 202: Simplified offset mho characteristic and vector diagram for phase A-to-ground fault
( ) {
β = arg VA − ( I A + 3I 0 ⋅ K N ) ⋅ Z 1set − arg VA − −( I A + 3I 0 ⋅ K N ⋅ Z 1RVset ] ) }
ANSIEQUATION15022 V1 EN-US (Equation 95)
where
is the complex positive sequence impedance of the line in Ω/phase
Z 1RVset for phase-to-ground fault opposite to zone direction and is defined as,
where
X1RvPEZx is the positive sequence reactance reach for phase-to-ground fault
opposite to zone direction for zone x (x=1-5, BU and RV)
R1RvPEZx is the positive sequence resistive reach for phase-to-ground fault
opposite to zone direction for zone x (x=1-5, BU and RV) and
expressed by,
R1FwPEZx
R1RvPEZx = X 1RvPEZx ⋅
X 1FwPEZx
IECEQUATION15024 V1 EN-US (Equation 97)
In some cases the load impedance might enter the zone characteristic without any fault on the protected
line. The phenomenon is called load encroachment and it might occur when an external fault is cleared
and high emergency load is transferred on the protected line. The effect of load encroachment is
illustrated in the left part of figure 203. A load impedance within the characteristic would cause an
unwanted trip. The traditional way of avoiding this situation is to set the distance zone resistive reach
with a security margin to the minimum load impedance. The drawback with this approach is that the
sensitivity of the protection to detect resistive faults is reduced.
The IED has a built-in function which shapes the under-impedance starting characteristic according
to the right part of figure 203. The load encroachment algorithm will increase the possibility to detect
high fault resistances, especially for phase-to-ground faults at remote line end.For example, for a given
setting of the load angle LdAngle the resistive blinder for the zone measurement can be expanded
according to the right part of the figure 203, given higher fault resistance coverage without risk for
unwanted operation due to load encroachment. This is valid in both directions.
The use of the load encroachment feature is essential for long heavily loaded lines, where there
might be a conflict between the necessary emergency load transfer and necessary sensitivity of the
distance protection. The function can also preferably be used on heavy loaded medium long lines. For
short lines, the major concern is to get sufficient fault resistance coverage. Load encroachment is not
a major problem. Nevertheless, always set RLdFwd, RldRev and LdAngleaccording to the expected
maximum load since these settings are used internally in the function as reference points to improve the
performance of the phase selection.
As already explained the built-in phase selection is mostly based on current change criteria and has no
user defined settings. However, a traditional under-impedance-based phase selector is always working
in parallel with it. This under-impedance-based criterion is defined by the two setting parameters XStart
and RStart, as shown in Figure 203. These two settings are common for both Ph-Ph and Ph-Gnd
measurement loops. In order to ensure proper operation of the distance zones the under-impedance
based starting element shall be set in such a way to always cover (i.e. be larger than) all used distance
zones for both Ph-Ph and Ph-Gnd loops. Consequently, the following settings are recommended:
Parameter XStart shall be set to a value which is at least 20% bigger than the value obtained by formula
(2*X1FwPEZx+X0FwPEZx)/3 applied for the longest reaching zone.
It is recommended that the RStart setting shall not exceed the load impedance, which is typically defined
as UBase/sqrt(3)/IBase in primary ohms. It is recommended to reduce the RStart set value to maximum
80% of the above defined load impedance value. However, the RLd settings can be utilized to get an
additional non-operation sector for emergency load, like for when a parallel line is opened, as shown in
Figure 203.
Zm Zm
ZL
ANSI05000495_2_en.vsd
ANSI05000495 V2 EN-US
When protecting a system with an alternative earthing method, other than direct earthing, there are
some things that need to be done differently in the ZMF. These adaptions are devised by the PPL2
function through its connections with ZMF. See Figure 173
So, besides its strong association with phase preference, the PPL2 will aid ZMF with an auxiliary phase
selection as well as adjustments related to the present earthing method (selected with PPL2 setting
SystemEarthing). This is done through the connection to the ORCND input.
The primary feature is the phase preference, which is fulfilled through the connection from PPL2-ZREL,
which transmits starts of preferred phases, to be released in the distance zones.
To avoid the situation where the ZMF is selecting PE loops but the PPL2 is not releasing them, it is
necessary to bring the internal loop selection inside ZMF in accordance with the PPL2 criterion.
Therefore, we are overriding the customary loop selection inside ZMF with the one decided by PPL2,
which is based mainly on the IN start level (IN>). This is realized by transmitting the IN start from PPL2
to ZMF, as composite data inside the PPL2-START signal.
There is nothing further in ZMF that influences this enforced loop selection. Even the INReleasePE
setting does not change this and may stay at its default value of 400%.
Also, through the connection to the PPL2-ZST output, the use of zero sequence quantities is restricted.
The fault current for a Fw/Rv Cross-country (CC) fault is going out on one line while coming back on
another. So, the standard calculation of earth-return current is not valid. Therefore, the earth return path
and the zero sequence current is removed from the phase-to-earth distance calculation.
Load compensation, which is normally based on the residual current, is disabled as well.
Zero sequence can only show one direction, while the CC fault is two faults, possibly one forward and
one reverse. In practice, the zero sequence direction will always go with the forward fault, while the
preferred fault and phase may be reverse. So, only direction based on phase current is used. When
the two CC faults are in the same direction, there is yet another situation. On un-faulted feeders (radial
especially), the zero sequence direction may show the wrong direction during the voltage asymmetry
because the current can be dominated by the load. ZMF will therefore use negative sequence-based
direction instead, when applicable.
The direction based on zero sequence quantities is directly affected by the neutral resistance, making
the direction resistive rather than inductive. So, with this setting value, the zero sequence direction
characteristic is automatically rotated by 70 degrees to better accommodate the direction. So, the
forward characteristic is rotated from its original 30 - 115 degrees, to -40 - 45 degrees. The reverse
characteristic is exactly 180 degrees behind, in both cases.
The IMinOpPEZx should be set high enough not to allow zones to start due to capacitive currents on
healthy feeders
PHSA, PHSB,...PHSCA are internal binary logical signals from the Phase-selection element. They
correspond directly to the six loops of the distance zones and determine which loops should be released
to possibly issue a pickup or a trip.
The ORCND input enables the use of external elements to supplement the internal phase selection
in specialized applications, like unblocking of the distance protection during power swings. Like with
the other CND signals, each bit of its binary encoded integer number corresponds to one of the six
measuring loops. The ORCND is primarily intended as a support to the internal phase selection, so
ultimately, the internal phase selection may make the final decision on enabling the PE or PP loops. See
Figure 204.
PPL2PHIZ ZMFPDIS
Automatic Phase selection
cross-country ZST
phase selection Internal
ORCND criteria Loop
Phase preference selection
Zone1
L1N L1N bitwise TRZ1
RELCNDZ1 release
AND
L2N L2N
ZREL Zone2
L3N bitwise TRZ2
L3N Bool to RELCNDZ2 release
Integer AND
L1L2 Zone3
bitwise TRZ3
L2L3 RELCNDZ3 release
AND
L3L1 Zone4
RELCNDZ4 bitwise TRZ4
TRUE AND
release
Zone5
RELCNDZ5 bitwise release
TRZ5
AND
ZoneRV
RELCNDZRV bitwise TRZRV
release
AND
ZoneBU
RELCNDZBU bitwise release
TRZBU
AND
IEC16000017 V2 EN-US
FWA, FWB,...FWCA and RVA, RVB,...RVCA are the internal binary signals from the Directional element.
An FW signal is set true if the criteria for a forward fault or load is fulfilled for its particular loop. The
same applies to the reverse (RV) signals.
The internal input 'IN present' is true if the residual current (3I0) exceeds 7% of IBase. However, if
current transformer saturation is detected, this criterion is changed to residual voltage (3V0) exceeding
5% of VBase/sqrt(3) instead.
DirModeZ3-5
TRUE (1) Non-directional
FWD(n & mn) Forward DIR(n & mn)Z3-5
REV(n & mn) Reverse
ANSI12000137-1-en.vsd
ANSI12000137 V1 EN-US
PGZx
OR
ZMAZx
PHSA AND
DIRAZx AND
ZMBZx
PHSB AND
DIRBZx AND
ZMCZx AZx
OR
PHSC AND
DIRCZx AND
ZMABZx BZx
OR
PHSAB AND
DIRABZx AND
ZMLBCZx CZx
PHSBC AND OR
DIRBCZx AND
ZMCAZx
PHSCA AND
DIRCAZx AND
PPZx
OR
NDZx
OR
ANSI12000140-1-en.vsd
ANSI12000140 V1 EN-US
TimerModeZx =
Enable PhPh or
Ph-G
PPZx AND tPPZx
OR AND
AND t
PGZx
AND tPGZx OR
TimerModeZx = OR
AND t
Enable Ph-G or AND
Ph-G PhPh
BLOCK
VTSZ
BLKZx OR
BLKTRZx
OR
TimerLinksZx
ZoneLinkStart
LoopLink (tPP-tPG)
Phase Selection
LoopLink & ZoneLink
1st pickup zone OR
No Links
LNKZ2
LNKZx
FALSE (0) AND
OR
LNKZ4
TimerLinksZx =
LNKZ5
LoopLink & ZoneLink
EXTNST
ANSI12000139-3-en.vsdx
ANSI12000139 V3 EN-US
TZx 0 TRIPZx
15 ms AND
BLKTRZx
TR_A_Zx
OR AND
BLOCK
LOVBZ TR_B_Zx
OR AND
BLKZx
TR_B_Zx
AND
AZx 0 PU_A_Zx
15 ms AND
BZx 0 PU_B_Zx
15 ms AND
CZx 0 PU_C_Zx
15 ms AND
PPZx
PGZx OR 0 PU_Zx
15 ms AND
NDZx 0 PU_ND_Zx
15 ms AND
ANSI12000138-1-en.vsd
ANSI12000138 V1 EN-US
OR 0 PHG_FLT
15 ms AND
PHSA
PHSB OR 0
15 ms AND
PHSC
OR 0
PHSAB 15 ms AND
PHSBC
OR 0
15 ms AND
PHSCA
OR 0 PHPH_FLT
15 ms AND
BLOCK PU_ND
OR
LOVBZ OR
PU_PHS
ANSI12000133-1-en.vsd
ANSI12000133 V1 EN-US
PHSA
FWA AND
PHSB
OR 0 FWD_A
FWB AND
15 ms AND
PHSC
FWC AND
OR 0 FWD_B
PHSAB 15 ms AND
FWAB AND
PHSBC
FWBC AND OR 0 FWD_C
PHSCA 15 ms AND
FWCA AND
OR
FWD_G
IN present AND
FWD_1PH
=1
BLOCK
LOVBZ OR
FWD_2PH
=2
FWD_3PH
=3
ANSI12000134-1-en.vsd
ANSI12000134 V1 EN-US
PHSA
RVA AND
PHSB
OR 0 REV_A
RVB AND
15 ms AND
PHSC
RVC AND
OR 0 REV_B
PHSAB 15 ms AND
RVAB AND
PHSBC
RVBC AND OR 0 REV_C
PHSCA 15 ms AND
RVCA AND
OR
REV_G
IN present AND
BLOCK
LOVBZ OR
ANSI12000141-1-en.vsd
ANSI12000141 V1 EN-US
TDFWL1 AND
15 ms
TDFWL2 AND OR t
AND
PHSL3
TDFWL3 AND 15 ms
PHSL1L2 OR t STTDFWL2
AND
AND
AND 15 ms
PHSL2L3 OR t STTDFWL3
AND AND
AND
PHSL3L1
AND
AND
PHSL1
TDRVL1 AND
15 ms
TDRVL2 AND OR t
AND
AND 15 ms
OR t STTDRVL2
AND
AND
AND 15 ms
PHSL2L3 OR t STTDRVL3
AND AND
AND
PHSL3L1
AND
AND
VTSZ
OR
BLOCKTD
IEC18000241-1-en.vsdx
IEC18000241 V1 EN-US
In Figure 212, inputs TDFWLx and TDRVLx (where, x = 1-3) are the directionalities calculated internally
by the transient directional element.
9.12.8.12 Measurement
The protection, control, and monitoring IEDs have functionality to measure and further process
information for currents and voltages obtained from the pre-processing blocks. The number of processed
alternate measuring quantities depends on the type of IED and built-in options.
The information on measured quantities is available for the user at different locations:
Measured value below zero point clamping limit is forced to zero. This allows the noise in the input
signal to be ignored. The zero point clamping limit is a setting (XZeroDb where X equals Z).
Users can continuously monitor the measured quantity available in the function block by means of four
defined operating thresholds, see figure 213. The monitoring has two different modes of operating:
• Overfunction, when the measured quantity exceeds the High limit (XHiLim) or High-high limit
(XHiHiLim) pre-set values
• Underfunction, when the measured quantity decreases under the Low limit (XLowLim) or Low-low limit
(XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
IEC05000657 V4 EN-US
Each analog output has one corresponding supervision level output (X_RANGE). The output signal is an
integer in the interval 0-4 (0: Normal, 1: High limit exceeded, 3: High-high limit exceeded, 2: below Low
limit and 4: below Low-low limit).
The logical value of the functional output signals changes according to figure 213.
The user can set the hysteresis (XLimHyst), which determines the difference between the operating
and reset value at each operating point, in wide range for each measuring channel separately. The
hysteresis is common for all operating values within one channel.
The actual value of the measured quantity is available locally and remotely. The measurement is
continuous for each measured quantity separately, but the reporting of the value to the higher levels
depends on the selected reporting mode. The following basic reporting modes are available:
The cyclic reporting of measured value is performed according to chosen setting (XRepTyp). The
measuring channel reports the value independent of magnitude or integral dead-band reporting.
In addition to the normal cyclic reporting the IED also report spontaneously when measured value
passes any of the defined threshold limits.
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
If a measuring value is changed, compared to the last reported value, and the change is larger than
the ±ΔY pre-defined limits that are set by user (XDbRepInt), then the measuring channel reports the
new value to a higher level. This limits the information flow to a minimum necessary. Figure 215 shows
an example with the magnitude dead-band supervision. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle from each other.
Value Reported
Y
Value Reported Value Reported
Value Reported
(1st)
Y3 Y
Y
Y2 Y
Y
Y
Y
Y1
IEC99000529 V3 EN-US
After the new value is reported, the ±ΔY limits for dead-band are automatically set around it. The new
value is reported only if the measured quantity changes more than defined by the ±ΔY set limits.
The measured value is reported if the time integral of all changes exceeds the pre-set limit (XDbRepInt),
figure 216, where an example of reporting with integral dead-band supervision is shown. The picture
is simplified: the process is not continuous but the values are evaluated with a time interval of one
execution cycle from each other.
The last value reported, Y1 in figure 216 serves as a basic value for further measurement. A difference
is calculated between the last reported and the newly measured value and is multiplied by the time
increment (discrete integral). The absolute values of these integral values are added until the pre-set
value is exceeded. This occurs with the value Y2 that is reported and set as a new base for the following
measurements (as well as for the values Y3, Y4 and Y5).
The integral dead-band supervision is particularly suitable for monitoring signals with small variations
that can last for relatively long periods.
Y A1 >=
A >= pre-set value A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
(1st) Value
Value Reported Y5
A Reported Value
Reported Value
Y1 Reported
t
IEC99000530 V4 EN-US
The magnitude and angle of the impedance for each phase-to-ground and phase-to-phase loop are
available on local HMI, monitoring tools within PCM600 or to the station level, for example, via IEC
61850.
When the operating current is too low, the impedance measurement can be erroneous. To avoid such
error, minimum operating current will be checked. For phase-earth currents or phase-phase currents
lower than 2% of IBase, the resistance and reactance of the impedance are forced to 99 999 ohm,
corresponding to a magnitude at 141419 (99 999*√2) ohm and an angle at 45 degree.
9.13.2 Identification
GUID-69401D58-00EB-4560-8C35-72AF417E5441 v1
SYMBOL-EE V1 EN-US
Power swings may occur after disconnection of heavy loads or trip of big generation plants.
Power swing detection, blocking and unblocking function (ZMBURPSB (68)) is used to detect power
swings and initiate blocking of all distance protection zones.
Also, fault identification and its classification for various types of fault occurrences during the power
swing are available in the ZMBURPSB function. So, six measuring loops used in each distance
protection zone, if blocked during power swing, can be unblocked/released for distance measurement
depending upon the fault type and thereby, reliable fault clearance can be achieved for faults during
power swing.
It is still possible to inhibit the ZMBURPSB function for ground-fault currents during a power swing
without activating power swing unblocking functionality.
ZMBURPSB (68)
I3P* PICKUP
V3P* ZOUT
BLOCK ZIN
BLK_SS FLTL1
BLK_I0 FLTL2
BLK1PH FLTL3
REL1PH FLT1PH
BLK2PH FLT2PH
REL2PH FLT3PH
I0CHECK PHSEL
TRSP RELCND
EXT_PSD
ANSI19000323 V1 EN-US
9.13.5 Signals
PID-7380-INPUTSIGNALS v2
9.13.6 Settings
PID-7380-SETTINGS v1
The power swing detection, blocking and unblocking (ZMBURPSB ,68) function comprises an inner and
an outer quadrilateral measurement characteristic with load encroachment, as shown in figure 218.
Its principle of operation is based on the measurement of the time it takes for a power swing transient
impedance to pass through the impedance area between the outer and the inner characteristics. The
power swings are identified by transition times longer than a transition time set in corresponding timers.
The impedance measuring principle is the same as that used for the distance protection zones. The
impedance and the characteristic passing times are measured in all three phases separately.
One-out-of-three or two-out-of-three operating modes can be selected according to the specific system
operating conditions.
X1OutFw jX ZL R1LIn
X1InFw D Fw
j
DRv
R1FInRv R1FInFw
D Fw
LdAngle j
LdAngle
DRv
D Fw
D Fw
R
D Fw
DRv
RLdInRv RLdInFw
D Fw
DRv
RLdOutRv RLdOutFw
j D Rv X1InRv
X1OutRv
ANSI05000175-2-en.vsd
ANSI05000175 V2 EN-US
Figure 218: Operating characteristic for ZMBURPSB (68) function (setting parameters in italic)
The impedance measurement within ZMBURPSB (68) function is performed by solving equation 98 and
equation 99 (Typical equations are for phase A, similar equations are applicable for phases B and C).
æVAö
Re ç ÷ £ Rset
è IA ø
EQUATION1557 V1 EN-US (Equation 98)
æVAö
Im ç ÷ £ Xset
è IA ø
EQUATION1558 V1 EN-US (Equation 99)
To avoid load encroachment, the resistive reach is limited in forward direction by setting the parameter
RLdOutFw which is the outer resistive load boundary value while the inner resistive boundary is
calculated according to equation 100.
RLdInFw = kLdRFw·RLdOutFw
EQUATION1185 V2 EN-US (Equation 100)
where:
kLdRFw is a settable multiplication factor less than 1
The slope of the load encroachment inner and outer boundary is defined by setting the parameter
LdAngle.
The load encroachment in the fourth quadrant uses the same settings as in the first quadrant (same
LdAngle and RLdOutFw and calculated value RLdInFw).
The quadrilateral characteristic in the first quadrant is tilted to get a better adaptation to the distance
measuring zones. The angle is the same as the line angle and derived from the setting of the reactive
reach inner boundary X1InFw and the line resistance for the inner boundary R1LIn. The fault resistance
coverage for the inner boundary is set by the parameter R1FInFw.
From the setting parameter RLdOutFw and the calculated value RLdInFw a distance between the inner
and outer boundary, DFw, is calculated. This value is valid for R direction in first and fourth quadrant and
for X direction in first and second quadrant.
To avoid load encroachment in reverse direction, the resistive reach is limited by setting the parameter
RLdOutRv for the outer boundary of the load encroachment zone. The distance to the inner resistive
load boundary RLdInRv is determined by using the setting parameter kLdRRv in equation 101.
RLdInRv = kLdRRv·RLdOutRv
EQUATION1187 V2 EN-US (Equation 101)
where:
kLdRRv is a settable multiplication factor less than 1
From the setting parameter RLdOutRv and the calculated value RLdInRv, a distance between the inner
and outer boundary, DRv, is calculated. This value is valid for R direction in second and third quadrant
and for X direction in third and fourth quadrant.
The inner resistive characteristic in the second quadrant outside the load encroachment part
corresponds to the setting parameter R1FInRv for the inner boundary. The outer boundary is internally
calculated as the sum of DRv+R1FInRv.
The inner resistive characteristic in the third quadrant outside the load encroachment zone consist of the
sum of the settings R1FInRv and the line resistance R1LIn. The angle of the tilted lines outside the load
encroachment is the same as the tilted lines in the first quadrant. The distance between the inner and
outer boundary is the same as for the load encroachment in reverse direction, that is DRv.
The inner characteristic for the reactive reach in forward direction correspond to the setting parameter
X1InFw and the outer boundary is defined as X1InFw + DFw,
where:
DFw = RLdOutFw - KLdRFw · RLdOutFw
The inner characteristic for the reactive reach in reverse direction correspond to the setting parameter
X1InRv for the inner boundary and the outer boundary is defined as X1InRv + DRv.
where:
DRv = RLdOutRv - KLdRRv · RLdOutRv
The operation of the Power swing detection ZMBURPSB (68) is only released if the magnitude of the
current is above the setting of the minimum operating current, IMinPUPG.
• The 1 out of 3 operating mode is based on detection of power swing in any of the three phases.
Figure 219 presents a composition of an internal detection signal DET-A in this particular phase.
• The 2 out of 3 operating mode is based on detection of power swing in at least two out of three
phases. Figure 220 presents a composition of the detection signals DET1of3 and DET2of3.
Signals ZOUT_n (outer boundary) and ZIN_n (inner boundary) in figure 219 are related to the operation
of the impedance measuring elements in each phase separately (n represents the corresponding A, B
and C). They are internal signals, calculated by ZMBURPSB (68) function.
The tP1 timer in figure 219 serve as detection of initial power swings, which are usually not as fast
as the later swings are. The tP2 timer become activated for the detection of the consecutive swings, if
the measured impedance exit the operate area and returns within the time delay, set on the tW waiting
timer. The upper part of figure 219 (internal input signal ZOUT_A, ZIN_A, AND-gates and tP-timers) are
duplicated for phase B and C. All tP1 and tP2 timers in the figure have the same settings.
ZOUTA AND
0-tP1
ZINA 0 OR
-loop
0-tP2
-loop
AND
0
OR DET-A
AND AND
ZOUTB OR
ZOUTC
detected 0
0-tW
ANSI05000113-2-en.vsd
ANSI05000113 V2 EN-US
DET-A
DET-B DET1of3 - int.
OR
DET-C
AND
DET2of3 - int.
AND OR
AND
ANSI01000057-2-en.vsd
ANSI01000057 V2 EN-US
Figure 220: Detection of power swing for 1-of-3 and 2-of-3 operating mode
ZOUT_A ZOUT
OR
ZOUT_B ZIN_A
ZIN
ZOUT_C AND ZIN_B OR
ZIN_C
TRSP 0 AND
0-tGF
I0CHECK
AND 10ms
BLK_I0 0 OR
DET2of3 - int. OR 0
0-tH
REL2PH
AND
BLK2PH OR PICKUP
AND
EXT_PSD
en05000114-1-ansi.vsd
ANSI05000114 V2 EN-US
Figure 221 presents a simplified logic diagram for the Power swing detection function ZMBURPSB
(68). The internal signals DET1of3 and DET2of3 relate to the detailed logic diagrams in figure 219 and
figure 220 respectively.
Selection of the operating mode is possible by the proper configuration of the functional input signals
REL1PH, BLK1PH, REL2PH, and BLK2PH.
The load encroachment characteristic can be switched off by setting the parameter OperationLdCh =
Disabled, but notice that the DFw and DRv will still be calculated from RLdOutFw and RLdOutRv. The
characteristic will in this case be only quadrilateral.
There are four different ways to form the internal INHIBIT signal:
• Logical 1 on functional input BLOCK inhibits the output PICKUP signal instantaneously.
• The INHIBIT internal signal is activated, if the power swing has been detected and the measured
impedance remains within its operate characteristic for the time, which is longer than the time delay
set on tR2 timer. It is possible to disable this condition by connecting the logical 1 signal to the
BLK_SS functional input.
• The INHIBIT internal signal is activated after the time delay, set on tR1 timer, if an ground-fault
appears during the power swing (input IOCHECK is high) and the power swing has been detected
before the ground-fault (activation of the signal I0CHECK). It is possible to disable this condition by
connecting the logical 1 signal to the BLK_I0 functional input.
• The INHIBIT logical signals becomes logical 1, if the functional input I0CHECK appears within the time
delay, set on tGF timer activated by the input signal TRSP and the impedance has been seen within
the outer characteristic of ZMBURPSB (68) operate characteristic in all three phases. This function
prevents the operation of ZMBURPSB (68) function in cases, when the circuit breaker closes onto
persistent single-pole fault after single-pole autoreclosing dead time, if the initial single-pole fault and
single-pole opening of the circuit breaker causes the power swing in the remaining two phases.
Operation of power swing unblocking feature is set to On/Off by a configurable setting parameter
OpModePSU. Power swing unblocking enables reliable phase selection (i.e. accurate selection of faulty
phases) for various types of faults that occur during power swing and keeps healthy phase(s) remain
blocked during power swing.
Filtering GUID-04D2D0B4-98CB-44E0-95A2-955687EB9F76 v1
The calculation of current change criteria (i.e. delta quantities) is implemented from a sample-based
algorithm. The algorithm yields zero changes in currents irrespective of regular load flow and power
swing conditions, while it gives significant changes in currents during power system faults.
Operation of the phase selection element is primarily based on change of current criteria with increased
reliability. There are fault scenarios during power swing where change in current is not detectable. So, a
change in ucosφ (that is, ducosφ, where φ is the impedance angle) based algorithm is also implemented
although it is slow in operation in comparison with the delta current based algorithm. It compliments the
delta current based algorithm.
The phase selection element consists of three phase-to-ground loops and three phase-to-phase
loops which are executed in parallel. Phase-to-phase-ground faults (also called double ground faults)
practically activate phase-to-phase loop for distance measurement.
The internal signal FLTL1E is set high when the following conditions are met:
Since delta quantities exist for a short period, the internal signal, FLTL1E is sealed-in as long as either
negative sequence current is above 12.0% IB or residual current is above 20.0% IB.
or
The above logic is also valid for the remaining two phase-to-ground loops. Output FLT1PH is set to
the logical 1 if any of three phase-to-ground loops detects a fault during power swing. In case of
phase-to-phase-ground on the protected line, no output from the phase-to-ground loops is shown to
avoid overreaching or underreaching of the distance measuring zones.
If the input signal BLOCK is high during the fault period, output FLT1PH is reset to a logical 0.
The internal signal FLTL12 is set high when the following conditions are met:
Since delta quantities exist for a short period, the internal signal, FLTL12 is sealed-in as long as negative
sequence current is above 12.0% IB.
or
The above logic is also valid for the remaining two phase-to-phase loops. Output FLT2PH is set to the
logical 1 if any of three phase-to-phase loops detects a fault during power swing.
If the input signal BLOCK is high during the fault period, output FLT2PH is reset to a logical 0.
The internal signal FLTL12 is set high when the following conditions are met:
Since delta quantities exist for a short period, the internal signal, FLTL12 is sealed-in as long as either
negative sequence current is above 12.0% IB or residual current is above 20.0% IB.
or
The above logic is also valid for the remaining two phase-to-phase loops. Output FLT2PH is set to the
logical 1 if any of three phase-to-phase loops detects a fault during power swing.
If the input signal BLOCK is high during the fault period, output FLT2PH is reset to a logical 0.
Conditions to detect three-phase fault with or without earth connection are as follows:
Output FLT3PH is set high and sealed-in if the rate of change in impedance angle is lower than 5.73 deg
and voltage magnitude in all phases restore above 75.0% UB.
or
Output FLT3PH is set high and sealed-in if the rate of change in impedance angle is lower than 5.73
deg.
or
Detected three-phase fault activates all phase-to-phase loops for distance measurement i.e. output
STCND shows 56.
If the input signal BLOCK is high during the fault period, output FLT3PH is reset to a logical 0.
After the fault detection during power swing, respective loop(s) are released for a distance measuring
zone depending on the fault type. Output STCND is provided to indicate the faulty loop(s) as a binary
coded integer and must be connected to the input ORCND of the ZMF(C)PDIS function. STCND shows
0 if the setting parameter OpModePSU is set to Off.
Code build up for the output STCND to release the measuring fault loops is as follows:
Also, outputs FLTL1, FLTL2 and FLTL3 are shown to indicate the faulty phases during power swing. The
logical diagram of the phase selection logic implemented in ZMBURPSB is depicted in Figure 222.
BLOCK
FLTL12
&
FLTL23
&
FLT2PH
FLTL31 1
&
FLTL1E
&
&
FLTL2E
& FLT1PH
& 1
FLTL3E
&
&
Bit to word
FLT3PH
b0
&
1 b1
STCND
b2
b3
b4
1 b5
1
FLTL1
1
FLTL2
1
FLTL3
1
IEC19000324 V1 EN-US
Figure 223 shows the releasing condition for a distance measuring zone. Output RELCND is provided
based on the power swing condition as a binary coded integer and it must be connected to the input
RELCNDZx (where x = 1, 2, 3…) of the ZMF(C)PDIS function.
START
&
OpModePSU
STCND RELCND
T
63 F
IEC19000325 V1 EN-US
Figure 223: Logical diagram of a releasing logic for distance protection function
If the setting parameter OpModePSU is set to On and the output START (i.e. power swing is detection)
is high, RELCND indicates the faulty loop(s) information for the power system faults during power swing
and releases the measuring loops for faults.
If either the setting parameter OpModePSU is set to Off or the output START (no power swing detection)
is low, RELCND indicates 63, i.e. all six loops are released for distance measuring. It means that no
phase selection is performed inside the ZMBURPSB function. However, phase selection is performed in
ZMF(C)PDIS function to release the distance measuring loop for distance measurement.
Usage of outputs START, STCND and RELCND of the ZMBURPSB function together with
ZMF(C)PDIS function to achieve power swing blocking and unblocking features is explained
in the Application manual.
Power swing detection trip time (0.000-60.000) s ±0.2% or ±10 ms whichever is greater
Second swing reclaim trip time (0.000-60.000) s ±0.2% or ±20 ms whichever is greater
Minimum trip current, Ph-E (5-1000)% of IBase ±1.0% of In
9.14.2 Identification
SEMOD155890-2 v4
Automatic switch onto fault logic ZCVPSOF is a function that gives an instantaneous trip when closing
the breaker onto a fault. A dead-line detection check is provided to activate ZCVPSOF when the line is
de-energized.
Mho distance protections cannot operate for switch onto fault conditions when the phase voltages are
close to zero. An additional logic based on VI Level is used for this purpose.
ZCVPSOF is a complementary function to the distance protection function. It is enabled for operation
either by the closing command to the circuit breaker (normally closed auxiliary contact of the circuit
breaker) to the BC input or automatically by the dead-line detection. Once enabled, it remains active
for tSOTF duration after the enabling signal is reset. The protection function can be enabled for
tripping during the activated time by connecting the functions included in the terminal to the ZACC
input. Therefore, the pickup of the selected protection functions connected to ZACC during the enabled
condition results in an immediate TRIP output from the function.
ZCVPSOF
I3P* TRIP
V3P*
BLOCK
START_DLYD
BC
ZACC
ANSI06000459-3-en.vsdx
ANSI06000459 V3 EN-US
PID-3875-INPUTSIGNALS v11
PID-3875-SETTINGS v11
The automatic switch onto fault logic ZCVPSOF can be activated externally (by the breaker-closed input)
or internally (automatically) with the dead-line detection using the VI level-based logic. When the setting
AutoInitMode is DLD disabled, ZCVPSOF is activated by an external binary input BC. When the setting
AutoInitMode is set to Voltage, Current or Current & Voltage modes, ZCVPSOF is activated by the
dead-line detection.
The activation from the dead-line detection function is released if the internal signal DeadLine from
the UILevel Detector function is activated at the same time as the inputs ZACC and START_DLYD are
not activated at least for the duration of tDLD. The internal signal DeadLine from the UILevel Detector
function is activated under any of the following conditions:
• If all three-phase currents are below the setting IPh< and the AutoInitMode setting is set to Current
• If all three-phase voltages are below the setting UPh< and the AutoInitMode setting is set to Voltage
• If all three-phase currents and voltages are below the settings IPh< and UPh< and the AutoInitMode
setting is set to Current & Voltage
Once the dead line drops off after energization or once BC drops off, the activated signal is extended for
the duration of tSOTF.
The internal signal SOTFUILevel is activated if the phase voltage is below the set UPh< and the
corresponding phase current is above the set IPh< for a time longer than the duration set by tDuration.
To get the TRIP signal, one of the different operate modes must also be selected with the Mode
parameter:
• Mode = Impedance; TRIP is released if either the ZACC input (connected normally to a nondirectional
distance protection start zone) or the START_DLYD input is activated. If START_DLD is activated, TRIP
is released after a delay of tOperate.
• Mode = UILevel; TRIP is released if UILevel detector is activated
• Mode = UILvl&Imp; TRIP is released based either on the impedance-measured criteria or UILevel
detection
The measured phase voltages and currents are provided as service values.
BLOCK
AND 0 TRIP
15
BC
AutiInit=On
OR 0
ZACC AND 200
0 1000
IL1
deadLine
IL2
IL3
VA VILevel detector
VB
VC
IphPickup
SOTFVILevel
VphPickup
AND
Mode = Impedance
AND OR
Mode = UILevel
OR
AND
Mode = UILvl&Imp
en07000084_ansi.vsd
ANSI07000084 V1 EN-US
Figure 225: Simplified logic diagram for Automatic switch onto fault logic
M16043-1 v14
9.15.2 Identification
SEMOD175682-2 v3
Power Swing Logic (PSLPSCH) provides possibility for selective tripping of faults on power lines during
system oscillations (power swings or pole slips), when the distance protection function should normally
be blocked. The complete logic consists of two different parts:
• Communication and tripping part: provides selective tripping on the basis of special distance protection
zones and a scheme communication logic, which are not blocked during the system oscillations.
• Blocking part: blocks unwanted operation of instantaneous distance protection zone 1 for oscillations,
which are initiated by faults and their clearing on the adjacent power lines and other primary elements.
PSLPSCH
BLOCK TRIP
STZMUR STZMURPS
STZMOR BLKZMUR
STPSD BLKZMOR
STDEF CS
STZMPSD
CACC
AR1P1
CSUR
CR
ANSI07000026-3-en.vsd
ANSI07000026 V3 EN-US
9.15.5 Signals
PID-3664-INPUTSIGNALS v7
9.15.6 Settings
PID-3664-SETTINGS v6
Communication and tripping logic as used by the power swing distance protection zones is
schematically presented in figure 227.
PUDOG
AR1P1 AND
PUPSD
CS
BLOCK AND 0-tCS AND
0
CSUR
BLKZMUR
AND
0
0-tTrip 0-tBlkTr
0
PLTR_CRD TRIP
OR
CR AND
en06000236_ansi.en
ANSI06000236 V1 EN-US
Figure 227: Simplified logic diagram – power swing communication and tripping logic
The complete logic remains blocked as long as there is a logical one on the BLOCK functional input
signal. Presence of the logical one on the PUDOG functional input signal also blocks the logic as long
as this block is not released by the logical one on the AR1P1 functional input signal. The functional
output signal BLKZMUR remains logical one as long as the function is not blocked externally (BLOCK
is logical zero) and the ground-fault is detected on protected line (PUDOG is logical one), which is
connected in three-phase mode (AR1P1 is logical zero). Timer tBlkTr prolongs the duration of this
blocking condition, if the measured impedance remains within the operate area of the Power Swing
Detection (ZMRPSB, 68) function (PUPSD input active). The BLKZMUR can be used to block the
operation of the power-swing zones.
Logical one on functional input CSUR, which is normally connected to the TRIP functional output of a
power swing carrier sending zone, activates functional output CS, if the function is not blocked by one of
the above conditions. It also activates the TRIP functional output.
Initiation of the CS functional output is possible only, if the PUPSD input has been active longer than the
time delay set on the security timer tCS.
Simultaneous presence of the functional input signals CACC and CR (local trip condition) also activates
the TRIP functional output, if the function is not blocked by one of the above conditions and the PUPSD
signal has been present longer then the time delay set on the trip timer tTrip.
Figure 228 presents the logical circuits, which control the operation of the underreaching zone (zone 1)
at power swings, caused by the faults and their clearance on the remote power lines.
AND
BLKZMOR
AND
PUZMUR
PUZMURPS
BLOCK AND 0-tZL OR
0 AND
PUZMOR
PUZMPSD AND 0-tDZ
0 OR
PUPSD
AND
-loop
en06000237_ansi.vsd
ANSI06000237 V1 EN-US
Figure 228: Control of underreaching distance protection (Zone 1) at power swings caused by the faults and their clearance
on adjacent lines and other system elements
The logic is disabled by a logical one on functional input BLOCK. It can start only if the following
conditions are simultaneously fulfilled:
• PUPSD functional input signal must be a logical zero. This means, that Power swing detection
(ZMRPSB, 68) function must not detect power swinging over the protected power line.
• PUZMPSD functional input must be a logical one. This means that the impedance must be detected
within the external boundary of ZMRPSB (68) function.
• PUZMOR functional input must be a logical one. This means that the fault must be detected by the
overreaching distance protection zone, for example zone 2.
The PUZMURPS functional output, which can be used in complete terminal logic instead of a normal
distance protection zone 1, becomes active under the following conditions:
• If the PUZMUR signal appears at the same time as the PUZMOR or if it appears with a time delay,
which is shorter than the time delay set on timer tDZ.
• If the PUZMUR signal appears after the PUZMOR signal with a time delay longer than the delay set on
the tDZ timer, and remains active longer than the time delay set on the tZL timer.
The functional output signal can be used to block the operation of the higher distance protection zone, if
the fault has moved into the zone 1 operate area after tDZ time delay.
SEMOD171935-5 v5
9.16.1 Identification
SEMOD158949-2 v4
9.16.2 Functionality
SEMOD143246-17 v7
Sudden events in an electric power system such as large changes in load, fault occurrence or fault
clearance, can cause power oscillations referred to as power swings. In a non-recoverable situation, the
power swings become so severe that the synchronism is lost, a condition referred to as pole slipping.
The main purpose of the pole slip protection (PSPPPAM ,78) is to detect, evaluate, and take the
required action for pole slipping occurrences in the power system.
PSPPPAM (78)
I3P* TRIP
V3P* TRIP1
BLOCK TRIP2
BLKGEN PICKUP
BLKMOTOR ZONE1
EXTZONE1 ZONE2
GEN
MOTOR
SFREQ
SLIPZOHM
SLIPZPER
VCOS
VCOSPER
ANSI10000045-1-en.vsd
ANSI10000045 V1 EN-US
9.16.4 Signals
PID-3526-INPUTSIGNALS v3
9.16.5 Settings
PID-3526-SETTINGS v4
The value of StartAngle and TripAngle should always be set equal to or below 170 degree.
The angles values above 170 degree will be treated as 170 degree.
If the generator is faster than the power system, the rotor movement in the impedance and voltage
diagram is from right to left and generating is signaled. If the generator is slower than the power system,
the rotor movement is from left to right and motoring is signaled (the power system drives the generator
as if it were a motor).
The movements in the impedance plane can be seen in Figure 230. The transient behavior is described
by the transient EMF's EA and EB, and by X'd, XT and the transient system impedance ZS.
Zone 1 Zone 2
EB X’d XT XS EA
IED
B A
jX
XS
Pole slip
impedance XT
d Apparent generator
movement impedance R
X’d
IEC06000437_2_en.vsd
IEC06000437 V2 EN-US
where:
X'd = transient reactance of the generator
XT = short-circuit reactance of the unit step-up transformer
ZS = impedance of the power system A
• the minimum current exceeds 0.10 IN (IN is IBase parameter set under general setting).
• the maximum voltage falls below 0.92 VBase
• the voltage Ucosφ (the voltage in phase with the generator current) has an angular velocity of 0.2...8
Hz and
• the corresponding direction is not blocked.
en07000004.vsd
IEC07000004 V1 EN-US
Figure 231: Different generator quantities as function of the angle between the equivalent generators
An alarm is given when movement of the rotor is detected and the rotor angle exceeds the angle set for
'WarnAngle'.
When the impedance crosses the slip line between ZB and ZC it counts as being in zone 1 and between
ZC and ZA in zone 2. The entire distance ZA-ZB becomes zone 1 when signal EXTZONE1 is high
(external device detects the direction of the centre of slipping).
After the first slip, the signals ZONE1 or ZONE2 and – depending on the direction of slip - either GEN or
MOTOR are issued.
Every time pole slipping is detected, the impedance of the point where the slip line is crossed and the
instantaneous slip frequency are displayed as measurements.
Further slips are only detected, if they are in the same direction and if the rate of rotor movement has
reduced in relation to the preceding slip or the slip line is crossed in the opposite direction outside
ZA-ZB. A further slip in the opposite direction within ZA-ZB resets all the signals and is then signalled
itself as a first slip.
The TRIP1 tripping command and signal are generated after N1 slips in zone 1, providing the rotor angle
is less than TripAngle. The TRIP2 signal is generated after N2 slips in zone 2, providing the rotor angle
is less than TripAngle.
PICKUP
AND
0.2 Slip.Freq. 8 Hz
startAngle
ZONE1
AND
Z cross line ZC - ZB
ZONE2
AND
Z cross line ZA - ZC
Counter
a
ab
N1Limit b TRIP1
AND
tripAngle OR
TRIP
Counter
a
ab
N2Limit b TRIP2
AND
ANSI07000005.vsd
ANSI07000005 V2 EN-US
Figure 232: Simplified logic diagram for pole slip protection PSPPPAM (78)
GUID-88E02516-1BFE-4075-BEEB-027484814697 v2
9.17.1 Identification
GUID-BF2F1533-BA39-48F0-A55C-0B13A393F780 v2
<
The out-of-step protection (OOSPPAM (78)) function in the IED can be used for both generator
protection and as well for line protection applications.
The main purpose of the OOSPPAM (78) function is to detect, evaluate, and take the required action
during pole slipping occurrences in the power system.
The OOSPPAM (78) function detects pole slip conditions and trips the generator as fast as possible,
after the first pole-slip if the center of oscillation is found to be in zone 1, which normally includes the
generator and its step-up power transformer. If the center of oscillation is found to be further out in the
power system, in zone 2, more than one pole-slip is usually allowed before the generator-transformer
unit is disconnected. A parameter setting is available to take into account the circuit breaker opening
time. If there are several out-of-step relays in the power system, then the one which finds the center of
oscillation in its zone 1 should operate first.
Two current channels I3P1 and I3P2 are available in OOSPPAM function to allow the direct connection
of two groups of three-phase currents; that may be needed for very powerful generators, with stator
windings split into two groups per phase, when each group is equipped with current transformers. The
protection function performs a simple summation of the currents of the two channels I3P1 and I3P2.
OOSPPAM (78)
I3P1* TRIP
I3P2* TRIPZ1
V3P* TRIPZ2
BLOCK PICKUP
BLKGEN GENMODE
BLKMOT MOTMODE
EXTZ1 R
X
SLIPFREQ
ROTORANG
VCOSPHI
ANSI14000055-1-en.vsd
ANSI12000188 V2 EN-US
9.17.4 Signals
PID-3539-INPUTSIGNALS v10
9.17.5 Settings
PID-3539-SETTINGS v10
General
Under balanced and stable conditions, a generator operates with a constant rotor angle (power angle),
delivering active electrical power to the power system, which is approximately equal to the input
mechanical power on the generator axis.The currents and voltages are constant and stable. An out-of-
step condition is characterized by periodic changes in the rotor angle, that leads to a wild flow of the
synchronizing power; so there are also periodic changes of rotational speed, currents and voltages.
When displayed in the complex impedance plane, these changes are characterized by a cyclic change
in the complex load impedance Z(R, X) as measured at the terminals of the generator, or at the location
of the instrument transformers of a power line connecting two power subsystems. This is shown in
Figure 234.
1.5 ¬ trajectory
of Z(R, X)
to the 3rd
The 2nd pole-slip
1 The 1st X in Ohms
pole slip
pole slip
occurred Pre-disturbance
occurred
RE normal load
- - - - -
Imaginary part (X) of Z in Ohms
- - - - ----------- - - - - Z(R, X)
0.5 - 3 ----- ---- --
Zone 2 -- --- 2 1 ---- - 0
- -- -
- ---- - -
- -
^ -^ ^ ^ ^ -^ ^ ^ ^ ^ ^ ^ - - -
- -- ^ --^- ^ ^ ^ --^
Zone 1 - --- - -
0 - - -- -
- -- relay
- --
- -
- -- -- - R in Ohms
limit of reach® - -- - -
-
-- --
--- ---- -
-
-
lens determined - - ® ---- ------ -
0- -® pre-disturbance Z(R, X)
- -
-0.5 by the setting - - - - -------- - - - - -
1 ® Z(R, X) under 3-phase fault
Pickup Angle = 120° SE
2 ® Z(R, X) when fault cleared
3® Z when pole-slip declared
-1
-1.5 -1 -0.5 0 0.5 1 1.5
Real part (R) of Z in Ohms
ANSI10000109-1-en.vsd
ANSI10000109 V1 EN-US
Figure 234: Loci of the complex impedance Z(R, X) for a typical case of generator losing step after a short circuit that was
not cleared fast enough
Under typical, normal load conditions, when the protected generator supplies the active and the reactive
power to the power system, the complex impedance Z(R, X) is in the 1st quadrant, point 0 in Figure
234. One can see that under a three-phase fault conditions, the centre of oscillation is at the point of
fault, point 1, which is logical, as all three voltages are zero or near zero at that point. Under the fault
conditions the generator accelerated and when the fault was finally cleared, the complex impedance
Z(R, X) jumped to the point 2. By that time, the generator has already lost its step, Z(R, X) continues
its way from the right-hand side to the left-hand side, and the 1st pole-slip cannot be avoided. If the
generator is not immediately disconnected, it will continue pole-slipping — see Figure 234, where two
pole-slips (two pole-slip cycles) are shown. Under out-of-step conditions, the centre of oscillation is
where the locus of the complex impedance Z(R, X) crosses the (impedance) line connecting the points
SE (Sending End), and RE (Receiving End). The point on the SE – RE line where the trajectory of Z(R,
X) crosses the impedance line can change with time and is mainly a function of the internal induced
voltages at both ends of the equivalent two-machine system, that is, at points SE and RE.
Measurement of the magnitude, direction and rate-of-change of load impedance relative to a generator’s
terminals provides a convenient and generally reliable means of detecting whether machines are out-of-
step and pole-slipping is taking place. Measurement of the rotor (power) angle δ is important as well.
Rotor (power) angle δ can be thought of as the angle between the two lines, connecting point 0 in
Figure 234, that is, Z(R, X) under normal load, with the points SE and RE, respectively. These two lines
are not shown in Figure 234. Normal values of the power angle, that is, under stable, steady-state,
load conditions, are from 30 to 60 electrical degrees. It can be observed in Figure 235 that the angle
reaches 180 degrees when the complex impedance Z(R, X) crosses the impedance line SE – RE. It then
changes the sign, and continues from -180 degrees to 0 degrees, and so on. Figure 235 shows the rotor
(power) angle and the magnitude of Z(R, X) against time for the case from Figure 234.
4
|Z| in Ohms
rotor (power)
3 normal angle in rad
angle
Impe dance Z in Ohm and rotor a ngle in radian ® load
Z(R, X) unde r fa ult lies |Z|
2
on the impe dance line
or nea r (for 3-ph faults )
1
0
0
fault 500 ms
-1 fa ult
occ urrs
Unde r 3-pha s e fa ult
condition rotor a ngle 3
-2
of a pp. ±180 de gre e s
is m e a s ure d ...
2
-3 Z(R,X) cros s e d
1 1 the im pe da nce line , Z-line ,
conne cting points S E - RE
-4
0 200 400 600 800 1000 1200 1400
Time in millis econds ®
IEC10000110-2-en.vsd
IEC10000110 V2 EN-US
Figure 235: Rotor (power) angle and magnitude of the complex impedance Z(R, X) against the time
In order to be able to fully understand the principles of OOSPPAM (78), a stable case, that is, a case
where the disturbance does not make a generator to go out-of-step, must be shown.
1
SE RE
G X [Ohm]
0.8 Z(R,X) 20 ms
fault
relay after line out
- - - RE - - -
0.6 - - -- -
-- ---- ----- 4 - - pre-fault
Imaginary part (X) of Z in Ohms →
--- ---
zone 2 - - -- -
-- --- - Z(R,X)
0.4 - ---- --- 2 -
- -
-- -- -1 5
- --- fault→ --- -
X-line → ^ -^ ^ ^ ^ ---^ ^ 3 - -
0.2 - -- ^ ^ ^ ^ ^ ^ ---^- ^ ^ -
- --- Z-line→ -- ^ -^ 0
-
- --
-- --- - 6
0 - -- --- -
- -- -
- - R
limit of - -- relay lens → -- -- -
--
-0.2 reach - --
--- 110° ---- -
zone 1- - -- --- -
-
- --- - - -
-- --- ---
-0.4
- - ----------
---
- --
- - - - -
-0.6 SE - - -
0 → pre-fault Z(R, X)
this circle forms 3 → Z(R, X) under fault
-0.8 the right-hand side 5 → Z 20 ms after line out
edge of the lens 6 → pow er line reclosed
-1
-1 -0.5 0 0.5 1 1.5
Real part (R) of Z in Ohms → ANSI10000111-1-en.vsd
ANSI10000111 V1 EN-US
Figure 236: A stable case where the disturbance does not make the generator to go out-of-step
It shall be observed that for a stable case, as shown in Figure 236, where the disturbance does not
cause the generator to lose step, the complex impedance Z(R, X) exits the lens characteristic on the
same side (point 4) it entered it (point 2), and never re-enters the lens. In a stable case, where the
protected generator remains in synchronism, the complex impedance returns to quadrant 1, and, after
the oscillations fade, it returns to the initial normal load position (point 0), or near.
A precondition in order to be able to construct a suitable lens characteristic is that the power system
in which OOSPPAM (78) is installed, is modeled as a two-machine equivalent system, or as a single
machine – infinite bus equivalent power system. Then the impedances from the position of OOSPPAM
(78) in the direction of the normal load flow (that is from the measurement point to the remote system)
can be taken as forward. The lens characteristic, as shown in Figure234 and Figure236, is obtained
so that two equal in size but differently offset Mho characteristics are set to overlap. The resultant lens
characteristic is the loci of complex impedance Z(R, X) for which the rotor (power) angle is constant,
for example 110 degrees or 120 degrees; if the rotor (power) angle approaches this value, then there
is a high risk to have an out of step condition. The limit-of- reach circle is constructed automatically
by the algorithm; it is about 10% wider than the the circle that has the line SE-RE as diameter (that is
the out-of-step characteristic which corresponds to the rotor (power) angle of 90 degrees). Figure 237
illustrates construction of the lens characteristic for a power system.
X
Position of the OOS
- - - RE - - -
0.6 - - --- - relay is the origin of
- - -- ---- - the R - X plane
- - - -
- --- Ze --
-- -
- Zone 2 -- -- -
0.4 X-line - - -- -- -
- --
- --- -
determined -- Zline
- - -- -
by the ® ^ ^- ^ -
- --
0.2 ^ ^ ^-- ^ - -
setting - ^ ^ ^ ^ -
Imaginary part (X) of Z in Ohms
- ^ ^ ^ --- ^ -
---
ReachZ1 - -- -- ^ ^ ^-
Ztr
- --
- -- - R
0 - Zone 1 -- --
- -
-- relay -
- -- 120° -- Z(R,X) -
- -- --
- -
- -- ¬ Z-line -- -
-0.2 - Zgen -
- -- -- -
limit-of-reach® - -- --
-- - --¬ Lens is -the locus
circle depends on- -- - -
-0.4 - -- --- of constant
- rotor (power)
the position of the - --
- - ---- angle, - e.g. 120°.
- - --- - -
points SE and RE - - - - - - - - - Lens' width determined
SE
-0.6 by the setting Pickup Angle
SE RE
ANSI10000113-1-en.vsd
ANSI10000113 V1 EN-US
To be able to automatically construct the lens characteristic for a system shown in Figure 238, the
actual power system must be modeled as a two-machine equivalent system, or as a single machine
– infinite bus equivalent system, the following information is necessary: Zgen(Rgen, Xgen), Ztr(Rtr,
Xtr), Zline(Rline, Xline), Zeq(Req, Xeq), and the setting PickupAngle, for example 120 degrees. All
impedances must be referred to the voltage level where the out-of-step protection relay is placed; in
the case shown in Figure 238 the relay is connected to the terminals of the generator and, therefore,
the previous quantities shall be referred to the generator nominal voltage and nominal current. The
impedances from the position of the out-of-step protection in the direction of the normal load flow can be
taken as forward.
The out-of-step relay, as in Figure 238 looks into the system and the impedances in that direction are
forward impedances:
Resistances are much smaller than reactances, but in general can not be neglected. The ratio
(ForwardX + ReverseX) / (ForwardR + ReverseR) determines the inclination of the Z-line, connecting
the point SE (Sending End) and RE (Receiving End), and is typically approximately 85 degrees. While
the length of the Z-line depends on the values of ForwardX, ReverseX, ForwardR, and ReverseR, the
width of the lens is a function of the setting PickupAngle.The lens is broader for smaller values of the
PickupAngle, and becomes a circle for PickupAngle = 90 degrees.
When the complex impedance Z(R, X) enters the lens, pole slipping is imminent, and a pickup signal
is issued. The angle recommended to form the lens is 110 or 120 degrees, because it is this rotor
(power) angle where problems with dynamic stability usually begin. Rotor (power) angle 120 degrees
is sometimes called “the angle of no return” because if this angle is reached under generator power
swings, the generator is most likely to lose step.
An out-of-step condition is characterized by periodic changes of the rotor angle, that leads to a wild
flow of the synchronizing power; so there are also periodic changes of rotational speed, currents and
voltages. When displayed in the complex impedance plane, these changes are characterized by a cyclic
change in the complex load impedance Z(R, X) as measured at the terminals of the generator, or at
the location of the instrument transformers of a power line connecting two power sub-systems. This
was shown in Figure 234. When a synchronous machine is out-of-step, pole-slips occur. To recognize a
pole-slip, the complex impedance Z(R,X) must traverse the lens from right to left in case of a generator
and in the opposite direction in case of a motor. Another requirement is that the travel across the lens
takes no less than a specific minimum traverse time, typically 40...60 milliseconds. The above timing
is used to discriminate a fault from an out-of-step condition. In Figure 234, some important points on
the trajectory of Z(R, X) are designated. Point 0: the pre-fault, normal load Z(R, X). Point 1: impedance
Z under a three-phase fault with low fault resistance: Z lies practically on, or very near, the Z-line.
Transition of the measured Z from point 0 to point 1 takes app. 20 ms, due to Fourier filters. Point 2:
Z immediately after the fault has been cleared. Transition of the measured Z from point 1 to point 2
takes approximately 20 ms, due to Fourier filters. The complex impedance then travels in the direction
from the right to the left, and exits the lens on the opposite side. When the complex impedance exits
the lens on the side opposite to its entrance, the 1st pole-slip has already occurred and more pole-slips
can be expected if the generator is not disconnected. Figure 234 shows two pole-slips. Figures like
Figure 234 and Figure 236 are always possible to draw by means of the analog output data from the
pole-slip function, and are of great help with eventual investigations of the performance of the out-of-step
function.
A pole-slip may be detected if it has a slip frequency lower than a maximum value fsMax. The specific
value of fsMax depends on the setting (parameter) PickupAngle (which determines the width of the
lens characteristic). A parameter in this calculation routine is the value of the minimum traverse time,
traverseTimeMin. The minimum traverse time is the minimum time that the travel of the complex
impedance Z(R, X) through the lens, from one side to the other, must last in order to recognize that
a pole-slip has occurred. The value of the internal constant traverseTimeMin is a function of the set
PickupAngle.For values of PickupAngle <= 110°, traverseTimeMin = 50 ms. For values PickupAngle >
110°, traverseTimeMin = 40 ms. The expression which relates the maximum slip frequency fsMax and
the traverseTimeMin is as follows:
The minimum value of fsMax is 6.994 Hz. When PickupAngle = 110 degrees, fsMax = 7.777 Hz. This
implies, that the default PickupAngle = 110 degrees covers 90% of cases as, the typical final slip
frequency is between 2 - 5Hz. In practice, however, before the slip frequency, for example 7.777 Hz,
is reached, at least three pole-slips have occurred. In other words, if we consider a linear increase
of frequency from 50 Hz to 57.777 Hz, at least three pole-slips will occur (in fact: (57.777 - 50) / 2 =
3.889). The exact instantaneous slip-frequency expressed in Hz (corresponding to number of pole slips
per second) is difficult to calculate. The easiest and most exact method is to measure time between
two successive pole slips. This means that, the instantaneous slip-frequency is measured only after
the second pole-slip, if the protected machine is not already disconnected after the first pole-slip. The
measured value of slipsPerSecond (SLIPFREQ) is equal to the average slip-frequency of the machine
between the last two successive pole-slips.
Although out-of-step events are relatively rare, the out-of-step protection should take care of the circuit
breaker health. The electromechanical stress to which the breaker is exposed shall be minimized. The
maximum currents flowing under out-of-step conditions can be even greater that those for a three-phase
short circuit on generator terminals; see Figure 240. The currents flowing are highest at rotor angle 180
degrees, and smallest at 0 degrees, where relatively small currents flow. To open the circuit breaker at
180 degrees, when not only the currents are highest, but the two internal (that is, induced) voltages at
both ends are in opposition, could be fatal for the circuit breaker. There are two methods available in
order to minimize the stress; the second method is more advanced than the first one.
X[Ohm]
0.6 trip RE - Receiving End (infinite bus)
region
loci of Z(R, X)
Imaginary part (X) of Z in Ohms → 0.4 3
no trip
region 1
here rotor here
0.2 2
angle rotor angle
is -90° no trip is +90°
rotor angle
region
= ±180°
0 no trip
relay
region R[Ohm]
inside ← Z - line connects
points SE & RE
-0.2 circle
← this circle
is loci of
outside the
the rotor
-0.4 circle is the trip
angle = 90°
region for
TripAngle <= 90° SE - Sending End (generator)
Figure 239: The imaginary offset Mho circle represents loci of the impedance Z(R, X) for which the rotor angle is 90 degrees
35
very high currents due
Current in kA, trip command to CB, rotor angle in rad →
← rotor angle
0
angle towards 0°
-5
0 200 400 600 800 1000 1200
Time in milliseconds →
IEC10000115-1-en.vsd
IEC10000115 V1 EN-US
Figure 240: Trip initiation when the break-time of the circuit breaker is known
At every execution of the function the following is calculated: active power P, reactive power Q, rotor
angle ROTORANG, quantity UCOSPHI, the positive-sequence current CURRENT and voltage VOLTAGE. All
other quantities, that can as well be read as outputs, are only calculated if the Z(R, X) enters the limit of
reach zone, which is a circle in the complex (R – X) plane. When the complex impedance Z(R, X) enters
the limit-of-reach region, the algorithm:
• determines in which direction the impedance Z moves, that is, the direction the lens is traversed
• measures the time taken to traverse the lens from one side to the other one
If the traverse time is more than the limit 40 or 50 ms, a pole-slip is declared. If the complex impedance
Z(R, X) exits the lens on the same side it entered, then it is a stable case and the protected machine
is still in synchronism. If a pole-slip has been detected, then it is determined in which zone the centre
of oscillation is located. If the number of actual pole-slips exceeds the maximum number of allowed
pole-slips in either of the zones, a trip command is issued taking care of the circuit breaker safety.
R R
UPSRE Calculation of X X
UPSIM R and X parts
of the complex Z(R,X)
UPSMAG
positive-
IPSRE
sequence Z(R,X) NO
IPSIM
impedance within limit of Return
Z(R, X) reach?
YES UCOSPHI
Z(R,X) ROTORANG
within lens NO
Function alert
characteristic?
SLIPFREQ
YES GENMODE
Z(R,X) MOTMODE
LEFT Z(R,X) RIGHT NO
exited lens
entered lens
on the left- hand
from?
Motor losing Generator losing side?
step ? step ?
YES
Was
traverse time NO
more than
Calculation of 50 ms?
P
positive- sequence YES (pole- slip!)
active power P, Q TRIP
>= 1
reactive power Q, Number
ZONE 2 NO
rotor angle UCOSPHI
of pole- slips
ROTORANG exceeded in TRIPZ1
a zone? Open
and
ROTORANG circuit
UCOSPHI ZONE 1 TRIPZ2
breaker
safely
IEC10000116-3-en.vsd
IEC10000116 V3 EN-US
9.18.2 Identification
SEMOD151937-2 v2
The Phase preference logic function PPLPHIZ is intended to be used in isolated or high impedance
grounded networks where there is a requirement to trip on only one of the faulty lines during a cross-
country fault. It can be used without preference to restrain trip for single ground faults with a delayed
zero-sequence current release for cable networks grounded using a resistor.
For cross-country faults, the logic selects either the leading or lagging phase-ground loop for
measurement. It initiates trip on the preferred phase based on the selected phase preference scheme. A
number of different phase preference schemes are available.
PPLPHIZ provides an additional phase selection criteria, namely under voltage criteria, suitable for
phase selection during cross-country faults. In radial networks, where there is no fault current in the
phase with the external fault, current or impedance based phase selection methods become ineffective.
Hence, only voltage can be used for phase selection. The phase selection result will be the same for
all bays on a bus since the voltage is the same, which is an important condition for tripping with phase
preference.
In meshed and stronger networks, it may be difficult to find appropriate under-voltage settings for phase
selection. Therefore an automatic phase selection logic is made available which works in parallel with
a set under-voltage criterion in order to detect the two faulty phases even for complex networks. If for
any reason the PPLPHIZ is unable to detect the two faulty phases, then after a short time delay all three
phase-to-earth loops of the distance protection will be released for operation. The final result might be
that both faulty feeders are disconnected. In other words, protection operation is prioritized over strict
adherence to preference.
During a cross-country fault, both fault locations are in front of the distance protection. The measured
residual current magnitude can be quite small. The PPLPHIZ function has built-in logic that can detect
such a condition and properly release the preferred phase-to-ground loop.
PPLPHIZ
I3P* BFI_3P
V3P* ZREL
BLOCK
RELAG
RELBG
RELCG
PHSEL
ANSI07000029-2-en.vsd
ANSI07000029 V2 EN-US
PID-8030-INPUTSIGNALS v1
PID-8030-SETTINGS v1
PPLPHIZ is connected between the Distance protection zones ZMQPDIS and ZMQAPDIS and Phase
selection FDPSPDIS, see Figure 243. Depending on the setting, the original phase selection will be
supplemented with an additional voltage based phase selection inside PPLPHIZ and then filtered
through the phase preference logic in order to release only the preferred phases of the distance zones.
ZMQAPDIS (21)
FDPSPDIS (21)
W2_CT_B_I3P I3P* TRIP
I3P* TRIP
W2_VT_B_v3P V3P* TR_A
V3P* BFI
FALSE BLOCK TR_B
BLOCK FWD_A PHS_L1 W2_FSD1-BLKZ LOVBZ TR_C
DIRCND FWD_B PHS_L2 FALSE BLKTR PICKUP
FWD_C PHS_L3 PHSEL PU_A
FWD_G
DIRCND PU_B
REV_A
PU_C
REV_B
PHPUND
REV_C
REV_G
NDIR_A ZMQPDIS (21)
NDIR_B
W2_CT_B_I3P I3P* TRIP
NDIR_C
W2_VT_B_v3P V3P* TR_A
NDIR_G FALSE BLOCK TR_B
FWD_1PH TR_C
W2_FSD1-BLKZ LOVBZ
FWD_2PH PICKUP
FALSE BLKTR
FWD_3PH
PHSEL PU_A
PHG_FLT
DIRCND PU_B
PHPH_FLT
PU_C
PHSELZ PHPUND
DLECND
PPLPHIZ
W2_CT_B_I3P I3P* BFI_3P
W2_VT_B_V3P V3P* ZREL
FALSE BLOCK
FALSE RELAG
FALSE RELBG
FALSE RELCG
PHSEL
ANSI06000552-2-en.vsd
ANSI06000552 V2 EN-US
The fundamental pickup criterion for a cross-country fault is a continuous residual current (3I0) above
setting level Pickup_N.
Transient residual currents associated with single phase fault inception are not allowed to release the
distance protection. This is taken care of by a time-on-delay tIN, which should be set longer than the
expected duration of the transient. This time delay can be bypassed if the magnitude of the residual
current exceeds the set high level Pickup.
If a single phase fault remains for some time, it is possible to bypass the tIN time delay, since the
next fault event is expected to be a cross-country fault. The criterion for this bypass is that the residual
voltage is greater than setting level 3V0PU for a time longer than setting tVN. The time-off-delay tOffVN
is used to make sure that the bypass is steady during the cross-country fault.
The time delay for residual current pickup is also bypassed as soon as two low voltages are detected
during the cross-country fault (startUPP). See Figure 244 for a simplified diagram showing the residual
current start logic.
tIN
a
Pickup_N b AND t
pickupIN
OR
IN a
maxPhCurrent b OR
AND
INStartFulfilled
I3P OR
Max(lL1, IL2, IL3) AND
X
kINStab
a
Pickup b nonDelayedStartIN
pickupUN
pickupUPP
ANSI16000018 V2 EN-US
Residual overcurrent start has a special stabilizing element in order to prevent a response caused by
an unbalance or different current transformer behavior in the event of high currents during short circuits.
This specializing element can be tuned with respect to the setting parameter, kINStab. The characteristic
for residual overcurrent start is shown in Figure 245. This method of starting element is applicable to all
types of grounding systems.
Operation area
for IN>>
IN>>
Operation area
for IN> No operation
kINStab
IN>
Figure 245: Slope characteristic of residual over current start when using kINStab
During a cross-country fault in a radially fed network, the phase with an external fault typically does not
carry any fault current, which will make it difficult for a conventional phase selection function to detect
both faults. Therefore, PPLPHIZ function provides an additional phase selection based on voltage.
PPLPHIZ is designed to detect two-phase faults based on under-voltage in two phases or between two
phases.
Vx < PU27PN<
A Pickup V
AND
B OR
C
Pickup VBC
AND
AND OR Pickup VA
OR OR AND
OR Pickup VB
AND OR OR AND
AND OR Pickup VC
OR OR AND
Vxy < PU27PP
AB
BC
CA
VA
VB
VC AND
Automatic
VAB phase
VBC detection AND
VCA
OpAutoDetect AND
pickup IN OR
nonDelayedStartIN
AND
pickup UPP
OR
forceIN
ANSI16000019 V2 EN-US
Figure 246: Voltage based phase selection for cross coutry faults
In meshed and complex networks, it may be difficult to find appropriate under-voltage settings for phase
selection. Therefore, an automatic phase selection logic is made available which works in parallel with
a set under-voltage criterion in order to detect the two faulty phases even for complex networks. This
automatic phase selection logic can be switched off or on with the setting OpAutoDetect, which by
default is set On. If, for any reason, this additional logic is unable to detect the two faulty phases, then
after a short time delay, all the three phase-to-earth loops of the distance protection will be released for
operation. The final result might be that both faulty feeders are disconnected. In other words, protection
operation is prioritized over strict adherence to preference.
During a cross-country fault when both faults are in front of the distance protection the residual current
start criterion might not be fulfilled. Additional logic, as given in Figure 247, is then available to detect
such condition and force the phase selection for phase-to-ground loops without the IN criterion. This
logic shall be enabled by using the parameter EnableAutoPhSel. Additional checks for maximum
phase current level, minimum phase voltage level, residual voltage level and phase-to-phase voltage
unbalance level are also included in order to make this logic more secure.
EnableAutoPhSel
MaxPhPhVolt
MinPhPhVolt startUN
nonDelayedStartIN
a
DeltaUPP b forceIN
AND
maxPhCurrent
a
IPhMax> b
minPhVoltage
Min(UL1, UL2, UL3) a
UPhMin< b
U3P maxPhVoltage
Max(UL1, UL2, UL3) a
b
3U0
1,05
X
GUID-14452519-D522-4C60-900F-1E2386D4E704 V1 EN-US
Figure 247: Automatic phase selection for Cross Country fault without residual current
The voltage phase selection can be complemented with external phase selection through inputs
RELAG-CG.
ccfphL1
startUL1 ccfphL2
AND ccfphL3
startUL2
startUPP
AND OR
startUL3
AND
startUL1UL2
phL1L2OpenLoop
AND
startUL2UL3
phL2L3OpenLoop
AND
startUL3UL1
phL3L1OpenLoop
AND
OperMode =
No Filter
OR AND
OperMode =
NoPref startL1
OR
OR
startL2
OR
OR
startL3
RELL3N OR
OR
OR
forceIN
INStartFulfilled
STCND
zrelL1L2
Integer OR
To
Boolean zrelL2L3
OR
zrelL13L1
OR
IEC20210802 V1 EN-US
The different operating modes (selected with OperMode setting) determine how the internal status is
used to release the phases of the connected distance protection.
This setting shall be set in accordance with used phase preference scheme in the protected network. It
is of uttermost importance that all distance relays installed in this network has the same setting value for
this parameter.
In No Filter mode, all distance protection phases are released constantly, leaving it to the phase
selection inside the distance protection to decide which distance zone loops should be allowed to
operate.
startL1 zrelL1
startL2 zrelL2
startL3 zrelL3
IEC16000106-1-en.vsdx
IEC16000106 V1 EN-US
No Filter mode is equivalent to disconnecting the PPLPHIZ from the distance protection.
The ‘NoPref’ mode uses only the residual current criteria (startIN). There is no preference provided in
this mode. All three phase-to-ground loops of the distance protection release when a residual current
start has occurred.
startL1
zrelL1
AND
startL2
zrelL2
AND
startL3
zrelL3
AND
startIN
IEC16000107-1-en.vsdx
IEC16000107 V1 EN-US
In the preference modes (for example, ‘1231c’), the internal under-voltage phase selection status
is filtered with the selected preference scheme to achieve the desired phase preference. Only the
preferred phase-to-earth loop of the distance protection is released to operate. In addition to the voltage
phase selection, a residual current start is also required for operation.
A logic is also included to handle the special case where only one start (startL1-3) is present.
The internal under-voltage phase selection always issues a release in at least two phases, but the
inputs RELL1-3N can be activated with some time apart. If no measures are taken, the phase activated
first will pass through the preference scheme and release the distance protection. Since it could a be
non-preferred phase, a time delay of 40 ms is provided to release if only one phase is detected, in order
to wait for the second phase to be activated. If no second phase is detected within 40 ms, the single
phase is released without preference.
• All three phases are involved in the fault and a cyclic scheme is selected
• No faulty phase can be detected due to an insufficient voltage drop
In both cases, no release signals come from the phase preference scheme. For these cases, an
additional logic is provided that releases all three phase-to-ground loops if there is no output from the
preference scheme after 40 ms from the activation of the residual current start.
Hence, if there is a residual current start, it is guaranteed that the distance protection is released in at
least one phase. This is valid for all phase preference schemes.
Preference
OperMode scheme
Scheme
startL1 prefL1
INL1 OUTL1
startL2 INL2 OUTL2
prefL2
startL3 INL3 OUTL3
prefL3
More than
one true stIN
AND
startIN
40 ms
AND stIN40ms
t
IEC16000023 V3 EN-US
prefL1
OR zrelL1
AND
prefL2
OR zrelL2
AND
prefL3
OR zrelL3
AND
30 ms
OR t
AND
stIN40ms
stIN OR
IEC16000024 V2 EN-US
Figure 252: Logic to release the preferred phase towards distance protection
Table 236 shows the preferred phase for each detected cross-country fault type and operating mode
(OperMode).
Table 236: Preferred phase for each cross-country fault type and operating mode
All loop releasing signals are gathered in the binary coded integer output ZREL. The value of ZREL can
be calculated according to Equation 103.
The BLOCK input will only block the enabling signals for phase-to-earth loops, phase-to-
phase loops are still released.
startIN
STIN
BLOCK AND
startUN
STU
AND
zreIL1
OPENL1E
AND
zreIL2
OPENL2E
AND
zreIL3
OPENL2E
AND
L1N
L2N
L3N
zrelL1L2
L1L2 Bool to ZREL
OR
zrelL2L3 Integer
L2L3
OR
zrelL3L1
L3L1
OR
ccfphL1
CCFPHL1
AND
ccfphL2
CCFPHL2
AND
ccfphL3
CCFPHL3
AND
phL1L2OpenLoop
AND
phL2L3OpenLoop
AND
phL3L1OpenLoop
AND
forceIN
FORCEIN
AND
IEC16000108 V3 EN-US
Table 237: Phase preference logic PPL2PHIZ technical dataPhase preference logic PPLPHIZ technical data
9.19.2 Identification
GUID-850E4134-E912-45EC-981E-E1A2C12A91A8 v1
The Phase preference logic function (PPL2PHIZ) is used with the high speed distance protection, quad
and mho characteristic (ZMFPDIS). It is intended to be used in isolated or high impedance grounded
networks where there is a requirement to trip on only one of the faulty lines during a cross-country fault.
It can be used without preference to restrain trip for single ground faults with a delayed zero-sequence
current release for cable networks grounded using a resistor.
For cross-country faults, the logic selects either the leading or lagging phase-to-ground loop for
measurement. It initiates trip on the preferred phase based on the selected phase preference scheme. A
number of different phase preference schemes are available.
PPL2PHIZ provides an additional phase selection criteria, namely under voltage criteria, suitable for
phase selection during cross-country faults. In radial networks, where there is no fault current in the
phase with the external fault, current or impedance based phase selection methods become ineffective.
Hence, only voltage can be used for phase selection. The phase selection result will be the same for
all bays on a bus since the voltage is the same, which is an important condition for tripping with phase
preference.
In meshed and stronger networks, it may be difficult to find appropriate under-voltage settings for phase
selection. Therefore an automatic phase selection logic is made available which works in parallel with a
set under-voltage criterion in order to detect the two faulty phases even for complex networks. If for any
reason the PPL2PHIZ is unable to detect the two faulty phases, then after a short time delay all three
phase-to-ground loops of the distance protection will be released for operation. The final result might be
that both faulty feeders are disconnected. In other words, protection operation is prioritized over strict
adherence to preference.
During a cross-country fault, both fault locations are in front of the distance protection. The measured
residual current magnitude can be quite small. The PPL2PHIZ function has built-in logic that can detect
such a condition and properly release the preferred phase-to-ground loop.
PPL2PHIZ
I3P* OPENL1E
V3P* OPENL2E
BLOCK OPENL3E
RELAG CCFPHL1
RELBG CCFPHL2
RELCG CCFPHL3
STU
STIN
FORCEIN
ZREL
ZST
ANSI16000016 V2 EN-US
9.19.5 Signals
PID-8024-INPUTSIGNALS v1
9.19.6 Settings
PID-8024-SETTINGS v1
The PPL2PHIZ function releases the phase selection inside the distance protection, see Figure 255.
Before a trip from the distance zones is achieved, the phase selection inside the distance
protection or the automatic phase selection inside PPL2PHIZ has to detect the fault and the
preference phase must be received from the ZREL output of PPL2PHIZ.
PPL2PHIZ ZMFPDIS
Automatic Phase selection
cross-country ZST
phase selection Internal
ORCND criteria bitwise
Phase preference OR
Zone1
AG AG bitwise TRZ1
RELCNDZ1 enable
AND
BG BG
ZREL Zone2
CG bitwise TRZ2
CG Bool to RELCNDZ2 enable
Integer AND
AB Zone3
bitwise TRZ3
BC RELCNDZ3 enable
AND
CA Zone4
RELCNDZ4 bitwise TRZ4
TRUE AND
enable
Zone5
bitwise TRZ5
RELCNDZ5 enable
AND
ZoneRV
RELCNDZRV bitwise TRZRV
enable
AND
ZoneBU
RELCNDZBU bitwise enable
TRZBU
AND
ANSI16000017 V2 EN-US
The fundamental pickup criterion for a cross-country fault is a continuous residual current (3I0) above
setting level Pickup_N.
Transient residual currents associated with single phase fault inception are not allowed to release the
distance protection. This is taken care of by a time-on-delay tIN, which should be set longer than the
expected duration of the transient. This time delay can be bypassed if the magnitude of the residual
current exceeds the set high level Pickup.
If a single phase fault remains for some time, it is possible to bypass the tIN time delay, since the
next fault event is expected to be a cross-country fault. The criterion for this bypass is that the residual
voltage is greater than setting level 3V0PU for a time longer than setting tVN. The time-off-delay tOffVN
is used to make sure that the bypass is steady during the cross-country fault.
The time delay for residual current pickup is also bypassed as soon as two low voltages are detected
during the cross-country fault (startUPP). See Figure 256 for a simplified diagram showing the residual
current start logic.
tIN
a
Pickup_N b AND t
pickupIN
OR
IN a
maxPhCurrent b OR
AND
INStartFulfilled
I3P OR
Max(lL1, IL2, IL3) AND
X
kINStab
a
Pickup b nonDelayedStartIN
pickupUN
pickupUPP
ANSI16000018 V2 EN-US
Residual overcurrent start has a special stabilizing element in order to prevent a response caused by
an unbalance or different current transformer behavior in the event of high currents during short circuits.
This specializing element can be tuned with respect to the setting parameter, kINStab. The characteristic
for residual overcurrent start is shown in Figure 257. This method of starting element is applicable to all
types of grounding systems.
Operation area
for IN>>
IN>>
Operation area
for IN> No operation
kINStab
IN>
Figure 257: Slope characteristic of residual over current start when using kINStab
During a cross-country fault in a radially fed network, the phase with an external fault typically does not
carry any fault current, which will make it difficult for a conventional distance phase selection function
to detect both faults. Therefore, PPL2PHIZ function provides an additional phase selection based on
voltage.
PPL2PHIZ is designed to detect two-phase faults based on under-voltage in two phases or between two
phases.
Vx < PU27PN<
A Pickup V
AND
B OR
C
Pickup VBC
AND
AND OR Pickup VA
OR OR AND
OR Pickup VB
AND OR OR AND
AND OR Pickup VC
OR OR AND
Vxy < PU27PP
AB
BC
CA
VA
VB
VC AND
Automatic
VAB phase
VBC detection AND
VCA
OpAutoDetect AND
pickup IN OR
nonDelayedStartIN
AND
pickup UPP
OR
forceIN
ANSI16000019 V2 EN-US
Figure 258: Voltage based phase selection for cross coutry faults
In meshed and complex networks, it may be difficult to find appropriate under-voltage settings for phase
selection. Therefore, an automatic phase selection logic is made available which works in parallel with
a set under-voltage criterion in order to detect the two faulty phases even for complex networks. This
automatic phase selection logic can be switched disabled or enabled with the setting OpAutoDetect,
which by default is set enabled. If, for any reason, this additional logic is unable to detect the two faulty
phases, then after a short time delay, all the three phase-to-ground loops of the distance protection will
be released for operation. The final result might be that both faulty feeders are disconnected. In other
words, protection operation is prioritized over strict adherence to preference.
During a cross-country fault, when both faults are in front of the distance protection, the residual
current start criterion might not be fulfilled. Additional logic, as given in Figure 259, is then available to
detect such condition and force the phase selection for phase-to-ground loops without the IN criterion.
This logic shall be enabled by using the parameter EnableAutoPhSel. Additional checks for maximum
phase current level, minimum phase voltage level, residual voltage level and phase-to-phase voltage
unbalance level are also included in order to make this logic more secure.
EnableAutoPhSel
MaxPhPhVolt
MinPhPhVolt startUN
nonDelayedStartIN
a
DeltaUPP b forceIN
AND
maxPhCurrent
a
IPhMax> b
minPhVoltage
Min(UL1, UL2, UL3) a
UPhMin< b
U3P maxPhVoltage
Max(UL1, UL2, UL3) a
b
3U0
1,05
X
GUID-14452519-D522-4C60-900F-1E2386D4E704 V1 EN-US
Figure 259: Automatic phase selection for Cross Country fault without residual current
The voltage phase selection can be complemented with external phase selection through inputs
RELAG-CG.
ccfphA
pickupVA ccfphB
AND ccfphC
pickup27PP
AND OR
AND
pickupVAB
phABOpenLoop
AND
pickupVBC
phBCOpenLoop
AND
pickupVCA
phCAOpenLoop
AND
OperMode =
No Filter
OR
OperMode =
NoPref pickupA
RELAG OR
pickupB
RELBG OR
pickupC
RELCG OR
ANSI16000020 V2 EN-US
The different operating modes (selected with OperMode setting) determine how the internal status is
used to release the phases of the connected distance protection.
This setting shall be set in accordance with used phase preference scheme in the protected network. It
is of uttermost importance that all distance relays installed in this network has the same setting value for
this parameter.
In No Filter mode, all distance protection phases are released constantly, leaving it to the phase
selection inside the distance protection to decide which distance zone loops should be allowed to
operate.
TRUE
TRUE zrelL2
TRUE zrelL3
IEC16000021 V2 EN-US
No Filter mode is equivalent to disconnecting the PPL2PHIZ from the distance protection.
The ‘NoPref’ mode uses only the residual current criteria (startIN). There is no preference provided in
this mode. All three phase-to-earth loops of the distance protection releases when a residual current
start has occurred.
TRUE
zrelL1
AND
TRUE zrelL2
AND
TRUE
zrelL3
AND
startIN
IEC16000022 V2 EN-US
In the preference modes (for example, ‘1231c’), the internal under-voltage phase selection status
is filtered with the selected preference scheme to achieve the desired phase preference. Only the
preferred phase-to-earth loop of the distance protection is released to operate. In addition to the voltage
phase selection, a residual current start is also required for operation.
A logic is also included to handle the special case where only one start (startL1-3) is present.
The internal under-voltage phase selection always issues a release in at least two phases, but the
inputs RELL1-3N can be activated with some time apart. If no measures are taken, the phase activated
first will pass through the preference scheme and release the distance protection. Since it could a be
non-preferred phase, a time delay of 40 ms is provided to release if only one phase is detected, in order
to wait for the second phase to be activated. If no second phase is detected within 40 ms, the single
phase is released without preference.
• All three phases are involved in the fault and a cyclic scheme is selected
• No faulty phase can be detected due to an insufficient voltage drop
In both cases, no release signals come from the phase preference scheme. For these cases, an
additional logic is provided that releases all three phase-to-ground loops if there is no output from the
preference scheme after 40 ms from the activation of the residual current start.
Hence, if there is a residual current start, it is guaranteed that the distance protection is released in at
least one phase. This is valid for all phase preference schemes.
Preference
OperMode scheme
Scheme
startL1 prefL1
INL1 OUTL1
startL2 INL2 OUTL2
prefL2
startL3 INL3 OUTL3
prefL3
More than
one true stIN
AND
startIN
40 ms
AND stIN40ms
t
IEC16000023 V3 EN-US
prefL1
OR zrelL1
AND
prefL2
OR zrelL2
AND
prefL3
OR zrelL3
AND
30 ms
OR t
AND
stIN40ms
stIN OR
IEC16000024 V2 EN-US
Figure 264: Logic to release the preferred phase towards distance protection
Table 242 shows the preferred phase for each detected cross-country fault type and operating mode
(OperMode).
Table 242: Preferred phase for each cross-country fault type and operating mode
All loop releasing signals are gathered in the binary coded integer outputs ZREL and ZST. The value of
ZREL can be calculated according to Equation 104.
For example, if only L1N is active, then the value is 1. If both start L1N and L3N are active, then the
value is 1+4=5.
The phase-to-phase loops are always released, that is, the value of ZREL will always be at
least 8+16+32=56. For example:
If only L1N is active, then the value is 1+56=57
If start L1N and L3N are active, then the value is 1+4+56=61
The BLOCK input will only block the enabling signals for phase-to-ground loops, phase-to-
phase loops are still released.
Where P-Coil, Reactor, Resistor, Isolated and Solidly are the chosen system groundings in the setting of
SystemGrounding.
startIN
STIN
BLOCK AND
startUN
STU
AND
zreIL1
OPENL1E
AND
zreIL2
OPENL2E
AND
zreIL3
OPENL2E
AND
L1N
L2N
L3N
Bool to ZREL
TRUE L1L2 Integer
TRUE L2L3
TRUE L3L1
ccfphL1
CCFPHL1
AND
ccfphL2
CCFPHL2
AND
ccfphL3
CCFPHL3
AND
phL1L2OpenLoop
AND
phL2L3OpenLoop
AND
Bool to
AND Integer ZST
forceIN
AND
SystemEarthing
FORCEIN
IEC16000025 V2 EN-US
Table 243: Phase preference logic PPL2PHIZ technical dataPhase preference logic PPLPHIZ technical data
10.1.1 Identification
M14880-1 v5
SYMBOL-Z V1 EN-US
The instantaneous three phase overcurrent (PHPIOC) function has a low transient overreach and short
tripping time to allow use as a high set short-circuit protection function.
PHPIOC (50)
I3P* TRIP
BLOCK TR_A
MULTPU TR_B
TR_C
ANSI04000391-2-en.vsd
ANSI04000391 V2 EN-US
PID-6914-INPUTSIGNALS v3
PID-6914-SETTINGS v3
The sampled analogue phase currents are pre-processed in a discrete Fourier filter (DFT) block. The
RMS value of each phase current is derived from the fundamental frequency components, as well as
sampled values of each phase current. These phase current values are fed to the instantaneous phase
overcurrent protection 3-phase output function PHPIOC. In a comparator the RMS values are compared
to the set operation current value of the function (IP>>).
If a phase current is larger than the set operation current a signal from the comparator for this phase is
set to true. This signal will, without delay, activate the output signal TR_x(x=A, B or C) for this phase and
the TRIP signal that is common for all three phases.
There is an operation mode (OpModeSel) setting: 1 out of 3 or 2 out of 3. If the parameter is set to 1
out of 3, any phase trip signal will be activated. If the parameter is set to 2 out of 3, at least two phase
signals must be activated for trip.
There is also a possibility to activate a preset change of the set operation current (MultPU) via a binary
input (MULTPU). In some applications the operation value needs to be changed, for example, due to
transformer inrush currents.
The operation current value IP>>, is limited to be between IP>>Max and IP>>Min. The default values
of the limits are the same as the setting limits for IP>>, and the limits can only be used for reducing
the allowed range of IP>>. This feature is used when remote setting of the operation current value is
allowed, making it possible to ensure that the operation value used is reasonable. If IP>> is set outside
IP>>Max and IP>>Min, the closest of the limits to IP>> is used by the function. If IP>>Max is smaller
then IP>>Min, the limits are swapped. The principle of the limitation is shown in Figure 267.
IP>>Max
MAX hi
u y
IP>>_used
IP>>
MIN lo
IP>>Min
IEC17000016-1-en.vsdx
IEC17000016 V1 EN-US
M12336-1 v14
Q 2.2.6 -
R 2.2.6 Minimum value changed to 0.01 for k1,k2,k3 and k4 settings
10.2.2 Identification
M14885-1 v6
TOC-REVA V2 EN-US
Directional phase overcurrent protection, four steps OC4PTOC (51/67) has independent inverse time
delay settings for steps 1 to 4.
All IEC and ANSI inverse time characteristics are available together with an optional user defined time
characteristic.
The directional function needs voltage as it is voltage polarized with memory. The function can be set to
be directional or non-directional independently for each of the steps.
A second harmonic blocking level can be set for the function and can be used to block each step
individually.
OC4PTOC (51_67)
I3P* TRIP
V3P* TRST1
BLOCK TRST2
BLKTR TRST3
BLK1 TRST4
BLK2 TR_A
BLK3 TR_B
BLK4 TR_C
MULTPU1 TRST1_A
MULTPU2 TRST1_B
MULTPU3 TRST1_C
MULTPU4 TRST2_A
TRST2_B
TRST2_C
TRST3_A
TRST3_B
TRST3_C
TRST4_A
TRST4_B
TRST4_C
PICK UP
PU_ST1
PU_ST2
PU_ST3
PU_ST4
PU_A
PU_B
PU_C
PU_ST1_A
PU_ST1_B
PU_ST1_C
PU_ST2_A
PU_ST2_B
PU_ST2_C
PU_ST3_A
PU_ST3_B
PU_ST3_C
PU_ST4_A
PU_ST4_B
PU_ST4_C
PU2NDHARM
DIR_A
DIR_B
DIR_C
STDI RCND
=ANSI06000187=4=en=Original.vsdx
ANSI06000187 V4 EN-US
10.2.5 Signals
PID-8147-INPUTSIGNALS v1
10.2.6 Settings
PID-8147-SETTINGS v1
Directional phase overcurrent protection, four steps OC4PTOC (51_67) is divided into four different
sub-functions. For each step x , where x is step 1, 2, 3 and 4, an operation mode is set by DirModeSelx:
Disable/Non-directional/Forward/Reverse.
If VT inputs are not available or not connected, setting parameter DirModeSelx shall be left to
default value, Non-directional.
4 step overcurrent
Direction dirPhAFlt element faultState
faultState
Element One element for each
dirPhBFlt step
I3P dirPhCFlt PICKUP
V3P
TRIP
Harmonic harmRestrBlock
Restraint
Element
enableDir
Mode Selection
enableStep1-4
DirectionalMode1-4
ANSI05000740-3-en.vsdx
ANSI05000740 V3 EN-US
Using a parameter setting MeasType within the general settings for the function OC4PTOC (51/67), it is
possible to select the type of the measurement used for all overcurrent stages. Either discrete Fourier
filter (DFT) or true RMS filter (RMS) can be selected.
If the DFT option is selected, only the RMS value of the fundamental frequency component of each
phase current is derived. The influence of the DC current component and higher harmonic current
components are almost completely suppressed. If the RMS option is selected, then the true RMS value
is used. The true RMS value includes the contribution from the current DC component as well as from
the higher current harmonic in addition to the fundamental frequency component.
In a comparator, the DFT or RMS values are compared to the set operation current value of the function
(I1>, I2>, I3> or I4>) for each phase current. If a phase current is larger than the set operation current,
outputs START, STx, STL1, STL2 and STL3 are activated without delay. Output signals STL1, STL2
and STL3 are common for all steps. This means that the lowest set step will initiate the activation.
The START signal is common for all three phases and all steps. It shall be noted that the selection of
measured value (DFT or RMS) do not influence the operation of directional part of OC4PTOC.
Service values for individually measured phase currents are available on the local HMI for OC4PTOC
(51/67) function, which simplifies testing, commissioning and in service operational checking of the
function.
A harmonic restrain of the function can be chosen. A set 2nd harmonic current in relation to the
fundamental current is used.
The function can be directional. The direction of a fault is given as the current angle in relation to
the voltage angle. The fault current and fault voltage for the directional function are dependent on the
fault type. The selection of the measured value (DFT or RMS) does not influence the operation of the
directional part of OC4PTOC (51/67) . To enable directional measurement at close-in faults, causing a
low measured voltage, the polarization voltage is a combination of the apparent voltage (85%) and a
memory voltage (15%). The following combinations are used.
Vref _ AB = VA - VB I dir _ AB = I A - I B
GUID-4F361BC7-6D91-47B5-8119-A27009C0AD6A V1 EN-US (Equation 106)
Vref _ BC = VB - VC I dir _ BC = I B - I C
ANSIEQUATION1450 V1 EN-US (Equation 107)
Vref _ CA = VC - VA I dir _ CA = IC - I A
ANSIEQUATION1451 V1 EN-US (Equation 108)
Vref _ A = VA I dir _ A = I A
ANSIEQUATION1452 V1 EN-US (Equation 109)
Vref _ B = VB I dir _ B = I B
ANSIEQUATION1453 V1 EN-US (Equation 110)
Vref _ C = VC I dir _ C = I C
ANSIEQUATION1454 V1 EN-US (Equation 111)
The polarizing voltage is available as long as the positive-sequence voltage exceeds 5% of the set base
voltage VBase. So the directional element can be used for all unsymmetrical faults including close-in
faults.
For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence
voltage, ensures correct directional discrimination.
The memory voltage is used for 100 ms or until the positive sequence voltage is restored.
• If the current is still above the set value of the minimum operating current (7% of the set terminal rated
current IBase), the condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element in the reverse direction
remains in operation.
• If the current decreases below the minimum operating value, the memory resets until the positive
sequence voltage exceeds 10% of its rated value.
The directional setting is given as a characteristic angle AngleRCA for the function and an angle window
ROADir.
Reverse
Vref
RCA
ROA
ROA Forward
Idir
en05000745_ansi.vsd
ANSI05000745 V1 EN-US
The default value of AngleRCA is –55°. The parameter AngleROA gives the angular distance from
AngleRCA to define the directional borders.
A minimum current for the directional phase pickup current signal can be set. PUMinOpPhSel is the
pickup level for the directional evaluation of IA, IB and IC. The directional signals release the overcurrent
measurement in the respective phases if their current amplitudes are higher than the pickup level
(PUMinOpPhSel) and the direction of the current is according to the set direction of the step.
If no blocking signals are active, the pickup signal will start the timer of the steps. The time characteristic
for each step can be chosen as definite time delay or an inverse time delay characteristic. A wide range
of standardized inverse time delay characteristics is available. It is also possible to create a tailor made
time characteristic.
The possibilities for inverse time characteristics are described in section "Inverse characteristics".
HarmBlockx = Enabled
Freeze Timers
AND
2ndH_FreezeTimers_int
EMULTX
IMinx Characteristx=DefTime
X T b tx
F a>b
a t
TRINx
AND AND
|IOP|
a OR
a>b
b
PUSTx
MultPUx AND
X T
F
Inverse
Pickupx
AND
AND
Characteristx=Inverse
txmin
DirModex=Off t
OR STEPx_DIR_Int
DirModex=Non-directional
DirModex=Forward AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
ANSI12000008-2-en.vsdx
ANSI12000008 V4 EN-US
I3P
DFWDLx
V3P DFWDLxx
DREVLx
Directional
Element
AngleRCA DREVLxx FORWARD_int
Directional
AngleROA Release REVERSE_int
Block
STLx
Greater
PUminOpPhSel Comparator
x- means three phases 1,2 and 3
xx – means phase to phase 12,23,31
ANSI15000266-2-en.vsdx
ANSI15000266 V2 EN-US
Different types of reset time can be selected as described in section "Inverse characteristics".
There is a possibility to activate a preset change (MultiPUx, x= 1, 2, 3 or 4) of the set operation current
via a binary input ENMULTx (enable multiplier). In some applications the operation value needs to be
changed, for example due to changed network switching state.
The operation current value Ix>, is limited to be between Ix>Max and Ix>Min. The default values of the
limits are the same as the setting limits for Ix>, and the limits can only be used for reducing the allowed
range of Ix>. This feature is used when remote setting of the operation current value is allowed, making
it possible to ensure that the operation value used is reasonable. If Ix> is set outside Ix>Max and Ix>Min,
the closest of the limits to Ix> is used by the function. If Ix>Max is smaller then Ix>Min, the limits are
swapped. The principle of the limitation is shown in Figure 273.
Ix>Max
MAX hi
u y
Ix>_used
Ix>
MIN lo
Ix>Min
IEC17000018-1-en.vsdx
IEC17000018 V1 EN-US
The STDIRCND output provides an integer signal that depends on the start and directional evaluation
and is derived from a binary coded signal as described in Table 257.
STDIRCND Description
bit 0 (1) General start
bit 1 (2) Direction detected in forward
bit 2 (4) Direction detected in reverse
bit 3 (8) Start in phase L1
bit 4 (16) Forward direction detected in phase L1
bit 5 (32) Reverse direction detected in phase L1
bit 6 (64) Start in phase L2
bit 7 (128) Forward direction detected in phase L2
bit 8 (256) Reverse direction detected in phase L2
bit 9 (512) Start in phase L3
bit 10 (1024) Forward direction detected in phase L3
bit 11 (2048) Reverse direction detected in phase L3
All four steps in OC4PTOC (51/67) can be blocked from the binary input BLOCK. The binary input BLKx
(x=1, 2, 3 or 4) blocks the operation of the respective step.
The pickup signals from the function can be blocked by the binary input BLK. The trip signals from the
function can be blocked by the binary input BLKTR.
GUID-E3980B2D-EEDA-4BF1-A07D-E7B721130554 v7
A harmonic restrain of the directional phase overcurrent protection function OC4PTOC 51_67 can be
chosen. If the ratio of the 2nd harmonic component in relation to the fundamental frequency component
in a phase current exceeds the preset level defined by the parameter 2ndHarmStab setting, any of
the four overcurrent stages can have their timers selectively frozen by the parameter HarmBlockx
setting. When the 2nd harmonic restraint feature is active, the OC4PTOC 51_67 function output signal
ST2NDHRM will be set to the logical value one.
BLOCK
a
a>b
0.07*IBase b
a
a>b
b
Extract second AND
IOP
harmonic current a
a>b
component b
Extract 2ndH_FreezeTimers_Int
fundamental
current component
X
2ndHarmStab
IEC13000014-3-en.vsdx
IEC13000014 V3 EN-US
When enabled, the 2nd harmonic blocking function is used to freeze the Definite and/or the
Inverse Characteristics internal timers. When the function detects a 2nd harmonic higher
than the set threshold, the internal function timers are frozen but PICKUP outputs continues
to be active as long as the measured current is above the set pickup level. Internal timers
will again resume timing when harmonic content becomes smaller than the set threshold and
the measured current is higher than the pickup value. If TRIP output is already active when
harmonic blocking signal appears the TRIP output will not be affected.
When DirModex is set to Forward/Reverse and Ix> is set at its minimum value, that is, 5.0%
of IBase, the operation from the respective overcurrent step takes place at 20.0% of IBase.
This is done to avoid unintentional maloperations during unbalanced loading conditions that
might appear in power systems and the unbalanced loading condition might lead to a neutral
current in the range of 10.0% to 15.0% of IBase.
10.3.1 Identification
M14887-1 v4
IEF V1 EN-US
The Instantaneous residual overcurrent protection (EFPIOC (50N)) has a low transient overreach and
short tripping times to allow the use for instantaneous ground-fault protection, with the reach limited
to less than the typical eighty percent of the line at minimum source impedance. EFPIOC (50N) is
configured to measure the residual current from the three-phase current inputs and can be configured to
measure the current from a separate current input.
EFPIOC (50N)
I3P* TRIP
BLOCK
BLKAR
ENMULT
ANSI06000269-3-en.vsdx
ANSI06000269 V3 EN-US
PID-6915-INPUTSIGNALS v4
PID-6915-SETTINGS v4
The sampled analog residual currents are pre-processed in a discrete Fourier filter (DFT) block. From
the fundamental frequency components of the residual current, as well as from the sample values the
equivalent RMS value is derived. This current value is fed to the Instantaneous residual overcurrent
protection (EFPIOC). In a comparator the RMS value is compared to the set operation current value of
the function (IN>>).
If the residual current is larger than the set operation current a signal from the comparator is set to true.
This signal will, without delay, activate the output signal TRIP.
There is also a possibility to activate a preset change of the set operation current via a binary
input (enable multiplier ENMULT). In some applications the operation value needs to be changed, for
example, due to transformer inrush currents.
The operation current value IN>>, is limited to be between IN>>Max and IN>>Min. The default values
of the limits are the same as the setting limits for IN>>, and the limits can only be used for reducing
the allowed range of IN>>. This feature is used when remote setting of the operation current value is
allowed, making it possible to ensure that the operation value used is reasonable. If IN>> is set outside
IN>>Max and IN>>Min, the closest of the limits to IN>> is used by the function. If IN>>Max is smaller
then IN>>Min, the limits are swapped. The principle of the limitation is shown in Figure 276.
IN>>Max
MAX hi
u y
IN>>_used
IN>>
MIN lo
IN>>Min
IEC17000015-1-en.vsdx
IEC17000015 V1 EN-US
EFPIOC (50N) function can be blocked from the binary input BLOCK. The trip signals from the
function can be blocked from the binary input BLKAR, that can be activated during single pole trip
and autoreclosing sequences.
M12340-2 v10
10.4.2 Identification
M14881-1 v7
Directional residual overcurrent protection, four steps EF4PTOC (51N/67N) can be used as main
protection for phase-to-ground faults. It can also be used to provide a system back-up, for example,
in the case of the primary protection being out of service due to communication or voltage transformer
circuit failure.
EF4PTOC (51N/67N) has an inverse or definite time delay independent for each step.
All IEC and ANSI time-delayed characteristics are available together with an optional user-defined
characteristic.
EF4PTOC (51N/67N) can be set to be directional or non-directional independently for each step.
IDir, VPol and IPol can be independently selected to be either zero sequence or negative sequence.
Directional operation can be combined together with the corresponding communication logic in
permissive or blocking teleprotection scheme. The current reversal and weak-end infeed functionality
are available as well.
The residual current can be calculated by summing the three-phase currents or taking the input from the
neutral CT.
EF4PTOC (51N/67N) also provides very fast and reliable faulty phase identification for phase selective
tripping and subsequent reclosing during earth fault.
EF4PTOC (51N_67N)
I3P* TRIP
I3PDIR* TRST1
I3PPOL* TRST2
V3P* TRST3
BLOCK TRST4
BLKTR TRSOTF
BLK1 PICKUP
BLK2 PUST1
BLK3 PUST2
BLK4 PUST3
BLKPHSEL PUST4
MULTPU1 PUSOTF
MULTPU2 PUFW
MULTPU3 PUREV
MULTPU4 PHSEL_A
52A PHSEL_B
CLOSECMD PHSEL_C
OPENCMD 2NDHARMD
ANSI06000424-6-en.vsdx
ANSI06000424 V6 EN-US
PID-8149-INPUTSIGNALS v1
PID-8149-SETTINGS v1
M13941-51 v8
This function has the following four analog inputs on its function block in the configuration tool:
1. I3P, input used for the operating quantity. Supplies the zero-sequence magnitude measuring
functionality.
2. V3P, input used for the voltage polarizing quantity. Supplies either the zero or the negative
sequence voltage to the directional functionality
3. I3P and V3P also supply current and voltage samples for faulty phase selection functionality.
4. I3PPOL, input used for the current polarizing quantity. Provides polarizing current to the directional
functionality. This current is normally taken from the grounding of a power transformer.
5. I3PDIR, input used for directional detection. Supplies either the zero or the negative sequence
current to the directional functionality.
These inputs are connected from the corresponding pre-processing function blocks in the configuration
tool in PCM600.
The function always uses residual current (3I0) for its operating quantity. The residual current can be:
1. Directly measured (when a dedicated CT input of the IED is connected in PCM600 to the fourth
analog input of the pre-processing block connected to EF4PTOC (51N/67N) function input I3P). This
dedicated IED CT input can be, for example, connected to:
• Parallel connection of current instrument transformers in all three phases (Holm-Green
connection).
• One single core balance current instrument transformer (cable CT).
• One single current instrument transformer located between power system WYE point and ground
(current transformer located in the neutral grounding of a WYE connected transformer winding).
• One single current instrument transformer located between two parts of a protected object (current
transformer located between two WYE points of double WYE shunt capacitor bank).
2. Calculated from three-phase current input within the IED (when the fourth analog input of the
pre-processing block, connected to EF4PTOC (51N/67N) function Analog Input I3P, is not connected
to a dedicated CT input of the IED in PCM600). In such a case, the pre-processing block will
calculate 3I0 from the first three inputs into the pre-processing block by using the following formula
(will take 3I0 from SMAI AI3P and will be connected to I3PDIR and I3P inputs.
I op = 3 × Io = IA + IB + IC
EQUATION2011-ANSI V1 EN-US (Equation 112)
where:
IA, IB, and IC are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete Fourier filter. Thus the phasor of the fundamental
frequency component of the residual current is derived. The phasor magnitude is used within the
EF4PTOC protection to compare it with the set operation current value of the four steps (IN1>, IN2>,
IN3>, or IN4>).
If the residual current is larger than the set operation current and the step is used in non-directional
mode a signal from the comparator for this step is set to true. This signal will, without delay, activate the
output signal STINx (x=step 1-4) for this step and a common START signal.
A polarizing quantity is used within the protection in order to determine the direction to the ground fault
(forward/reverse).
The function can be set to use voltage polarizing, current polarizing or dual polarizing.
Voltage polarizing
When voltage polarizing is selected, the protection will use the residual voltage -3V0 as the polarizing
quantity V3P.
1. Directly measured (when a dedicated VT input of the IED is connected in PCM600 to the fourth
analog input of the pre-processing block connected to EF4PTOC (51N/67N) function input V3P).
This dedicated IED VT input shall be then connected to the open delta winding of a three-phase
main VT.
2. Calculated from three-phase voltage input within the IED (when the fourth analog input of the pre-
processing block, connected to EF4PTOC (51N/67N) analog function input V3P, is NOT connected
to a dedicated VT input of the IED in PCM600). In such a case, the pre-processing block will
calculate -3V0 from the first three inputs into the pre-processing block by using the following formula:
where:
VA, VB, and VC are fundamental frequency phasors of three individual phase voltages.
In order to use this, all three phase-to-ground voltages must be connected to three IED VT
inputs.
The residual voltage is pre-processed by a discrete Fourier filter. Thus, the phasor of the fundamental
frequency component of the residual voltage is derived.
This phasor is used together with the phasor of the operating directional current, in order to determine
the direction to the ground fault (Forward/Reverse). In order to enable voltage polarizing the magnitude
of polarizing voltage shall be bigger than a minimum level defined by setting parameter VPolMin.
It shall be noted that residual voltage (-3V0) or negative sequence voltage (-3V2) is used to determine
the location of the ground fault. This ensures the required inversion of the polarizing voltage within the
ground-fault function.
Current polarizing
When current polarizing is selected, the function will use an external residual current (3I0) as the
polarizing quantity IPol. This current can be:
1. Directly measured (when a dedicated CT input of the IED is connected in PCM600 to the fourth
analog input of the pre-processing block, connected to EF4PTOC (51N/67N) function input I3PPOL).
This dedicated IED CT input is then typically connected to one single current transformer located
between power system WYE point and ground (current transformer located in the WYE point of a
WYE connected transformer winding).
• For some special line protection applications, this dedicated IED CT input can be connected to a
parallel connection of current transformers in all three phases (Holm-Green connection).
2. Calculated from three phase current input within the IED (when the fourth analog input into the
pre-processing block, connected to EF4PTOC (51N/67N) function analog input I3PPOL, is NOT
connected to a dedicated CT input of the IED in PCM600). In such case, the pre-processing block
will calculate 3I0 from the first three inputs into the pre-processing block by using the following
formula:
I Pol = 3 × Io = IA + IB + IC
EQUATION2019-ANSI V1 EN-US (Equation 116)
where:
IA, IB, and IC are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete fourier filter. Thus the phasor of the fundamental
frequency component of the polarizing current is derived. This phasor is then multiplied with the pre-set
equivalent zero-sequence source impedance in order to calculate the equivalent polarizing voltage VIPol
in accordance with the following formula:
which will be then used, together with the phasor of the operating current, in order to determine the
direction to the ground fault (forward/reverse).
In order to enable current polarizing, the magnitude of the polarizing current shall be bigger than a
minimum level defined by setting parameter IPolMin.
Dual polarizing
When dual polarizing is selected, the function will use the vectorial sum of the voltage based and current
based polarizing in accordance with the following formula:
Vpol and Ipol can be either zero sequence component or negative sequence component depending
upon the user selection.
Then the phasor of the total polarizing voltage VTotPol will be used, together with the phasor of the
operating current, to determine the direction of the ground fault (forward/reverse).
The individual steps within the protection can be set as non-directional. When this setting is selected,
it is possible via the function binary input BLKx to provide external directional control (that is, torque
control) by, for example, using one of the following functions if available in the IED:
Zero sequence components will be used for detecting directionality for the ground fault function. In some
cases, zero sequence quantities might detect directionality incorrectly. In such a scenario, negative
sequence quantities will be used. The user can select either zero sequence components or negative
sequence components for detecting directionality with the parameter SeqTypeIPol. I3PDIR input is
always connected to the same source as I3P input.
The base quantities are entered as global settings for all functions in the IED. Base current (IBase) shall
be entered as rated phase current of the protected object in primary amperes. Base voltage (VBase)
shall be entered as rated phase-to-phase voltage of the protected object in primary kV.
Each overcurrent step uses operating quantity Iop (residual current) as the measuring quantity. Each of
the four residual overcurrent steps has the following built-in facilities:
• Time delay related settings. By these parameter settings the properties like definite time delay,
minimum operating time for inverse curves, reset time delay and parameters to define user
programmable inverse curve are defined.
• Supervision by second harmonic blocking feature (Enabled/Disabled). By this parameter setting it
is possible to prevent operation of the step if the second harmonic content in the residual current
exceeds the preset level.
• Multiplier for scaling of the set residual current pickup value by external binary signal. By this
parameter setting it is possible to increase residual current pickup value when function binary input
MULTPUx has logical value 1.
• The operation current value INx>, is limited to be between INx>Max and INx>Min. The default values
of the limits are the same as the setting limits for INx>, and the limits can only be used for reducing
the allowed range of INx>. This feature is used when remote setting of the operation current value is
allowed, making it possible to ensure that the operation value used is reasonable. If INx> is set outside
INx>Max and INx>Min, the closest of the limits to INx> is used by the function. If INx>Max is smaller
then INx>Min, the limits are swapped. The principle of the limitation is shown in Figure 278.
INx>Max
MAX hi
INx>_used
INx> u y
MIN lo
INx>Min
IEC17000017-2-en.vsdx
IEC17000017 V2 EN-US
Simplified logic diagram for one residual overcurrent step is shown in Figure 279.
HarmBlockx = Enabled
Freeze Timers
AND
2ndH_FreezeTimers_int
EMULTX
IMinx Characteristx=DefTime
X T b tx
F a>b
a t
TRINx
AND AND
|IOP|
a OR
a>b
b
PUSTx
MultPUx AND
X T
F
Inverse
Pickupx
AND
AND
Characteristx=Inverse
txmin
DirModex=Off t
OR STEPx_DIR_Int
DirModex=Non-directional
DirModex=Forward AND OR
FORWARD_Int
DirModex=Reverse
AND
REVERSE_Int
ANSI10000008-4-en.vsdx
ANSI10000008 V4 EN-US
Figure 279: Simplified logic diagram for residual overcurrent step x, where x = step 1, 2, 3 or 4
The protection can be completely blocked from the binary input BLOCK. Output signals for respective
step, and PUSTx and TRSTx, can be blocked from the binary input BLKx. The trip signals from the
function can be blocked from the binary input BLKTR.
At least one of the four residual overcurrent steps shall be set as directional in order
to enable execution of the directional supervision element and the integrated directional
comparison function.
The protection has an integrated directional feature. As the operating quantity current Iop is always used,
the polarizing method is determined by the parameter setting polMethod. The polarizing quantity will be
selected by the function in one of the following three ways:
The operating and polarizing quantity are then used inside the directional element, as shown in Figure
280, in order to determine the direction of the ground fault.
Operating area
PUREV
0.6 * INDirPU
Characteristic for reverse
release of measuring steps
-RCA -85 deg
Characteristic
for PUREV 40% of
INDirPU RCA +85 deg
RCA
65° VPol = -3V0
PUFW
I op = 3I0
Operating area
Characteristic
for PUFW ANSI11000243-1-en.ai
ANSI11000243 V1 EN-US
Figure 280: Operating characteristic for ground-fault directional element using the zero sequence components
The relevant setting parameters for the directional supervision element are:
• The directional element will be internally enabled to trip as soon as Iop is bigger than 40% of IDirPU
and the directional condition is fulfilled in the set direction.
• The relay characteristic angle AngleRCA, which defines the position of forward and reverse areas in
the operating characteristic.
1. PUFW=1 when operating quantity magnitude Iop x cos(φ - AngleRCA) is bigger than setting
parameter IDirPU and directional supervision element detects fault in forward direction.
2. PUREV=1 when operating quantity magnitude Iop x cos(φ - AngleRCA) is bigger than 60% of
setting parameter IDirPU and directional supervision element detects fault in reverse direction.
These signals shall be used for communication based ground-fault teleprotection communication
schemes (permissive or blocking).
Simplified logic diagram for directional supervision element with integrated directional comparison step is
shown in Figure 281:
|IopDir|
a
a>b PUREV
b AND
REVERSE_Int
0.6
X
a
a>b
AND PUFW
IDirPU b
FORWARD_Int
X
0.4
FWD
AND FORWARD_Int
AngleRCA
polMethod=Voltage
OR
VPolMin
Characteristic
Directional
polMethod=Dual IPolMin
VPol T
I3PDIR
polMethod=Current 0.0 F
OR
VTPol
IPol AND REVERSE_Int
T RVS
0.0 F
VIPol
RNPol X STAGE1_DIR_Int
Complex T
STAGE2_DIR_Int
XNPol Number 0.0 F STAGE3_DIR_Int OR
STAGE4_DIR_Int
BLOCK AND
ANSI07000067-4-en.vsd
ANSI07000067 V4 EN-US
Figure 281: Simplified logic diagram for directional supervision element with integrated directional comparison step
A harmonic restrain can be chosen for each step by a parameter setting HarmBlockx. If the ratio of
the 2nd harmonic component in relation to the fundamental frequency component in the residual current
exceeds the preset level (defined by parameter 2ndHarmStab), output signal 2NDHARMD is set to
logical value one and the harmonic restraining feature to the function block will be applicable.
Blocking from the 2nd harmonic element activates if all of three criteria are satisfied:
In addition to the basic functionality explained above, the 2nd harmonic blocking can be set in such
way to seal-in until residual current disappears. This feature might be required to stabilize EF4PTOC
(51N67N) during switching of parallel transformers in the station. In case of parallel transformers there
is a risk of sympathetic inrush current. If one of the transformers is in operation, and the parallel
transformer is switched in, the asymmetric inrush current of the switched-in transformer will cause
partial saturation of the transformer already in service. This is called transferred saturation. The 2nd
harmonic of the inrush currents of the two transformers is in phase opposition. The summation of the
two currents thus gives a small 2nd harmonic current. The residual fundamental current is however
significant. The inrush current of the transformer in service before the parallel transformer energizing,
is a little delayed compared to the first transformer. Therefore, we have high 2nd harmonic current
component initially. After a short period this current is however small and the normal 2nd harmonic
blocking resets. If the BlkParTransf function is activated, the 2nd harmonic restrain signal is latched as
long as the residual current measured by the relay is larger than a selected step current level by using
setting UseStartValue.
This feature has been called Block for Parallel Transformers. This 2nd harmonic seal-in feature is
activated when all of the following three conditions are simultaneously fulfilled:
Once Block for Parallel Transformers is activated, the basic 2nd harmonic blocking signal is sealed-in
until the residual current magnitude falls below a value defined by parameter setting Use_PUValue (see
condition 3 above).
Simplified logic diagram for 2nd harmonic blocking feature is shown in Figure 282.
BLOCK
a
a>b
0.07*IBase b
a
a>b
b
Extract second AND
IOP
harmonic current a
a>b
component b
Extract
fundamental
current component
X
2ndHarmStab
q-1
0-70ms OR 2ndH_FreezeTimers_int
AND OR
0
BlkParTransf=On
|IOP|
a
a>b
b
Use_PUValue
Pickup1>
Pickup2>
Pickup3>
Pickup4>
ANSI13000015-2-en.vsdx
ANSI13000015 V2 EN-US
Figure 282: Simplified logic diagram for 2nd harmonic blocking feature and Block for Parallel Transformers feature
When enabled, the 2nd harmonic blocking function is used to freeze the Definite and/or the
Inverse Characteristics internal timers. When the function detects a 2nd harmonic higher
than the set threshold, the internal function timers are frozen but PICKUP outputs continues
to be active as long as the measured current is above the set pickup level. Internal timers
will again resume timing when harmonic content becomes smaller than the set threshold and
the measured current is higher than the pickup value. If TRIP output is already active when
harmonic blocking signal appears the TRIP output will not be affected.
Integrated in the four step residual overcurrent protection are the switch on to fault logic (SOTF) and
the under-time logic. The setting parameter SOTF is set to activate SOTF, the under-time logic or both.
When the circuit breaker is closing there is a risk to close it onto a permanent fault, for example during
an autoreclosing sequence. The SOTF logic will enable fast fault clearance during such situations. The
time during which SOTF and under-time logics will be active after activation is defined by the setting
parameter t4U.
The SOTF logic uses the pickup signal from step 2 or step 3 for its operation, selected by setting
parameter StepForSOTF. The setting parameter SOTFSel can be set for activation of CB position open
change, CB position closed change or CB close command. In case of a residual current pickup from
step 2 or 3 (dependent on setting) the function will give a trip after a set delay tSOTF. This delay is
normally set to a short time (default 200 ms).
The under-time logic acts as a circuit breaker pole-discrepancy protection, but it is only active
immediately after breaker switching. The under-time logic can only be used in solidly or low impedance
grounded systems.
The under-time logic always uses the pickup signal from the step 4. The under-time logic will normally
be set to operate for a lower current level than the SOTF function. The under-time logic can also be
blocked by the 2nd harmonic restraint feature. This enables high sensitivity even if power transformer
inrush currents can occur at breaker closing. This logic is typically used to detect asymmetry of CB poles
immediately after switching of the circuit breaker. The under-time logic is activated either from change in
circuit breaker position or from circuit breaker close and open command pulses. This selection is done
by setting parameter ActUnderTime. In case of a pickup from step 4 this logic will give a trip after a set
delay tUnderTime. This delay is normally set to a relatively short time (default 300 ms).
SOTF
200 ms
Open
t
t4U
200 ms
Closed
t ActivationSOTF
tSOTF
Close command AND
AND t
STIN2
StepForSOTF
STIN3
SOTF
BLOCK
OFF
SOTF
UNDERTIME TRIP
UnderTime
tUnderTime
SOTF or
2nd Harmonic AND
HarmResSOFT t UnderTime
OR
Open
Close OR
t4U
Close command
ActUnderTime
AND
STIN4
ANSI06000643-6-en.vsdx
ANSI06000643 V6 EN-US
Figure 283: Simplified logic diagram for SOTF and under-time features
M13941-3 v6
Simplified logic diagram for the complete EF4PTOC (51N/67N) function is shown in Figure 284:
harmRestrBlock
3I0 Harmonic
Restraint 1
Element TRIP
Blocking at parallel
transformers
SwitchOnToFault
TRSOTF
CB
DirModeSel pos
or cmd
enableDir
Mode
Selection enableStep1-4
DirectionalMode1-4
ANSI06000376-2-en.vsdx
ANSI06000376 V2 EN-US
The phase selection element provides very fast and reliable faulty phase identification for phase
selective tripping and subsequent reclosing during earth faults. The operation of the phase selection
element is based on both voltage phasor comparison and current change criteria. This measuring
principle successfully distinguishes the faulty phase with minimum influence from load current or other
disturbances, such as power swing. The phase selection feature can be enabled by setting EnPhaseSel.
The faulty phases are primarily identified by a delta current criteria. Per-phase and phase-to-phase delta
currents are calculated and compared with different criteria to determine if there is a single phase or
phase-to-phase to ground fault. In case the fault cannot be identified by the delta current criteria, a
voltage phasor based method will be applied by comparing the angle between the voltage phasor and
the zero sequence current. The voltage phasor based method is applicable for forward direction single
phase to ground faults. If a three phase disturbance has been identified (for example, during power
swing), the voltage based method will be temporarily disabled until the disturbance disappears.
The operation of the phase selection element is controlled by the measured zero sequence current.
When the measured zero sequence current is above the operate level (60% of IN>Dir), phase selection
is released. Once the faulty phase is selected, the selected phase will be latched until the zero sequence
current drops below the operate level.
Outputs PHSELL1, PHSELL2, and PHSELL3 are used to indicate the selected faulty phases. The
outputs are released when general START from EF4 function is TRUE.
The phase selection element will be blocked by the external input BLKPHSEL or when the circuit
breaker position is open. The CBPOS input will be high when the circuit breaker is closed and it will
be low when the circuit breaker is open. The CBPOS input provides the CB position to phase selection
element.
tON = 20ms
Phase selection by
U3P voltage and zero
AND 1s AND
sequence current
phasor
No 3 Phase Disturbance
STFW
IEC20000563-2-en.vsdx
IEC20000563 V2 EN-US
M15223-1 v19
10.5.2 Identification
GUID-E1720ADA-7F80-4F2C-82A1-EF2C9EF6A4B4 v1
alt
IEC10000053 V2 EN-US
Four step directional negative phase sequence overcurrent protection (NS4PTOC, (4612) ) has an
inverse or definite time delay independent for each step separately.
All IEC and ANSI time delayed characteristics are available together with an optional user defined
characteristic.
NS4PTOC (4612) can be set directional or non-directional independently for each of the steps.
NS4PTOC (4612) can be used as main protection for unsymmetrical fault; phase-phase short circuits,
phase-phase-ground short circuits and single phase ground faults.
NS4PTOC (4612) can also be used to provide a system backup for example, in the case of the primary
protection being out of service due to communication or voltage transformer circuit failure.
Directional operation can be combined together with corresponding communication logic in permissive
or blocking teleprotection scheme. The same logic as for directional zero sequence current can be used.
Current reversal and weak-end infeed functionality are available.
NS4PTOC (46I2)
I3P* TRIP
I3PDIR* TRST1
V3P* TRST2
BLOCK TRST3
BLKTR TRST4
BLK1 PICK UP
BLK2 PU_ST1
BLK3 PU_ST2
BLK4 PU_ST3
MULTPU1 PU_ST4
MULTPU2 PUFW
MULTPU3 PUREV
MULTPU4
ANSI10000054-1-en.vsd
ANSI10000054 V1 EN-US
10.5.5 Signals
PID-8148-INPUTSIGNALS v1
10.5.6 Settings
PID-8148-SETTINGS v1
Four step negative sequence overcurrent protection NS4PTOC (4612) function has the following three
“Analog Inputs” on its function block in the configuration tool:
These inputs are connected from the corresponding pre-processing function blocks in the Configuration
Tool within PCM600.
Four step negative sequence overcurrent protection NS4PTOC (46I2) function always uses negative
sequence current (I2) for its operating quantity. The negative sequence current is calculated from three-
phase current input within the IED. The pre-processing block calculates I2 from the first three inputs into
the pre-processing block by using the following formula:
1
I2 IA a IB a IC
2
where:
IA, IB, IC are fundamental frequency phasors of three individual phase currents.
a is so called operator which gives a phase shift of 120 deg, that is, a = 1∠120 deg
a2 similarly gives a phase shift of 240 deg, that is, a2 = 1∠240 deg
The phasor magnitude is used within the NS4PTOC (4612) protection to compare it with the set
operation current value of the four steps (Pickup1, Pickup2, Pickup3 or Pickup4). If the negative
sequence current is larger than the set operation current and the step is used in non-directional mode
a signal from the comparator for this step is set to true. This signal, without delay, activates the output
signal PU_STx (x=1 - 4) for this step and a common PICKUP signal.
A polarizing quantity is used within the protection to determine the direction to the fault (Forward/
Reverse).
Four step negative sequence overcurrent protection NS4PTOC (4612) function uses the voltage
polarizing method.
NS4PTOC (4612) uses the negative sequence voltage -V2 as polarizing quantity V3P. This voltage is
calculated from three phase voltage input within the IED. The pre-processing block calculates -V2 from
the first three inputs into the pre-processing block by using the following formula:
ANSIEQUATION00024 V2 EN-US
where:
VA, VB, VC are fundamental frequency phasors of three individual phase voltages.
To use this all three phase-to-ground voltages must be connected to three IED VT inputs.
This phasor is used together with the phasor of the operating current, in order to determine the direction
to the fault (Forward/Reverse).To enable voltage polarizing the magnitude of polarizing voltage must be
bigger than a minimum level defined by setting VpolMin.
Note that –V2 is used to determine the location of the fault. This ensures the required inversion of the
polarizing voltage within the function.
The individual steps within the protection can be set as non-directional. When this setting is selected it
is then possible via function binary input BLKx (where x indicates the relevant step within the protection)
to provide external directional control (that is, torque control) by for example using one of the following
functions if available in the IED:
Each overcurrent stage uses Operating Quantity I2 (negative sequence current) as measuring quantity.
Every of the four overcurrent stage has the following built-in facilities:
• Operating mode (Disabled/ Non-directional /Forward / Reverse). By this parameter setting the
operating mode of the stage is selected. Note that the directional decision (Forward/Reverse) is
not made within the overcurrent stage itself. The direction of the fault is determined in common
“Directional Supervision Element” described in the next paragraph.
• Negative sequence current pickup value.
• Type of operating characteristic (Inverse or Definite Time). By this parameter setting it is possible to
select Inverse or definite time delay for negative sequence overcurrent function. Most of the standard
IEC and ANSI inverse characteristics are available. For the complete list of available inverse curves,
refer to Chapter "Inverse characteristics"
• Type of reset characteristic (Instantaneous / IEC Reset /ANSI reset).By this parameter setting it is
possible to select the reset characteristic of the stage. For the complete list of available reset curves,
refer to Chapter "Inverse characteristics"
• Time delay related settings. By these parameter settings the properties like definite time delay,
minimum operating time for inverse curves, reset time delay and parameters to define user
programmable inverse curve are defined.
• Multiplier for scaling of the set negative sequence current pickup value by external binary signal. By
this parameter setting it is possible to increase negative sequence current pickup value when function
binary input MULTPUx has logical value 1.
Simplified logic diagram for one negative sequence overcurrent stage is shown in the following figure:
ANSI09000684 V1 EN-US
Figure 287: Simplified logic diagram for negative sequence overcurrent stage x , where x=1, 2, 3 or 4
NS4PTOC (4612) can be completely blocked from the binary input BLOCK. The pickup signals from
NS4PTOC (4612) for each stage can be blocked from the binary input BLKx. The trip signals from
NS4PTOC (4612) can be blocked from the binary input BLKTR.
At least one of the four negative sequence overcurrent steps must be set as directional
in order to enable execution of the directional supervision element and the integrated
directional comparison function.
The operating and polarizing quantity are then used inside the directional element, as shown in figure
288, to determine the direction of the fault.
Reverse
Area
AngleRCA Vpol=-V2
Forward
Area
Iop = I2
ANSI10000031-1-en.vsd
ANSI10000031 V1 EN-US
• Directional element is internally enable to trip as soon as Iop is bigger than 40% of INDirPU and the
directional condition is fulfilled in set direction.
• Relay characteristic angle AngleRCA which defines the position of forward and reverse areas in the
operating characteristic.
Directional comparison step, built-in within directional supervision element, set NS4PTOC (4612) output
binary signals:
1. PUFW=1 when tip of I2 phasor (operating quantity magnitude) is in forward area, see fig 288
(Operating quantity magnitude is bigger than setting INDirPU)
2. PUREV=1 when tip of I2 phasor (operating quantity magnitude) is in the reverse area, see fig 288.
(Operating quantity magnitude is bigger than 60% of setting INDirPU)
These signals must be used for communication based fault teleprotection communication schemes
(permissive or blocking).
Simplified logic diagram for directional supervision element with integrated directional comparison step is
shown in figure 289:
|IopDir|
a
a>b PUREV
b AND
REVERSE_Int
0.6
X
a
a>b
AND PUFW
IDirPU b
FORWARD_Int
X
0.4
FWD
AND FORWARD_Int
AngleRCA
polMethod=Voltage
OR
VPolMin
Characteristic
Directional
polMethod=Dual IPolMin
VPol T
I3PDIR
polMethod=Current 0.0 F
OR
VTPol
IPol AND REVERSE_Int
T RVS
0.0 F
VIPol
RNPol X STAGE1_DIR_Int
Complex T
STAGE2_DIR_Int
XNPol Number 0.0 F STAGE3_DIR_Int OR
STAGE4_DIR_Int
BLOCK AND
ANSI07000067-4-en.vsd
ANSI07000067 V4 EN-US
Figure 289: Simplified logic diagram for directional supervision element with integrated directional comparison step
GUID-E83AD807-8FE0-4244-A50E-86B9AF92469E v8
10.6.1 Identification
SEMOD172025-2 v4
In networks with high impedance grounding, the phase-to-ground fault current is significantly smaller
than the short circuit currents. Another difficulty for ground fault protection is that the magnitude of the
phase-to-ground fault current is almost independent of the fault location in the network.
Directional residual current can be used to detect and give selective trip of phase-to-ground faults in
high impedance grounded networks. The protection uses the residual current component 3I0 · cos φ,
where φ is the angle between the residual current and the residual voltage (-3V0), compensated with a
characteristic angle. Alternatively, the function can be set to strict 3I0 level with a check of angle φ.
Directional residual power can also be used to detect and give selective trip of phase-to-ground faults in
high impedance grounded networks. The protection uses the residual power component 3I0 · 3V0 · cos
φ, where φ is the angle between the residual current and the reference residual voltage, compensated
with a characteristic angle.
A normal non-directional residual current function can also be used with definite or inverse time delay.
A backup neutral point voltage function is also available for non-directional residual overvoltage
protection.
In an isolated network, that is, the network is only coupled to ground via the capacitances between the
phase conductors and ground, the residual current always has -90º phase shift compared to the residual
voltage (3V0). The characteristic angle is chosen to -90º in such a network.
In resistance grounded networks or in Petersen coil grounded, with a parallel resistor, the active residual
current component (in phase with the residual voltage) should be used for the ground fault detection. In
such networks, the characteristic angle is chosen to 0º.
As the magnitude of the residual current is independent of the fault location, the selectivity of the ground
fault protection is achieved by time selectivity.
When should the sensitive directional residual overcurrent protection be used and when should the
sensitive directional residual power protection be used? Consider the following:
• Sensitive directional residual overcurrent protection gives possibility for better sensitivity. The setting
possibilities of this function are down to 0.25 % of IBase, 1 A or 5 A. This sensitivity is in most cases
sufficient in high impedance network applications, if the measuring CT ratio is not too high.
• Sensitive directional residual power protection gives possibility to use inverse time characteristics. This
is applicable in large high impedance grounded networks, with large capacitive ground fault currents.
In such networks, the active fault current would be small and by using sensitive directional residual
power protection, the operating quantity is elevated. Therefore, better possibility to detect ground
faults. In addition, in low impedance grounded networks, the inverse time characteristic gives better
time-selectivity in case of high zero-resistive fault currents.
Phase
currents
IN
Phase
ground
voltages
VN
ANSI13000013-1-en.vsd
ANSI13000013 V1 EN-US
Overcurrent functionality uses true 3I0, i.e. sum of GRPxA, GRPxB and GRPxC. For 3I0 to be
calculated, connection is needed to all three phase inputs.
Directional and power functionality uses IN and VN. If a connection is made to GRPxN this signal is
used, else if connection is made to all inputs GRPxA, GRPxB and GRPxC the internally calculated sum
of these inputs (3I0 and 3V0) will be used.
SDEPSDE (67N)
I3P* TRIP
V3P* TRDIRIN
BLOCK TRNDIN
BLKTR TRVN
BLKTRDIR PICKUP
BLKNDN PUDIRIN
BLKVN PUNDIN
PUVN
PUFW
PUREV
CND
VNREL
ANSI07000032-2-en.vsd
ANSI07000032 V2 EN-US
10.6.4 Signals
PID-3892-INPUTSIGNALS v7
10.6.5 Settings
PID-3892-SETTINGS v7
The function is using phasors of the residual current and voltage. Group signals I3P and V3P containing
phasors of residual current and voltage which are taken from pre-processor blocks.
The sensitive directional ground fault protection has the following sub-functions included:
φ is defined as the angle between the residual current 3I0 and the reference voltage (|φ=ang(3I0)-
ang(Vref)|). The reference voltage (Vref) is the polarizing quantity which is used for directionality and is
defined as Vref = -3V0 e—jRCADir, that is -3V0 inversely rotated by the set characteristic angle RCADir.
RCADir is normally set equal to 0 in a high impedance grounded network with a neutral point resistor
as the active current component is appearing out on the faulted feeder only. RCADir is set equal to -90°
in an isolated network as all currents are mainly capacitive. The function operates when 3I0·cos φ gets
larger than the set value.
3I0
= ang(3I0) - ang(3Vref)
-3V0=Vref
3I0 cos
en06000648_ansi.vsd
ANSI06000648 V1 EN-US
3I0
3I0 cos
= ang(3I0) – ang(Vref)
-3V0
en06000649_ansi.vsd
ANSI06000649 V1 EN-US
For trip, the operating quantity 3I0 cos φ, the residual current 3I0, and the residual voltage 3V0 must be
larger than the set levels : INCosPhiPU, INRelPU and VNRelPU. Refer to the simplified logical diagram
in Figure 297.
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function picks up, binary output signals PICKUP and PUDIRIN are activated. If the output
signals PICKUP and PUDIRIN remain active for the set delay tDef the binary output signals TRIP and
TRDIRIN get activated. The trip from this sub-function has definite time delay.
ROADir is Relay Operating Angle. ROADir is identifying a window around the reference direction in
order to detect directionality. Figure 294 shows the restrictions made by the ROADir.
RCADir 0
3I0
Trip area
3V0 Vref
3I0 cos
ROADir
ANSI06000650-3-en.vsd
ANSI06000650 V3 EN-US
The function indicates forward/reverse direction to the fault. Reverse direction is defined as 3I0·cos (φ +
180°) ≥ the set value.
It is also possible to tilt the characteristic to compensate for current transformer angle error with a setting
RCAComp as shown in the Figure 295:
RCADir = 0º
Trip area
-3V0 =Vref
Instrument
transformer
angle error
RCAcomp
Characteristic after
angle compensation
ANSI06000651-2-en.vsd
ANSI06000651 V2 EN-US
φ is defined as the angle between the residual current 3I0 and the reference voltage (Vref = -3V0 e-jRCA)
compensated with the set characteristic angle RCADir (|φ=ang(3I0)—ang(Vref)|). The function operates
when 3I0 · 3V0 · cos φ gets larger than the set value SN>. Refer to the simplified logical diagram in
Figure 297.
For trip, the residual power 3I0 · 3V0 · cos φ, the residual current 3I0 and the release voltage 3V0, shall
be larger than the set levels (SN_PU, INRelPU and VNRelPU).
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function picks up, binary output signals PICKUP and PUDIRIN are activated. If the output
signals PICKUP and PUDIRIN remain active for the set delay tDef or after the inverse time delay (setting
TDSN) the binary output signals TRIP and TRDIRIN get activated.
The function shall indicate forward/reverse direction to the fault. Reverse direction is defined as 3I0 ·
3V0·cos (φ + 180°) ³ the set value.
This variant has the possibility of choice between definite time delay and inverse time delay.
The function will operate if the residual current is larger than the set value and the angle |φ = ang(3I0)-
ang(Vref)| is within the sector RCADir ± ROADir
RCA = 0º
ROA = 80º
Operate area
3I0
Vref=-3V0
ANSI06000652-2-en.vsd
ANSI06000652 V2 EN-US
For trip, Residual current 3I0 shall be larger than both INRelPU and INDirPU, and residual voltage 3V0
shall be larger than the VNRelPU. In addition, the angle φ shall be in the set area defined by ROADir
and RCADir. Refer to the simplified logical diagram in Figure 297.
Trip from this function can be blocked from the binary input BLKTRDIR.
When the function picks up, binary output signals PICKUP and PUDIRIN are activated. If the output
signals PICKUP and PUDIRIN remain active for the set delay tDef the binary output signals TRIP and
TRDIRIN get activated.
The function indicates forward/reverse direction to the fault. Reverse direction is defined as φ is within
the angle sector: RCADir + 180° ± ROADir
For all the directional functions there are directional pickup signals PUFW: fault in the forward direction,
and PUREV: fault in the reverse direction. Even if the directional function is set to operate for faults
in the forward direction, a fault in the reverse direction will give the pickup signal PUREV. Also if the
directional function is set to operate for faults in the reverse direction, a fault in the forward direction will
give the pickup signal PUFW.
This function will measure the residual current without checking the phase angle. The function will
be used to detect cross-country faults. This function can serve as alternative or backup to distance
protection with phase preference logic. To assure selectivity the distance protection can block the
non-directional ground fault current function via the input BLKNDN.
The non-directional function is using the calculated residual current, derived as sum of the phase
currents. This will give a better ability to detect cross-country faults with high residual current, also when
dedicated core balance CT for the sensitive ground fault protection will saturate.
This variant has the possibility of choice between definite time delay and inverse time delay (TimeChar
parameter). The inverse time delay shall be according to IEC 60255-3.
For trip, the residual current 3I0 shall be larger than the set level (INNonDirPU).
Trip from this function can be blocked from the binary input BLKNDN.
When the function picks up, binary output signal PUNDIN is activated. If the output signal PUNDIN
remains active for the set delay tINNonDir or after the inverse time delay the binary output signals TRIP
and TRNDIN get activated.
All the directional functions shall be released when the residual voltage gets higher than a set level
VNRelPU.
In addition, there is also a separate non-directional residual over voltage protection, with its own definite
time delay tVN and set level VN_PU.
For trip, the residual voltage 3V0 shall be larger than the set level (VN_PU).
Trip from this function can be blocked from the binary input BLKVN.
When the function picks up, binary output signal PUVN is activated. If the output signal PUVN is active
for the set delay tVNNonDir, the binary output signals TRIP and TRUN get activated. A simplified logical
diagram of the total function is shown in Figure 297.
INNonDirPU PUNDIN
0-t TRNDIN
0
PUVN
UN_PU
0-t TRVN
0
OpMODE=INcosPhi
Pickup_N
AND
INCosPhiPU
OpMODE=INVNCosPhi
AND OR AND PUDIRIN
INVNCosPhiPU t
SN
AND TRDIRIN
Phi in RCA +- ROA
TimeChar = InvTime
AND
OpMODE=IN and Phi
AND
TimeChar = DefTime
DirMode = Forw
AND OR
PUFW
Forw
DirMode = Rev
AND
Rev PUREV
en06000653_ansi.vsd
ANSI06000653 V1 EN-US
Figure 297: Simplified logical diagram of the sensitive ground fault current protection
SEMOD173350-2 v17
10.7.2 Identification
M17106-1 v7
The increasing utilization of the power system closer to the thermal limits has generated a need of a
thermal overload protection for power lines.
A thermal overload will often not be detected by other protection functions and the introduction of the
thermal overload protection can allow the protected circuit to trip closer to the thermal limits.
The three-phase current measuring protection has an I2t characteristic with settable time constant and
a thermal memory. The temperature is displayed in either Celsius or Fahrenheit, depending on whether
the function used is Thermal overload protection (Fahrenheit) LFPTTR (26) or Celsius (LCPTTR).
An alarm pickup gives early warning to allow operators to take action well before the line is tripped.
Estimated time to trip before operation, and estimated time to reclose after operation are presented.
LCPTTR (26)
I3P* TRIP
BLOCK BFI_3P
BLKTR ALARM
MULTPU LOCKOUT
AMBTEMP
SENSFLT
RESET
ANSI13000199 V3 EN-US
LFPTTR (26)
I3P* TRIP
BLOCK BFI_3P
BLKTR ALARM
MULTPU LOCKOUT
AMBTEMP
SENSFLT
RESET
ANSI13000301 V3 EN-US
10.7.5 Signals
PID-8003-INPUTSIGNALS v1
10.7.6 Settings
PID-8003-SETTINGS v1
The sampled analog phase currents are pre-processed and for each phase current the RMS value
is derived. These phase current values are fed to the thermal overload protection, one time constant
LFPTTR/LCPTTR (26) function. The temperature is displayed either in Celsius or Fahrenheit, depending
on whether LFPTTR/LCPTTR (26) function is selected.
From the largest of the three-phase currents a final temperature is calculated according to the
expression:
2
æ I ö
Q final =ç ÷÷ × Tref
ç I ref
è ø
EQUATION1167 V1 EN-US (Equation 121)
where:
I is the largest phase current,
Iref is a given reference current and
Tref is steady state temperature rise corresponding to Iref
The ambient temperature is added to the calculated final temperature. If this temperature is larger than
the set trip temperature level, TripTemp, a PICKUP output signal is activated.
æ Dt
ö
Qn = Qn -1 + ( Q final - Q n-1 ) × ç1 - e t ÷
-
è ø
EQUATION1168 V1 EN-US (Equation 122)
where:
Qn is the calculated present temperature,
Q n-1 is the calculated temperature at the previous time step,
Q final is the calculated final temperature with the actual current,
Dt is the time step between calculation of the actual temperature and
t is the set thermal time constant for the protected device (line or cable)
The actual temperature of the protected component (line or cable) is calculated by adding the ambient
temperature to the calculated temperature, as shown above. The ambient temperature can be taken
from a separate sensor or can be given a constant value. The used ambient temperature is available
as a real figure signal, TEMPAMB. The calculated component temperature is available as a real figure
signal, TEMP. The temperature of the component compared to the setting TripTemp is also available as
a real figure signal, TERMLOAD which indicates the thermal status compared to the trip level.
When the component temperature reaches the set alarm level AlarmTemp the output signal ALARM is
set. When the component temperature reaches the set trip level TripTemp the output signal TRIP is set.
There is also a calculation of the present time to trip with the present current. This calculation is only
performed if the final temperature is calculated to be above the operation temperature:
final trip
ttrip ln
final n
After a trip, caused by the thermal overload protection, there can be a lockout to reconnect the tripped
circuit. The output lockout signal LOCKOUT is activated when the device temperature is above the set
lockout release temperature setting ReclTemp.
The time to lockout release is calculated by the following cooling time calculation. The thermal content of
the function can be reset with input RESET.
æQ - Qlockout _ release ö
tlockout _ release = -t × ln ç final ÷÷
ç Q final - Q n
è ø
EQUATION1170 V1 EN-US (Equation 124)
In the above equation, the final temperature is equal to the set or measured ambient temperature. The
calculated time to reset of lockout is available as a real figure signal, TENRECL. This signal is enabled
when the LOCKOUT output is activated.
In some applications the measured current can involve a number of parallel lines. This is often used
where one bay connects several parallel cables. By setting the parameter IMult to the number of parallel
lines (cables) the actual current on one line is used in the protection algorithm by dividing the measured
current by the total number of cables. To activate this option the input MULTPU must be activated.
The protection has a reset input: RESET. By activating this input the calculated temperature is reset
to its default initial value. This is useful during testing when secondary injected current has given a
calculated “false” temperature level.
PICKUP
Final Temp > Trip Temp
TEMP
Calculation of actual
temperature
AMBTEMP ALARM
Actual Temp > Alarm Temp
I3P
Calculation of final
temperature
ENMULT
TRIP
LOCKOUT
Lockout logic
TTRIP
Calculation of time to trip
BLKTR
TENRECL
Calculation of time to reset
of lockout
ANSI09000637-3-en.vsd
ANSI09000637 V3 EN-US
10.8.2 Identification
M14878-1 v5
SYMBOL-U V1 EN-US
Breaker failure protection (CCRBRF) (50BF) ensures a fast backup tripping of the surrounding breakers
in case the own breaker fails to open. CCRBRF (50BF) measurement criterion can be current based, CB
position based or an adaptive combination of these two conditions.
A current based check with extremely short reset time is used as check criterion to achieve high security
against inadvertent operation.
CB position check criteria can be used where the fault current through the breaker is small.
CCRBRF provides three different options to select how t1 and t2 timers are run:
CCRBRF (50BF) can be single- or three- phase initiated to allow its use with single pole tripping
applications. For the three-phase application of the CCRBRF (50BF) the current criteria can be set to
operate only if “2 elements operates out of three phases and neutral” for example; two phases or one
phase plus the residual current pickups. This gives a higher security to the backup trip command.
The CCRBRF (50BF) function can be programmed to give a single- or three- phase retrip to its own
breaker to avoid unnecessary tripping of surrounding breakers at an incorrect initiation due to mistakes
during testing.
CCRBRF (50BF)
I3P* TRBU
BLOCK TRBU2
PICK UP TRRET
BFI_A TRRET_A
PU_B TRRET_B
BFI_C TRRET_C
52A_A CBALARM
52A_B STALARM
52A_C
52FAIL
ANSI18001006-1-en.vsd
ANSI18001006 V1 EN-US
10.8.5 Signals
PID-7233-INPUTSIGNALS v1
10.8.6 Settings
PID-7233-SETTINGS v1
Breaker failure protection CCRBRF (50BF) is initiated from the protection trip command, either from
protection functions within the IED or from external protection devices.
To this function the three-phase current input and/or change to: the breaker normally open auxiliary
contact (i.e. "52a" or "closed") shall be connected. On OHL feeders where single pole auto-reclosing is
used, auxiliary contact from each CB pole shall be connected separately
The input START signal (i.e. initiate signal) can be phase selective or common (for all three phases).
Phase selective start signals enable single pole retrip functionality. This means that a second attempt to
open the same breaker can be done phase-selective. The retrip attempt is made after a set time delay
t1. For transmission lines, single pole trip and auto-reclosing is often used. The retrip function can be
phase selective if it is initiated from the phase selective line protection.
The retrip function can be done with or without FunctionMode check. With this check, the retrip is only
performed if the circuit breaker is still seen as closed when t1 timer has elapsed.
The INITIATE signal will also start the backup trip timer. The function detects the successful breaker
opening, either by detection of low current through RMS evaluation and a special adapted current
algorithm or by monitoring the circuit breaker status using normally open auxiliary contact from the
breaker. The special algorithm enables a very fast detection of successful breaker opening, which is,
fast resetting of the current measurement. If the function has not detected breaker opening before the
backup timer has run-out its time a backup trip is initiated.
• Three phase (i.e. common) start/initiation via input INITIATE or individual start/initiation per phase by
using phase segregated inputs STLx.
• The minimum length of the retrip pulse, the backup trip pulse and the second backup trip pulse are
settable. This pulse duration is defined by a parameter setting tPulse. The retrip pulse, the backup trip
pulse and the second backup trip pulse will however sustain as long as there is an indication of closed
breaker.
• If the current detection is used it is possible to use three different options: 1 out of 3 where it is
sufficient to detect failure to open (high current) in one pole, 1 out of 4 where it is sufficient to detect
failure to open (high current) in one pole or high residual current and 2 out of 4 where at least two
currents (phase current and/or residual current) shall be high for breaker failure detection.
• The current detection level for the residual current can be set different from the setting of phase
current detection.
• It is possible to have different backup time delays for single-phase faults and for multi-phase faults.
• It is possible to have instantaneous backup trip function if the circuit breaker is incapable to clear
faults, for example, at low gas pressure. This will happen when input signal 52FAIL has logical value
one and timer tCBAlarm has expired. This situation will be indicated via output signal CBALARM.
The selection of measurement criterion is done with setting parameter FunctionMode, to determine if the
breaker has opened or not:
• Option 1 - Current: Compares the measured phase current magnitude to setting IPPU (operate phase
current level in % of IBase), and the measured residual current magnitude to setting IN> (Operate
residual current level in % of IBase). Criterion is active (i.e. breaker did not open yet) if the measured
current magnitudes are higher than the set values.
• Option 2 - CB Pos: This criterion is active (i.e. breaker did not open yet in phase Lx) if the binary input
CBCLDLx has logical value one. Thus function simply follows the status of CB pole normally open
auxiliary contact (i.e. "52a" or "closed") which shall be connected to this input.
If TRBU has been given and CBCLDLx still has value one, TRBU and TRRET will internally be reset
intentionally after approximately 10 seconds. Another way of resetting TRBU and TRRET is either to
shortly activate BLOCK input or setting CCRBRF to blocked when the IED is in TestMode.
• Option 3 - Current or CB Pos: It uses a combination of Current or CB Pos criteria. Note that Current
criterion will be then always used, while the CB Pos criterion will be only enabled and used if current is
smaller than set value I>BlkCBPos at the moment when external INITIATE signal has been received. It
is recommended to set value for I>BlkCBPos higher than the set value for IPPU.
If TRBU has been given and CBCLDLx still has value one and if the CB Pos criterion is used,TRBU
and TRRET will internally be reset intentionally after approximately 10 seconds. Another way of
resetting TRBU and TRRET is either to shortly activate BLOCK input or setting CCRBRF to blocked
when the IED is in TestMode.
By the setting StartMode it is possible to select how t1 and t2 timers are run and consequently how
output commands are given from the function:
stopped by removing the external INITIATE signal. Function can be started again only when all of the
following three timers t1, t2 and fixed timer of 150 ms in function internal design has expired and the
measurement criterion defined by parameter FunctionMode has been deactivated, see Figure 301.
When one of the two “follow modes” is used, there is a settable timer tStartTimeout which will block
the external INITIATE input signal when it times-out. This will automatically also reset the t1 and t2
timers and consequently prevent any backup trip command. At the same time the STALARM output from
the function will have logical value one. To reset this signal external INITIATE signal shall be removed.
This is done in order to prevent unwanted operation of the breaker failure function for cases where a
permanent INITIATE signal is given by mistake (e.g. due to a fault in the station battery system). Note
that any backup trip command will inhibit running of tStartTimeout timer.
The BLOCK signal overrides any StartMode condition and resets INITIATE signal, running of t1 and t2
timers and all function outputs.
30ms t1 30ms
PICKUP OR TRRET
S Q t AND
t2 30ms
OR TRBU
t AND
Current Check
CB Position Check OR
150ms
AND
t
NOT
ANSI 18001002-1-en.vsdx
ANSI18001002 V1 EN-US
t1
PICKUP OR TRRET
t AND
Current Check
CB Position Check OR
t2
TRBU
t AND
OR
ANSI18001003-1-en.vsdx
ANSI18001003 V1 EN-US
PICKUP t1 TRRET
AND t
Current Check
CB Position Check OR t2 TRBU
t
ANSI18001004-1-en.vsdx
ANSI18001004 V1 EN-US
The BuTripMode setting defines how many measurement elements must operate, when current criterion
is used, to determine if the CB is opened or not:
Note that it is possible to set several timers for the backup trip as described below:
1. Timer t2 is used when function is started in one phase only (i.e. for single-phase to ground fault on
an OHL (Over Head Lines) when single-pole auto-reclosing is used).
2. Timer t2MPh is used when function is started in at least two phases. This will allow to have shorter
backup trip times for a multi-phase fault on an OHL Note that for a protected object which are
always tripped three-phase (e.g. transformers, generators, reactors, cables, etc.) this timer shall
always be set to the same value as t2 timer.
3. Timer t3 can be used to give a second backup trip command. It can be used in stations having small
DC battery which is not capable to trip all surrounding breakers at once. Note that t3 timer will only
start when t2 timer expires.
• Off: The retrip command to the own circuit breaker is permanently disabled.
• UseFunctionMode: Retrip command to the own circuit breaker is given only if measurement
criterion defined by setting parameter FunctionMode is still active when set timer t1 expires (e.g. if
FunctionMode=Current and current magnitude is higher than set value IPPU when t1 expires, the
retrip command will be issued).
• Always: Retrip command to the own circuit breaker is given always when set timer t1 expires without
any further checks.
The simplified logic for the function is given in the following figures.
StartMode
LatchedStart
FollowStart
1 FollowStart&Mode OR
PICKUP 30ms
int startA
BFI_A OR AND S Q
BLOCK
NOT
int reset
OR R
NOT
TRBU
NOT int startAlarmA
tStartTimeout
AND t NOT
AND AND int startAlarmB STALARM
From other OR
phases int startAlarmC
ANSI18001005-1-en.vsdx
ANSI18001005 V1 EN-US
Figure 304: Start logic for all three Function Modes of operation
IA
a
a>b NOT
IPPU b
FunctionMode
Current
CB Pos OR AND int reset
OR
1
Current or CB Pos 150 ms
int startA
t
OR AND
t1
t
t2
t OR
t2MPh
t
AND
52A_A
NOT
ANSI18001007-1-en.vsdx
ANSI18001007 V1 EN-US
StartMode
LatchedStart
FollowStart
1 FollowStart&Mode OR AND
int retrip
currPh1Check
CB Position Check OR 30ms
AND t1 OR AND
int startA t OR
t1
t
BLOCK
RetripMode
Off tPulse
TRRETA
UseFunctionMode AND OR AND
1
Always
TRRETB TRRET
TRRETC
OR
ANSI18001008-2-en.vsdx
ANSI18001008 V2 EN-US
StartMode
LatchedStart
1 FollowStart
FollowStart&Mode OR AND
currCheck
CB Position Check OR
backupTripA
t2
AND t 30ms
OR AND
OR OR
int startA
BLOCK
t3
t TRBU2
OR
AND
tPulse
ANSI18001009 V2 EN-US
When the function Start mode is set to LatchedStart and the function mode is set CB Pos, Re-trip,
and Backup trip will internally operate and latch. To reset these two signals the breaker position has to
indicate that the CB is open.
To avoid continuous lockout of Re-trip and Back up trip signals, the signals are rested internally under
the following conditions:
1. When the function blocking input is activated breaker position input (CBCLDLxx) will internally be
forced to zero in all phases (that is simulating that CB is open), which will reset Re-trip(TRRET) and
back up trip (TRBU) output signals.
2. If TRBU is active for 10 seconds, then the activated breaker position input (CBCLDLxx) will internally
be forced to zero which will reset both RETRIP and TRBU.
3. When using FunctionMode=Current/CB pos, the same behavior is applicable only when the CB pos
part is active; that is, when the measured current is below the set value I>BlkCBPos.
M12353-1 v16
10.9.2 Identification
M17108-1 v2
3I>STUB
SYMBOL-T V1 EN-US
When a power line is taken out of service for maintenance and the line disconnector is opened in
multi-breaker arrangements the voltage transformers will mostly be outside on the disconnected part.
The primary line distance protection will thus not be able to trip and must be blocked.
The stub protection (STBPTOC) (50STB) covers the zone between the current transformers and the
open disconnector. The three-phase instantaneous overcurrent function is released from a normally
closed, 89b auxiliary contact on the line disconnector.
STBPTOC (50STB)
I3P* TRIP
BLOCK PICKUP
BLKTR
ENABLE
ANSI05000678-2-en.vsd
ANSI05000678 V2 EN-US
10.9.5 Signals
PID-7754-INPUTSIGNALS v1
10.9.6 Settings
PID-7754-SETTINGS v1
The sampled analog phase currents are pre-processed in a discrete Fourier filter (DFT) block. From
the fundamental frequency components of each phase current the RMS value of each phase current is
derived. These phase current values are fed to a comparator in the stub protection function STBPTOC
(50STB). In a comparator the RMS values are compared to the set operating current value of the
function IPickup.
If a phase current is larger than the set operating current the signal from the comparator for this phase is
activated. This signal will, in combination with the release signal from either line disconnector (RELEASE
input) and ReleaseMode is set to Release or ReleaseMode is set to Continuous activates START signal
and timer tDelay. The output signal TRIP activates, if the fault current remains during the set timer
tDelay.
The function can be blocked by activation of the BLOCK input. Also, activation of BLKTR resets TRIP
output.
BLOCK
I3P* IL1
a
IL2 a>b
IL3 b
AND
PICKUP
1
a
a>b tDelay
b TRIP
AND t AND
a
a>b
I> b
AND
ENABLE
AND
ReleaseMode = Release 1
ReleaseMode = Continuous
BLKTR
ANSI05000731 V2 EN-US
From the measured three-phase currents, various types of measurement modes such as DFT, Peak,
and Peak-to-peak can be selected for the BRPTOC operation.
Peak and Peak-to-Peak measurement mode allow this function to be used as instantaneous over-
current protection as well. If required by application, short time delay can also be applied.
BRPTOC can be used for different line and transformer protection applications. If required, it can also be
used to supervise on-load tap-changer operation.
BRPTOC (50)
I3P* TRIP
BLOCK BFI_3P
BLKTR PU_A
ENABLE PU_B
PU_C
ANSI21000231 V2 EN-US
10.10.5 Signals
PID-7755-INPUTSIGNALS v2
PID-7755-OUTPUTSIGNALS v2
10.10.6 Settings
PID-7755-SETTINGS v2
Using a parameter setting MeasType within the general settings for the function BRPTOC, it is possible
to select the type of the measurements such as DFT, Peak, and Peak-to-peak used for overcurrent
operation.
If the DFT option is selected, only the RMS value of the fundamental frequency component of each
phase current is derived. The influence of the DC current component and higher harmonic current
components are completely suppressed.
The peak-to-peak measurement efficiently suppress the DC current component from the measured
phase currents. On the contrary, when Peak measurement mode is selected, it allows the DC current
component into the measurement signal for the BRPTOC function.
If the Peak/Peak-to-peak option is selected, RMS equivalent phase currents are derived and therefore,
the set value of I> is remained intact irrespective of any type of the measurement mode.
These phase current values are fed to a comparator in the overcurrent protection with binary release
function BRPTOC. In a comparator, the RMS values are compared to the set operating current value of
the function I>.
If a phase current is larger than the set operating current, comparator output signal for this phase will
be high. This signal will, in combination with the release signal (RELEASE input), activate the timer for
the TRIP signal. If the current magnitude remains high during the timer tdelay, the TRIP output signal is
activated. The function can be blocked by activation of the BLOCK input.
I3P* IL1
a
IL2 a>b
IL3 b PU_A
AND
a
a>b
b PU_B
AND
a
a>b
I> b PU_C
AND
ENABLE BFI_3P
1
BLOCK
tDelay
TRIP
t AND
BLKTR
GUID-B1135912-9BFA-4933-B6BD-A6205A3A5D83 V1 EN-US
Figure 310: Simplified logic diagram for overcurrent protection with binary release
10.11.1 Identification
M14888-1 v4
PD
SYMBOL-S V1 EN-US
An open phase can cause negative and zero sequence currents which cause thermal stress on rotating
machines and can cause unwanted operation of zero sequence or negative sequence current functions.
Normally the own breaker is tripped to correct such a situation. If the situation warrants the surrounding
breakers should be tripped to clear the unsymmetrical load situation.
The Pole discrepancy protection function (CCPDSC (52PD)) operates based on information from
auxiliary contacts of the circuit breaker for the three phases with additional criteria from unsymmetrical
phase currents when required.
CCPDSC (52PD)
I3P* TRIP
BLOCK PICK UP
BLKDBYAR
CLOSECMD
OPENCMD
EXTPDIND
52B_A
52A_A
52B_B
52A_B
52B_C
52A_C
ANSI13000305-2-en.vsdx
ANSI13000305 V2 EN-US
10.11.4 Signals
PID-3525-INPUTSIGNALS v8
10.11.5 Settings
PID-3525-SETTINGS v8
C.B.
52a
52a
+
52a
52b
ANSI05000287 V1 EN-US
This binary signal is connected to a binary input of the IED. The appearance of this signal will pickup a
timer that will give a trip signal after the set time delay.
There is also a possibility to connect all phase selective auxiliary contacts (phase contact open and
phase contact closed) to binary inputs of the IED, see figure 313.
C.B.
+ 52b
poleOneOpened from C.B.
52b poleTwoOpened from C.B.
52b poleThreeOpened from C.B.
en05000288_ansi.vsd
ANSI05000288 V1 EN-US
In this case the logic is realized within the function. If the inputs are indicating pole discrepancy the trip
timer is started. This timer will give a trip signal after the set delay.
Pole discrepancy can also be detected by means of phase selective current measurement. The sampled
analog phase currents are pre-processed in a discrete Fourier filter (DFT) block. From the fundamental
frequency components of each phase current the RMS value of each phase current is derived. The
smallest and the largest phase current are derived. If the smallest phase current is lower than the setting
CurrUnsymPU times the largest phase current the settable trip timer (tTrip) is started. The tTrip timer
gives a trip signal after the set delay. The TRIP signal is a pulse 150 ms long. The current based pole
discrepancy function can be set to be active either continuously or only directly in connection to breaker
open or close command.
The function also has a binary input that can be configured from the autoreclosing function, so that
the pole discrepancy function can be blocked during sequences with a single pole open if single pole
autoreclosing is used.
M13946-3 v7
BLOCK
OR
BLKDBYAR
PolPosAuxCont
AND
52b_A
52a_A
52b_B Pole
52a_B Disc repancy
52b_C detection
52a_C 150 ms
0- t TRIP
AND
0
OR
PD signal from CB
AND
EXTPDIND
CLOSECMD t+ 200 ms
OR
OPENCMD
AND
Unsymmetry current
detection
en 05000747_ansi.vsd
ANSI05000747 V1 EN-US
Figure 314: Simplified block diagram of pole discrepancy function CCPDSC (52PD) - contact and current based
• The IED is in TEST mode and CCPDSC (52PD) has been blocked from the local HMI
• The input signal BLOCK is high
• The input signal BLKDBYAR is high
The BLOCK signal is a general purpose blocking signal of the pole discrepancy protection. It can be
connected to a binary input in the IED in order to receive a block command from external devices or can
be software connected to other internal functions in the IED itself in order to receive a block command
from internal functions. Through OR gate it can be connected to both binary inputs and internal function
outputs.
The BLKDBYAR signal blocks the pole discrepancy operation when a single phase autoreclosing cycle
is in progress. It can be connected to the output signal 1PT1 on SMBRREC (79) function block. If the
autoreclosing function is an external device, then BLKDBYAR has to be connected to a binary input in
the IED and this binary input is connected to a signalization “1phase autoreclosing in progress” from the
external autoreclosing device.
If the pole discrepancy protection is enabled, then two different criteria can generate a trip signal TRIP:
If one or two poles of the circuit breaker have failed to open or to close the pole discrepancy status,
then the function input EXTPDIND is activated from the pole discrepancy signal derived from the circuit
breaker auxiliary contacts (one NO contact for each phase connected in parallel, and in series with one
NC contact for each phase connected in parallel) and, after a settable time interval tTrip (0-60 s), a 150
ms trip pulse command TRIP is generated by the Polediscrepancy function (52PD).
• any phase current is lower than CurrUnsymPU of the highest current in the three phases.
• the highest phase current is greater than CurrRelPU of IBase.
If these conditions are true, an unsymmetrical condition is detected and the internal signal INPS is
turned high. This detection is enabled to generate a trip after a set time delay tTrip if the detection occurs
in the next 200 ms after the circuit breaker has received a command to open trip or close and if the
unbalance persists. The 200 ms limitation is for avoiding unwanted operation during unsymmetrical load
conditions.
The pole discrepancy protection is informed that a trip or close command has been given to the circuit
breaker through the inputs CLOSECMD (for closing command information) and OPENCMD (for opening
command information). These inputs can be connected to terminal binary inputs if the information are
generated from the field (that is from auxiliary contacts of the close and open push buttons) or may be
software connected to the outputs of other integrated functions (that is close command from a control
function or a general trip from integrated protections).
10.12.1 Identification
SEMOD158941-2 v5
The task of a generator in a power plant is to convert mechanical energy available as a torque on a
rotating shaft to electric energy.
Sometimes, the mechanical power from a prime mover may decrease so much that it does not cover
bearing losses and ventilation losses. Then, the synchronous generator becomes a synchronous motor
and starts to take electric power from the rest of the power system. This operating state, where
individual synchronous machines operate as motors, implies no risk for the machine itself. If the
generator under consideration is very large and if it consumes lots of electric power, it may be desirable
to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous state. The task of the low
forward power protection is to protect the turbine and not to protect the generator itself.
Figure 315 illustrates the low forward power and reverse power protection with underpower and
overpower functions respectively. The underpower IED gives a higher margin and should provide better
dependability. On the other hand, the risk for unwanted operation immediately after synchronization may
be higher. One should set the underpower IED to trip if the active power from the generator is less than
about 2%. One should set the overpower IED to trip if the power flow from the network to the generator
is higher than 1% depending on the type of turbine.
When IED with a metering class input CTs is used pickup can be set to more sensitive value (e.g.0,5%
or even to 0,2%).
Trip
Q Q
Trip
Line Line
Margin Margin
P P
ANSI06000315-1-en.vsd
ANSI06000315 V1 EN-US
GUPPDUP (37)
I3P* TRIP
V3P* TRIP1
BLOCK TRIP2
BLOCK1 PICKUP
BLOCK2 PICKUP1
PICKUP2
P
PPERCENT
Q
QPERCENT
ANSI07000027-2-en.vsd
ANSI07000027 V2 EN-US
10.12.4 Signals
PID-3709-INPUTSIGNALS v6
PID-3709-OUTPUTSIGNALS v6
10.12.5 Settings
PID-3709-SETTINGS v6
Chosen current
phasors P
P = POWRE
Q = POWIM
ANSI06000438-2-en.vsd
ANSI06000438 V2 EN-US
The function will use voltage and current phasors calculated in the pre-processing blocks. The apparent
complex power is calculated according to chosen formula as shown in table 330.
The active and reactive power is available from the function and can be used for monitoring and fault
recording.
The component of the complex power S = P + jQ in the direction Angle1(2) is calculated. If this angle is
0° the active power component P is calculated. If this angle is 90° the reactive power component Q is
calculated.
The calculated power component is compared to the power pick up setting Power1(2). For directional
underpower protection, a pickup signal PICKUP1(2) is activated if the calculated power component is
smaller than the pick up value. For directional overpower protection, a pickup signal PICKUP1(2) is
activated if the calculated power component is larger than the pick up value. After a set time delay
TripDelay1(2) a trip TRIP1(2) signal is activated if the pickup signal is still active. At activation of any
of the two stages a common signal PICKUP will be activated. At trip from any of the two stages also a
common signal TRIP will be activated.
To avoid instability there is a settable hysteresis in the power function. The absolute hysteresis of
the stage1(2) is Hysteresis1(2) = abs (Power1(2) + drop-power1(2)). For generator low forward power
protection the power setting is very low, normally down to 0.02 p.u. of rated generator power. The
hysteresis should therefore be set to a smaller value. The drop-power value of stage1 can be calculated
with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) + Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-power1(2) would be too
small. In such cases, the hysteresis1 greater than (0.5 · Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value, the function will reset after a set time
DropDelay1(2). The reset means that the pickup signal will drop out and that the timer of the stage will
reset.
In order to minimize the influence of the noise signal on the measurement it is possible to introduce a
recursive, low pass filtering of the measured values for S (P, Q). This will make slower measurement
response to the step changes in the measured quantity. Filtering is performed in according to the
following recursive formula:
S = TD ⋅ SOld + (1 − TD ) ⋅ SCalculated
EQUATION1959-ANSI V1 EN-US (Equation 135)
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
SCalculated is the new calculated value in the present execution cycle
TD is settable parameter by the end user which influence the filter properties
Default value for parameter TD is 0.00. With this value the new calculated value is immediately given
out without any filtering (that is without any additional delay). When TD is set to value bigger than 0, the
filtering is enabled. A typical value for TD=0.92 in case of slow operating functions.
Measured currents and voltages used in the Power function can be calibrated to get class 0.5 measuring
accuracy. This is achieved by amplitude and angle compensation at 5, 30 and 100% of rated current and
voltage. The compensation below 5% and above 100% is constant and linear in between, see example
in figure 318.
Magnitude
% of In compensation
+10
IMagComp5 Measured
IMagComp30 current
IMagComp100
5 30 100 % of In
0-5%: Constant
-10 5-30-100%: Linear
>100%: Constant
Degrees Angle
compensation
+10
IAngComp30 Measured
current
IAngComp5
IAngComp100
5 30 100 % of In
-10
ANSI05000652_3_en.vsd
ANSI05000652 V3 EN-US
The first current and voltage phase in the group signals will be used as reference and the amplitude and
angle compensation will be used for related input signals.
Analog outputs (Monitored data) from the function can be used for service values or in the disturbance
report. The active power is provided as MW value: P, or in percent of base power: PPERCENT. The
reactive power is provided as Mvar value: Q, or in percent of base power: QPERCENT.
SEMOD175152-2 v11
10.13.1 Identification
SEMOD176574-2 v4
The task of a generator in a power plant is to convert mechanical energy available as a torque on a
rotating shaft to electric energy.
Sometimes, the mechanical power from a prime mover may decrease so much that it does not cover
bearing losses and ventilation losses. Then, the synchronous generator becomes a synchronous motor
and starts to take electric power from the rest of the power system. This operating state, where
individual synchronous machines operate as motors, implies no risk for the machine itself. If the
generator under consideration is very large and if it consumes lots of electric power, it may be desirable
to disconnect it to ease the task for the rest of the power system.
Often, the motoring condition may imply that the turbine is in a very dangerous state. The task of the
reverse power protection is to protect the turbine and not to protect the generator itself.
Figure 319 illustrates the low forward power and reverse power protection with underpower and
overpower functions respectively. The underpower IED gives a higher margin and should provide better
dependability. On the other hand, the risk for unwanted operation immediately after synchronization may
be higher. One should set the underpower IED to trip if the active power from the generator is less than
about 2%. One should set the overpower IED to trip if the power flow from the network to the generator
is higher than 1%.
When IED with a metering class input CTs is used pickup can be set to more sensitive value (e.g.0,5%
or even to 0,2%).
Trip
Q Q
Trip
Line Line
Margin Margin
P P
ANSI06000315-1-en.vsd
ANSI06000315 V1 EN-US
Figure 319: Reverse power protection with underpower IED and overpower IED
GOPPDOP (32)
I3P* TRIP
V3P* TRIP1
BLOCK TRIP2
BLOCK1 PICKUP
BLOCK2 PICKUP1
PICKUP2
P
PPERCENT
Q
QPERCENT
ANSI07000028-2-en.vsd
ANSI07000028 V2 EN-US
10.13.4 Signals
PID-3710-INPUTSIGNALS v7
10.13.5 Settings
PID-3710-SETTINGS v7
Chosen current
phasors P
P = POWRE
Q = POWIM
ANSI06000567-2-en.vsd
ANSI06000567 V2 EN-US
The function will use voltage and current phasors calculated in the pre-processing blocks. The apparent
complex power is calculated according to chosen formula as shown in table 338.
The active and reactive power is available from the function and can be used for monitoring and fault
recording.
The component of the complex power S = P + jQ in the direction Angle1(2) is calculated. If this angle is
0° the active power component P is calculated. If this angle is 90° the reactive power component Q is
calculated.
The calculated power component is compared to the power pick up setting Power1(2). A pickup signal
PICKUP1(2) is activated if the calculated power component is larger than the pick up value. After a set
time delay TripDelay1(2) a trip TRIP1(2) signal is activated if the pickup signal is still active. At activation
of any of the two stages a common signal PICKUP will be activated. At trip from any of the two stages
also a common signal TRIP will be activated.
To avoid instability there is a settable hysteresis in the power function. The absolute hysteresis of the
stage1(2) is Hysteresis1(2) = abs (Power1(2) – drop-power1(2)). For generator reverse power protection
the power setting is very low, normally down to 0.02 p.u. of rated generator power. The hysteresis
should therefore be set to a smaller value. The drop-power value of stage1 can be calculated with the
Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) – Hysteresis1(2)
For small power1 values the hysteresis1 may not be too big, because the drop-power1(2) would be too
small. In such cases, the hysteresis1 greater than (0.5 · Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value the function will reset after a set time
DropDelay1(2). The reset means that the pickup signal will drop out ant that the timer of the stage will
reset.
In order to minimize the influence of the noise signal on the measurement it is possible to introduce the
recursive, low pass filtering of the measured values for S (P, Q). This will make slower measurement
response to the step changes in the measured quantity. Filtering is performed in accordance with the
following recursive formula:
S = k × SOld + (1 - k ) × SCalculated
EQUATION1959 V1 EN-US (Equation 145)
Where
S is a new measured value to be used for the protection function
Sold is the measured value given from the function in previous execution cycle
SCalculated is the new calculated value in the present execution cycle
k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is immediately given out
without any filtering (that is, without any additional delay). When k is set to value bigger than 0, the
filtering is enabled. A typical value for k = 0.92 in case of slow operating functions.
Measured currents and voltages used in the Power function can be calibrated to get class 0.5 measuring
accuracy. This is achieved by amplitude and angle compensation at 5, 30 and 100% of rated current and
voltage. The compensation below 5% and above 100% is constant and linear in between, see example
in figure 322.
Magnitude
% of In compensation
+10
IMagComp5 Measured
IMagComp30 current
IMagComp100
5 30 100 % of In
0-5%: Constant
-10 5-30-100%: Linear
>100%: Constant
Degrees Angle
compensation
+10
IAngComp30 Measured
current
IAngComp5
IAngComp100
5 30 100 % of In
-10
ANSI05000652_3_en.vsd
ANSI05000652 V3 EN-US
The first current and voltage phase in the group signals will be used as reference and the amplitude and
angle compensation will be used for related input signals.
Analog outputs from the function can be used for service values or in the disturbance report. The active
power is provided as MW value: P, or in percent of base power: PPERCENT. The reactive power is
provided as Mvar value: Q, or in percent of base power: QPERCENT.
SEMOD175159-2 v9
10.14.2 Identification
SEMOD172362-2 v2
Conventional protection functions cannot detect the broken conductor condition. Broken conductor
check BRCPTOC (46) function, consisting of continuous phase selective current unsymmetrical check
on the line where the IED is connected, gives an alarm or trip at detecting broken conductors.
BRCPTOC (46)
I3P* TRIP
BLOCK PICKUP
BLKTR
ANSI07000034-2-en.vsd
ANSI07000034 V2 EN-US
10.14.5 Signals
PID-8008-INPUTSIGNALS v1
PID-8008-OUTPUTSIGNALS v1
10.14.6 Settings
PID-8008-SETTINGS v1
Broken conductor check (BRCPTOC, 46) detects a broken conductor condition by detecting the
asymmetry between currents in the three phases. The current-measuring elements continuously
measure the three-phase currents.
The current asymmetry signal output PICKUP is set on after 50.0 ms if:
• The difference in currents between the phase with the lowest current and the phase with the highest
current is greater than set percentage Pickup_ub of the highest phase current
• The lowest phase current is below 50% of the minimum setting value Pickup_PH
The third condition is included to avoid problems in systems involving parallel lines. If a conductor
breaks in one phase on one line, the parallel line will experience an increase in current in the same
phase. This might result in the first two conditions being satisfied. If the unsymmetrical detection lasts for
a period longer than the set time tOper, the TRIP output is activated.
The simplified logic diagram of the broken conductor check function is shown in Figure
• The IED is in TEST status and the function has been blocked from the local HMI test menu
(BlockBRC=Yes).
• The input signal BLOCK is high.
The BLOCK input can be connected to a binary input of the IED in order to receive a block command
from external devices, or can be software connected to other internal functions of the IED itself to
receive a block command from internal functions.
The output trip signal TRIP is a three-phase trip. It can be used to command a trip to the circuit breaker
or for alarm purpose only.
TEST
TEST-ACTIVE
AND
BlockBRC = Yes
50.0 ms BRC--PICKUP
0
Function Enable
OR
0-tOper
BRC--TRIP
AND
Unsymmetrical 0
Current Detection
PU_ub
IA<50%Pickup_PN
IB<50%Pickup_PN OR
IC<50%Pickup_PN
IEC07000123-3-en.vsd
IEC07000123 V3 EN-US
Figure 324: Simplified logic diagram for Broken conductor check BRCPTOC (46)
SEMOD175200-2 v10
Voltage-restrained time overcurrent protection (VRPVOC, 51V) function can be used as generator
backup protection against short-circuits.
The overcurrent protection feature has a settable current level that can be used either with definite time
or inverse time characteristic. Additionally, it can be voltage controlled/restrained.
One undervoltage step with definite time characteristic is also available within the function in order to
provide functionality for overcurrent protection with undervoltage seal-in.
VRPVOC (51V)
I3P* TRIP
V3P* TROC
BLOCK 27 Trip
BLKOC PICKUP
BLKUV PU_OC
27 PU
ANSI14000056-1-en.vsd
ANSI12000184 V2 EN-US
10.15.4 Signals
PID-8153-INPUTSIGNALS v1
10.15.5 Settings
PID-8153-SETTINGS v1
GlobalBaseSel defines the particular Global Base Values Group where the base quantities of the
function are set. In that Global Base Values Group:
IBase shall be entered as rated phase current of the protected object in primary amperes.
VBase shall be entered as rated phase-to-phase voltage of the protected object in primary kV.
The overcurrent step simply compares the magnitude of the measured current quantity with the set
pickup level. The overcurrent step picks up if the magnitude of the measured current quantity is higher
than the set level.
The overcurrent protection operation is made dependent of a measured voltage quantity. This means
that the pickup level of the overcurrent step is not constant but decreases with the decrease in
magnitude of the measured voltage quantity. This feature affects the pickup current value of both
definite time and inverse time IDMT overcurrent protection; in particular the overcurrent with IDMT curve
operates faster during low voltage conditions. Two different types of dependencies are available:
• Voltage restrained overcurrent (when setting parameter VDepMode = Slope); the pickup level of
the overcurrent stage changes according to the Figure 326. The voltage restrained characteristic
is defined by the two points: (0.25*VBase ; VDepFact *Pickup_Curr/100*IBase) and (VHighLimit/
100*VBase; Pickup_Curr/100*IBase). In the first point the factor 0.25 that multiply VBase cannot be
changed.
PickupCurr
VDepFact * PickupCurr
0,25 VHighLimit
VBase
ANSI10000123-2-en.vsd
ANSI10000123 V2 EN-US
Figure 326: Example for pickup level of the current variation as function of measured voltage magnitude in Slope mode of
operation
• Voltage controlled overcurrent (when setting parameter VDepMode = Step); the pickup level of the
overcurrent stage changes according to the Figure 327.
PickupCurr
VDepFact * PickupCurr
VHighLimit VBase
ANSI10000124-2-en.vsd
ANSI10000124 V2 EN-US
Figure 327: Example for pickup level of the current variation as function of measured voltage magnitude in Step mode of
operation
DEF time
selected 0-tDef_OC
0 TROC
OR
MaxPhCurr
a PU_OC
a>b
b
PickupCurr
X Inverse
Inverse
time
Voltage selected
control or
restraint
feature
MinPh-Ph Voltage
ANSI10000214-2-en.vsd
ANSI10000214 V2 EN-US
DEF time
selected 0-tDef_UV TRUV
0
MinPh-PhVoltage a
b>a
b PU_UV
AND
PickupVolt
Operation_UV=Disabled
BLKUV
ANSI10000213-2-en.vsd
ANSI10000213 V2 EN-US
The undervoltage step simply compares the magnitude of the measured voltage quantity with the set
pickup level. The undervoltage step picks up if the magnitude of the measured voltage quantity is lower
than the set level.
The pickup signal starts a definite time delay. If the value of the pickup signal is one for longer than the
set time delay, the undervoltage step sets its trip signal to one.
This undervoltage functionality together with additional ACT logic can be used to provide functionality for
overcurrent protection with undervoltage seal-in.
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Average Power Transient APPTEF Io > → TEF 67NT
Earth Fault Protection
High impedance grounded power systems are characterized by a relatively high impedance which is
connected between the power system neutral point and ground. The most extreme example is an
isolated power system where this impedance is practically infinite. However, it is important to understand
that the natural distributed capacitances between the individual phase conductors and ground are
always present in any power network irrespective of the neutral point grounding. These distributed
capacitances are important to understand the power system behavior, during an Earth Fault (EF) in a
high impedance grounded power system.
The APPTEF (Average Power Transient Earth Fault Protection) function is a transient measuring
directional earth-fault protection. Determination of the earth fault direction is based on the short-term
built-up transient at the beginning of the earth fault. This transient is to a large extent independent of the
neutral point treatment. This means that the function can be used without any modification in all types of
high-impedance grounded, resonant grounded or isolated power systems.
For a resonant grounded system, the correct directional measurement is ensured regardless of how
many Petersen coils are used throughout the interconnected power network. The function is not
sensitive to the actual compensation degree of the coils. It will operate equally well in an under- or
over-compensated system. Parallel neutral resistor to the Petersen coil are not needed to correctly
determine earth fault direction. However, these neutral resistors can still be used if already installed in
the network.
APPTEF (67NT)
I3P* TRIP
V3P* PUFW
BLOCK PUREV
BLKTR PUVN
RESET STIEF
WRNFW
ALMCC
ALMCIRI
IFUNDRE
IFUNDIM
IHARMIM
ANSI19000949-1-en.vsdx
GUID-41AA3224-974A-43B4-B2E5-F2C0FC582CCB V1 EN-US
10.16.5 Signals
GUID-1DF01EED-2316-4540-AD51-1F44BE750C81 v1
10.16.6 Settings
PID-8086-SETTINGS v1
The basic operating condition for the transient earth fault (EF) protection in a high impedance grounded
system is explained for a substation having a single incoming transformer which will be feeding a LV
side busbar having three outgoing feeders. The associated directional EF protection for every feeder are
also shown in Figure 331 as well as a grounding impedance connected to the transformer LV winding
star point.
HV Busbar
HV
CB
Power Δ
Transformer
Y Ground
Grounding
Impedance
Transformer
LV Bay
CB
Feeder 1 Feeder 2 Feeder 3
LV Busbar
VT
F1 F2 F3
CB CB CB
IEC19000933-1-en.vsdx
IEC19000933 V1 EN-US
Figure 332, displays a simplified equivalent circuit for the zero-sequence system during an earth-fault in
Feeder 1.
Transformer
Feeder 1 Bay Feeder 2 Feeder 3
LV Busbar
VT
Uo
F1 LV F2 F3
CB CB CB CB
Io_F1
Io_F2
Io_F3
Io_Tr
67NT‐F1 67NT‐F2 67NT‐F3
Faulty Feeder
HV Busbar
Transformer HV
Y Δ CB
Rf Grounding
Impedance
Ground
IEC19000934-1-en.vsdx
IEC19000934 V1 EN-US
Such an equivalent circuit can be used to facilitate the understanding of the basic physics-processes
which occurs when EF happens in a high-impedance grounded system.
1. The EF location is in Feeder 1. Consequently, its distributed capacitance is split into two parts, one
in-between the LV busbar and the fault point (that is C_F1’) and the second one behind the fault
point (that is C_F1”).
2. All feeders are just represented with a capacitance to ground. All series parameters of any
feeder are ignored because their impedance is much lower than this capacitive impedance and
consequently these series parameters can be ignored.
3. A resistance to ground (R_F3) is shown with dashed lines for Feeder 3, in practice these resistances
are extremely large and typically can be ignored. Consequently, these are not shown for other
feeders.
4. An inductance to ground ( L_F3) is also shown with dashed lines for Feeder 3, that in practice may
represent distributed coils along that feeder or remote coils located in the other substation at the end
of Feeder 3. In systems with multiple coils the above-mentioned resistance to ground (R_F3) may
also include the coil losses.
5. The grounding impedance at the transformer LV winding neutral point is represented as a parallel
connection of an inductor ( L) and a resistor ( R). This is the most practical representation because it
can then represent the most commonly used grounding principles (for isolated system L= R=∞).
6. The location of all CTs and VTs are also given because these are used to determine the
measurement points for Io and respectively Uo signals in each feeder.
7. Note that Io and Uo are correct values for this equivalent circuit. In a real installation the IED will
actually measure 3Io and 3Uo, but the difference between them is just a fixed factor of 3. In further
writing only Io and Uo notation will be used, but whatever is written is applicable to 3Io and 3Uo as
well.
8. The reference direction for current measurement (towards the protected feeder) is also given with
associated directional EF protection ( 67NT-F1 for Feeder 1) in each outgoing feeder bay.
9. As per the superposition theorem, a single source in the zero-sequence system is located at the
fault point. Its magnitude is equal to the phase-to-ground voltage in the faulty phase just before
the fault, but its phase angle shall be turned-around for 180 degrees. If it is assumed that the fault
resistance (that is Rf) has approximately a value of zero ( a bolted fault), then the Uo voltage will be
equal to this source voltage. The Uo voltage will be approximately the same for all IEDs throughout
the system. That means that the differences in the measured Io currents in the individual feeders are
important to determine the faulty versus the healthy feeder.
When EF happens (that is when the switch at the fault point closes in Figure 332) the source located at
the fault point energizes all the distributed capacitances of all the feeders connected to the LV busbar.
Note that these capacitors are not energized (that is the capacitors are empty or without any stored
energy) just before the earth fault.
Consequently, these are first charged to an energy level corresponding to the Uo voltage level (using
the formula 0.5*Uo2*C) before starting to exchange reactive power with either the source located at the
fault point or with the coil(s) which are possibly located at transformer neutral point(s). This active power
surge is quite short, but if it can be measured or detected by the IED, then it can be used to detect
the faulty feeder. Figure 333 displays the path for this active but transient power from the source to the
distributed capacitors.
Transformer
Feeder 1 Bay Feeder 2 Feeder 3
LV Busbar
VT
Uo
F1 LV F2 F3
CB CB CB CB
Io_F1
Io_F2
Io_F3
Io_Tr
Transformer HV
Y Δ CB
Rf Grounding
Impedance
Ground
IEC19000935-1-en.vsdx
IEC19000935 V1 EN-US
Figure 333: Flow of active power in the zero-sequence system at the moment when EF happens
Note that the existence of any shunt resistance in the system (R or R_F3 in Figure 333) will increase the
active transient power flow and consequently make it easier for the active power measurement principle
to determine the EF position. The same is true if the fault resistance Rf is present in the circuit. At the
same time, the existence of any inductor in the circuit (L or L_F3) will not influence the active power flow
in any way.
The EF position can be determined because the flow of the active transient power will be in the opposite
direction through the CTs in the faulty feeder and the healthy feeders. In simple words this active
power will be negative in the faulty feeder and positive in a healthy feeder. Note that the transient
EF IED installed in a healthy feeder will measure the transient charging power of the own distributed
capacitance, while the IED installed in the faulty feeder will measure the active transient charging power
of all healthy feeders lumped together. Consequently, this transient charging power signal magnitude will
be the largest for the faulty feeder and the smallest for the shortest healthy feeder.
It is quite a common protection practice to use -Uo voltage (that is Uo voltage phasor which is
turned around/rotated for 180 degrees) for all EF protection functions. This will only invert all power
directions previously explained. For example, in an actual IED implementation the measured power
will be essentially positive in the faulty feeder and negative in a healthy feeder. This can be simply
understood as a sign convention which is commonly used in protective relaying practice.
In a power system the active power can be only supplied by the fundamental frequency signals, which
means that this active power must be generated by one or more generation plant connected to the
networks. Consequently, only the fundamental frequency content of the Io and Uo signals shall be used
to measure this active transient power in every bay. To calculate active power based on fundamental
frequency phasors the formula given below is used. Note that Uo is taken with the minus sign as
explained previously.
P U 01 * I 01 *cos( 1)
The index one in this equation indicates that only the fundamental frequency component signals are
used for the active power calculation. As mentioned previously -Uo is a constant for all EF IEDs in
the galvanically interconnected system, and consequently only the active fundamental frequency current
component Io*cos(ɸ) can be used to determine the direction of the EF.
Figure 334 displays the method to derive the Io*cos(ɸ) component. Practically it is a part of Io phasors
which is in phase with -Uo phasor. This calculation is done at every execution of the algorithm.
For fundamental frequency current phasor, only the Io*cos(ɸ) component has a useful physical meaning.
The Io*sin(ɸ) component is just a disturbing part of the input signal which can only cause confusion
and possible wrong operation of the transient EF IED if it is used. This is because when multiple
compensation coils are installed in the network, the flow of the reactive power in the zero-sequence
system is quite unpredictable.
‐Uo
Io
IEC19000936-1-en.vsdx
IEC19000936 V1 EN-US
Figure 334: Deriving Io*cos(ɸ) and Io*sin(ɸ) quantities from -Uo and Io phasors
Because the instantaneous Io*cos(ɸ) values will vary quite a lot during the transient an averaged (that
is integrated) value is used. This averaged power value will correspond to the actual energy stored
in the distributed capacitances. In the feeder where EF is located this averaged value will be always
positive, while in all healthy feeders this averaged value will be always negative. Thus, by setting two
simple current threshold levels (one positive and the second one negative) the direction of the EF can
be determined. The averaged Io*cos(ɸ) value is also given as a service value from the APPTEF function
in order to make easier testing and understanding of the function operation principles (that is see signal
IFUNDRE in Figure 339). This value can be recorded by the built in DR and even be used to fine-tune
the settings for the respective pickup levels.
An example how these signals may look like for an EF on a faulty feeder and on a healthy feeder are
given in Figure 335 and Figure 336 respectively.
IEC19000937 V1 EN-US
Figure 335: Example how waveforms and the active power signals may look like for a faulty feeder
IEC19000938=IEC19000938=1=en-us=Original.vsdx
IEC19000938=IEC19000938=1=en-us=Original.vsdx
IEC19000938-1-en.vsdx
IEC19000938 V1 EN-US
Figure 336: Example how waveforms and the active power signals may look like for a healthy feeder
Note that the presence of a grounding resistor is clearly visible in Figure 335b because the averaged
value of the Io*cos(ɸ) component do not drop to zero after the transient for a faulty feeder, but it drops to
zero for a healthy feeder as shown in Figure 336b.
The advantages of the averaged Io*cos(ɸ) method to detect the EF direction in high-impedance
grounded system are:
1. Simplicity, because only the active part of the fundamental frequency component of the Io current
phasor is used.
2. Use of the widely recognized protection principle Io*cos(ɸ).
3. Independence from the compensation degree, number of coils used and their physical location in
the protected network (Petersen coils do not consume active power).
4. Averaging (numerical integration) is performed continuously. No need to start/stop this calculation
process.
5. The Io*cos(ɸ) quantity will be approximately equal to zero during all operating conditions of the
protected network except during the transient charging process of the capacitors. Consequently, it is
relatively simple to determine when this quantity appears. As additional security measure it can also
be verified that this coincides with the jump of Uo voltage magnitude.
6. A low sampling rate is sufficient because only the fundamental frequency phasors of Uo and Io are
calculated from the input signal. A sampling rate of 20 samples per fundamental power system cycle
is enough for proper operation of the transient EF IED.
7. Raw samples of residual voltage and current are not at all directly used in the algorithm which
simplifies the overall design.
8. There are no angular accuracy issues because no angle-based criterion is used.
9. Separate operate levels for forward and reverse directions can be used.
The energizing of a shunt capacitor in a power system is typically followed by relatively large current and
voltage transients which contains a lot of harmonics. When an EF happens the same holds true for the
zero-sequence circuit.
As shown in Figure 335, some damped oscillation is clearly visible in the Io signal at the beginning of
this EF. The frequency of that oscillation is determined by network parameters (that is L, R and C) and
is almost never an exact multiple of the fundamental frequency signal. The frequency of the oscillating
signal may vary from 100Hz up to theoretically 5kHz. In modern numerical IEDs typically full-cycle filters
(that is 20ms long filtering window in 50Hz power system) will be used to extract the fundamental
frequency phasors but, also higher harmonic phasors. The filtering time is quite short and the oscillation
signal during an EF will pass through this filter making it visible in some of the Io current harmonic
phasors.
For resonant grounded systems the total inductance of all coils is tuned to the distributed capacitance
of the overall power system only at the fundamental (rated) frequency. For all higher harmonic signals
the coils have a h2 times higher impedance than the corresponding capacitive reactance, where h is
the harmonic number. Already for the second harmonic component (h=2) the compensation coils will
have a 4 times higher impedance than distributed capacitances. Therefore all coils can be omitted from
the zero-sequence equivalent circuit shown in Figure 332 for all harmonic components. A simplification
is that all harmonic components in any high-impedance grounded systems behave as the fundamental
frequency component in an isolated power system. Subsequently the Io*sin(ɸ) principle which is typically
used in an isolated power system can be now applied to all the higher order harmonic components
irrespective of the actual type of the grounding used in the protected network.
Since the higher harmonics will primarily be present during the transient part of the EF, these harmonic
components will behave in a similar transient way as previously explained for the fundamental frequency
Io*cos(ɸ) component. Consequently, the same integration principle can be used to measure this
transient harmonic reactive power exchange between the capacitors and the harmonic source located at
the fault point.
To simplify the IED calculations, the following sum is formed first, where all reactive power components
from all current harmonics are lumped together:
K
IOh *sin( h )
h2
where K is the maximum harmonic component which can be measured by the relay. This summed value
is proportional to the total harmonic reactive power seen by the IED during an EF.
Since the summed instantaneous Io*sin(ɸ) harmonic values will vary quite a lot during a transient period
of the EF, the averaged (integrated) value is used. In the feeder where the EF is located this averaged
value will be positive, while in all feeders which see the EF in reverse, this averaged value will be
negative. By settings, two current threshold levels (one positive and the second negative), the direction
of the EF can be determined. Since everything is scaled back to current, even the same pickup levels as
for the active transient power part can be used.
The summed averaged Io*sin(ɸ) harmonic value is also given as a service value from the function (see
signal IHARMIM in Figure 339) to make testing and understanding of the function operation principles
easier. This value can be recorded by the built in disturbance recorder and even be used to fine-tune the
settings for the respective pickup levels.
Examples how these signals may look like for an EF on a faulty feeder and on a healthy feeder are given
in Figure 337 and Figure 338 respectively. Note that this is the same EF and feeders as shown in Figure
335 and Figure 336.
IEC19000939=IEC19000939=1=en-us=Original.vsdx
IEC19000939-1-en.vsdx
IEC19000939-1-en.vsdx
IEC19000939 V1 EN-US
Figure 337: Example how waveforms and the summed harmonic reactive power signals may look like for a faulty feeder
IEC19000940=IEC19000940=1=en-us=Original.vsdx
IEC19000939-1-en.vsdx
IEC19000940=IEC19000940=1=en-us=Original.vsdx
IEC19000940=IEC19000940=1=en-us=Original.vsdx
IEC19000940 V1 EN-US
Figure 338: Example how waveforms and the summed harmonic reactive power signals may look like for a healthy feeder
Advantages of this harmonic based transient reactive power method to detect the EF direction in
high-impedance grounded system are:
1. Simplicity, because only the reactive part of the higher harmonic phasors of Io current is used.
2. Use of the widely recognized protection principle Io*sin(ɸ).
3. Independence from the compensation degree, number of coils used and their physical location in
the protected network (all coils are disregarded for harmonic calculations).
4. Averaging (that is numerical integration) is performed continuously. There is no need to start/stop
this calculation process.
5. The Ʃ(Ioh*sin(ɸh)) quantity will be approximately equal to zero during all operating conditions of
the protected network except during the transient period of the EF. Consequently, it is simple to
determine when this quantity appears. As an additional security measure, it can be verified that this
coincides with the jump of the fundamental frequency Uo voltage magnitude.
6. A low sampling rate is sufficient, because typically only up to and including the 5th harmonic is
required to be taken into calculation.
7. Raw samples of residual voltage and current are not at all directly used in the algorithm which
simplifies the overall design.
8. Separate operate levels for forward and reverse direction are possible.
As explained in the previous two sections this transient EF protection function is based on two principles:
1. Distribution of the active transient power at fundamental frequency, which is supplied from the fault
point to initially charge all distributed capacitances to ground in the zero-sequence system at the
moment of an EF inception in a high-impedance grounded network.
2. Distribution of the reactive transient power for higher harmonic components at the moment of an EF
inception in a high-impedance grounded network.
These two principles will hold true for any type of EF in a high-impedance grounded network, including
low-ohmic, high-ohmic, intermittent and restriking earth-faults. Consequently, this function is able to
operate for all of them.
Note that the neutral voltage Uo is common for all relays installed in the galvanically interconnected
system and typically the voltage measurement does not pose any problem for the IED operation.
It is not trivial to properly measure the residual current signal Io and extract the useful parts from it. Due
to this, use of complete current phasors for either fundamental frequency or higher harmonics can be a
problem and can lead to incorrect operation of the relays which are using complete current phasors for
measurement.
For fundamental frequency current phasor only the Io*cos(ɸ) component has useful physical meaning,
while the Io*sin(ɸ) component is just a disturbing part of the signal.
For all higher harmonic current phasors the situation is exactly the opposite. Io*sin(ɸ) is a useful
component with physical meaning, while the Io*cos(ɸ) component shall be avoided.
To achieve a stable and reliable signal, only the useful components of the current signal are integrated
in time. This makes these integral values proportional to the respective energy. However, these integral
values are scaled back to the measured current magnitude by using the moving average method. Only
the sign of this integral (positive or negative) during an EF is used in this design to determine the
direction of the earth fault. Some minimum (settable) magnitude level of the integrated signal shall be
exceeded for security reasons and to avoid any possible issues with IED hardware accuracy. Using two
independent measurement principles, the best practical results in respect to dependability and security
for the transient earth-fault protection will be ensured.
Figure 339 displays the overall simplified logic diagram for the APPTEF function.
a uormshigh
a>b
UN> b
UNMAG *)
ioangle
ANGDIF *)
uoangle -
uofundamp
iofundamp
Continuous
Extract -Uo1 IFUNDRE
Derive |Io1|*cos(ɸ1) Integration
Fundamental
current (Averaging)
Extract Io1 active and |Io1|*sin(ɸ1)
reactive part Continuous IFUNDIM
Fundamental
Integration
Invert (Averaging)
Uo
Extract -Uo2 a activepowerhigh
3Uo Derive |Io2|*cos(ɸ2) a>b
2nd Harmonic IMinForward b
VT input current
Extract Io2 active and |Io2|*sin(ɸ2)
reactive part a activepowerlow
2nd Harmonic a<b
IMinReverse
x b
-1
Extract -Uo3 Derive |Io3|*cos(ɸ3) 2% of IBase a activepoweralarm
3Io 3rd Harmonic a>b
current b
CT input active and |Io3|*sin(ɸ3)
Extract
3rd Harmonic
Io3 reactive part Ʃ Continuous
Integration a
a>b
reactivepowerhigh
(Averaging)
b
0.0 T IHARMIM
F INRMS *)
5 cycles
Io True RMS a iormshigh
t
Filter a>b
IN> b
*) shown only in PCM600 Monitoring Tool and LHMI
IEC19000941 V2 EN-US
Figure 339: Simplified logic for measurement part of the APPTEF function
If required, the harmonic part of the APPTEF function can be effectively disabled when the binary input
signal BLKHARM has a logical value one. That will effectively force the calculated value for IHARMIM
to zero. Therefore, the Transient EF function APPTEF will then work based only on the fundamental
frequency phasor measurements for 3Uo and 3Io quantities.
The harmonic part of the function is enabled by default (that is, BLKHARM=0).
Service values for 3Uo magnitude, 3Io magnitude and angle between them are only displayed in the
Monitoring Tool and LHMI, in order to facilitate function testing and commissioning.
The integrated value of the fundamental frequency Io*sin(ɸ) reactive part (IFUNDIM ) is not used in
the function but is provided as a service value. This enables the end user for easier understanding of
the flow of reactive power in the zero-sequence circuit during an EF in a complex sub-transmission
network configurations when several compensation coils are used which are geographically spread-out
throughout the system.
The output signals displayed in Figure 339 with small letters are only used in simplified logic
diagrams which are given below. These signals are not available outside of the function.
After performing the measurement of the two averaged power components, the following Boolean logics
are used to derive required binary outputs from the transient EF protection function.
Residual over-voltage start logic and function overall reset logic GUID-C68D706F-BABC-48E2-B5E0-98A26121C09C v1
The residual over-voltage start signal is internally used in the APPTEF function to arm the function to
operate in case of an EF.
Note that this voltage signal defines when the function resets internally as well.
BLOCK block
stunwindow
2.5 cycles AND
STUN
AND
tStart
stun
t tStartOn
tReset 20ms
uormshigh
t
AND
RESET 5ms
From LHMI reset
IEC61850 Command OR OR
almcc
IEC19000942-1-en.vsdx
IEC19000942 V1 EN-US
This logic will enable operation of the function in case of an intermittent EF when the residual over-
voltage start will not be able to do that due to short duration of STUN signal.
20ms
stfw Counter
AND Set CounterLimit
stun reset Reached STIEF
Reset block AND
UN>StartsNo CounterLimit
stief
IEC19000943-1-en.vsdx
IEC19000943 V1 EN-US
The following logic diagram shows how the binary signals WRNFW, STFW and TRIP are derived.
uofundamp = 600ms
High
iofundamp t
Impedance
activepoweralarm Fault 50ms
stun
almciri Logic
block WRNFW
AND
activepowerhigh
OR
reactivepowerhigh
stunwindow stfw
iormshigh AND
almcc S tPulseMin
AND
reset RS
R OR STFW
tTripInterm
t
AND
stief TRIP
OR tTrip OR
tStartOn
AND t
OR tPulseMin
OperationMode = Start and Trip
BLKTR AND
IEC19000944 V2 EN-US
The following logic diagram shows how the binary signal STRV is derived.
stunwindow
activepowerlow
reactivepowerlow OR
iormshigh AND
almcc
stfw
S
reset RS
R
stief
tStartOn OR AND STRV
OR
block tPulseMin
stun
IEC19000945-1-en.vsdx
IEC19000945 V1 EN-US
The following logic diagram shows the implementation of cross country fault logic.
tCC
OperationCC = On 200ms
t
iofundamp AND t ALMCC
a reset AND AND
a>b block
CrossCntry_IN> b
almcc
IEC19000946-1-en.vsdx
IEC19000946 V1 EN-US
Note that the operation of this logic unconditionally resets either the STFW or STRV signal.
The following logic diagram shows the implementation of circulating current logic.
tCircIN
iofundamp 500ms block
a t
a>b reset t ALMCIRI
Circulate_IN> b AND AND
200ms
activepowerhigh
t
activepowerlow OR AND OR
stun
almciri
IEC19000947-1-en.vsdx
IEC19000947 V1 EN-US
Circulating residual current may appear in a meshed high-impedance grounded network. It will be mostly
of a reactive nature. However, if the above logic operates due to the presence of some active current
component in the fundamental frequency circulating current, then the pickup for the integrated active
power component of the fundamental frequency residual current is altered. This is done to prevent
possible mal-operation of the function. If the ALMCIRI signal becomes active the end user shall try to
rectify this problem in the primary system as this may influence proper operation of the transient EF
protection. Especially, the operation of the APPTEF function for high ohmic EF will become much more
difficult.
GUID-BCCA5F2D-9FF7-4188-9B5D-DA05E8E80CC0 v2
11.1.1 Identification
M16876-1 v8
3U<
V2 EN-US
SYMBOL-R-2U-GREATER-THAN
Undervoltages can occur in the power system during faults or abnormal conditions. The two-step
undervoltage protection function (UV2PTUV, 27) can be used to open circuit breakers to prepare for
system restoration at power outages or as a long-time delayed back-up to the primary protection.
UV2PTUV (27) has two voltage steps, each with inverse or definite time delay.
It has a high reset ratio to allow settings close to the system service voltage.
UV2PTUV (27)
V3P* TRIP
BLOCK TRST1
BLKTR1 TRST1_A
BLK1 TRST1_B
BLKTR2 TRST1_C
BLK2 TRST2
TRST2_A
TRST2_B
TRST2_C
PICKUP
PU_ST1
PU_ST1_A
PU_ST1_B
PU_ST1_C
PU_ST2
PU_ST2_A
PU_ST2_B
PU_ST2_C
ANSI06000276-2-en.vsd
ANSI06000276 V2 EN-US
11.1.4 Signals
PID-3586-INPUTSIGNALS v7
11.1.5 Settings
PID-3586-SETTINGS v7
Two-step undervoltage protection (UV2PTUV ,27) is used to detect low power system voltage. If one,
two or three phase voltages decrease below the set value, a corresponding START signal is generated.
The parameters OpMode1 and OpMode2 influence the requirements to activate the PICKUP outputs: 1
out of 3, 2 out of 3, or 3 out of 3 measured voltages have to be lower than the corresponding set point to
issue the corresponding PICKUP signal.
UV2PTUV (27) has two voltage-measuring steps with separate time delays. If the voltage remains below
the set value for the chosen time delay, the corresponding trip signal is issued. To avoid an unwanted
trip due to the disconnection of the related high-voltage equipment, a voltage-controlled blocking of the
function is available: if the voltage is lower than the set blocking level, the function is blocked and no
PICKUP or TRIP signal is generated. The time delay characteristic is individually chosen for each step
and can be either definite time delay or inverse time delay.
To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
Depending on the set ConnType value, UV2PTUV (27) measures either phase-to-ground voltage or
phase-to-phase voltage and compares it against the set values, Pickup1 and Pickup2. The voltage-
related settings are made in percentage of the base voltage which is set in kV phase-to-phase voltage.
This means operation for phase-to-ground voltage under:
The time delay for the two steps can be either definite time delay (DT) or inverse time undervoltage
(TUV). For the inverse time delay three different modes are available:
• inverse curve A
• inverse curve B
• customer programmable inverse curve
TD
t=
Vpickup < -V
Vpickup <
ANSIEQUATION1431 V1 EN-US (Equation 150)
where:
Vpickup< Set value for step 1 and step 2
V Measured voltage
TD × 480
t= 2.0
+ 0.055
æ Vpickup < -V ö
ç 32 × - 0.5 ÷
è Vpickup < ø
EQUATION1608 V1 EN-US (Equation 151)
é ù
ê ú
TD × A
t=ê ú+D
ê æ Vpickup < -V ö ú
P
êç B × -C÷ ú
ëè Vpickup ø û
EQUATION1609 V1 EN-US (Equation 152)
When the denominator in the expression is equal to zero the time delay will be infinity. There will
be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate for this
phenomenon. In the voltage interval Vpickup< down to Vpickup< · (1.0 – CrvSatn/100) the used voltage
will be: Vpickup< · (1.0 – CrvSatn/100). If the programmable curve is used this parameter must be
calculated so that:
CrvSatn
B× -C > 0
100
EQUATION1435 V1 EN-US (Equation 153)
If the Programmable inverse curve is chosen for operation and Equation 153 does not satisfy
based on the set values, no TRIP signal is issued. However, START signal is set and
maintained as long as the measured quantity for operation is below the set start level of step.
The lowest voltage is always used for the inverse time delay integration. The details of the different
inverse time characteristics are shown in section "Inverse characteristics".
Voltage
VA
VB
VC
IDMT Voltage
Time
ANSI12000186-1-en.vsd
ANSI12000186 V2 EN-US
Figure 347: Voltage used for the inverse time characteristic integration
TRIP signal issuing requires that the undervoltage condition continues for at least the user set time
delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by some
special voltage level dependent time curves for the inverse time mode (TUV). If the pickup condition,
with respect to the measured voltage, ceases during the delay time, and is not fulfilled again within
a user-defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and tIReset2 pickup
for the inverse time) the corresponding pickup output is reset. After leaving the hysteresis area, the
pickup condition must be fulfilled again and it is not sufficient for the signal to only return back to the
hysteresis area. For the undervoltage function the TUV reset time is constant and does not depend on
the voltage fluctuations during the drop-off period. However, there are three ways to reset the timer: the
timer is reset instantaneously, the timer value is frozen during the reset time, or the timer value is linearly
decreased during the reset time. See figure 348 and figure 349.
tIReset1
Voltage Measured
PICKUP Voltage
HystAbs1
TRIP
PICKUP1
Time
PICKUP
TRIP
Time
Integrator Frozen Timer
Time
Linearly
Instantaneous
decreased
ANSI055000010‐4‐en.vsdx
ANSI05000010 V4 EN-US
Figure 348: Voltage profile not causing a reset of the pickup signal for step 1, and inverse time delay at different reset types
Voltage tIReset1
PICKUP
PICKUP
HystAbs1 Measured Voltage
TRIP
PICKUP 1
Time
PICKUP t
TRIP
Time
Integrator Frozen Timer
Time
Linearly
Instantaneous
decreased ANSI05000011-3-en.vsdx
ANSI05000011 V3 EN-US
Figure 349: Voltage profile causing a reset of the pickup signal for step 1, and inverse time delay at different reset types
When definite time delay is selected the function will trip as shown in figure 350. Detailed information
about individual stage reset/operation behavior is shown in figure 351 and figure 352 respectively. Note
that by setting tResetn = 0.0s, instantaneous reset of the definite time delayed stage is ensured.
PU_ST1
V
a
a<b 0 t1 TRST1
Pickup1
b R tReset1 0
AND
ANSI09000785-3-en.vsd
ANSI09000785 V3 EN-US
Pickup1
PU_ST1
TRST1
tReset1
t1
ANSI10000039-3-en.vsd
ANSI10000039 V3 EN-US
Pickup1
PU_ST1
TRST1
tReset1
t1
ANSI10000040-3-en.vsd
ANSI10000040 V3 EN-US
It is possible to block Two step undervoltage protection UV2PTUV (27) partially or completely, by binary
input signals or by parameter settings, where:
If the measured voltage level decreases below the setting of IntBlkStVal1, either the trip output of step
1, or both the trip and the PICKUP outputs of step 1, are blocked. The characteristic of the blocking is
set by the IntBlkSel1 parameter. This internal blocking can also be set to Disabled resulting in no voltage
based blocking. Corresponding settings and functionality are valid also for step 2.
In case of disconnection of the high voltage component the measured voltage will get very low. The
event will PICKUP both the under voltage function and the blocking function, as seen in figure 353. The
delay of the blocking function must be set less than the time delay of under voltage function.
V Disconnection
Normal voltage
Pickup1
Pickup2
tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2
Time
Block step 1
Block step 2
en05000466_ansi.vsd
ANSI05000466 V1 EN-US
The voltage measuring elements continuously measure the three phase-to-neutral voltages or the three
phase-to-phase voltages. Recursive fourier filters or true RMS filters of input voltage signals are used.
The voltages are individually compared to the set value, and the lowest voltage is used for the inverse
time characteristic integration. A special logic is included to achieve the 1 out of 3, 2 out of 3 and 3 out of
3 criteria to fulfill the PICKUP condition. The design of Two step undervoltage protection UV2PTUV (27)
is schematically shown in Figure 354.
VA Comparator PU_ST1_A
VA < V1< Voltage Phase Phase 1
Selector
PU_ST1_B
VB Comparator OpMode1 Phase 2
VB < V1< 1 out of 3
2 out of 3 Pickup PU_ST1_C
3 out of 3 Phase 3 t1
VC Comparator t1Reset
VC < V1< IntBlkStVal1 & PU_ST1
Trip OR
Output
PICKUP Logic TRST1_A
Step 1 TRST1_B
Time integrator
tIReset1 TRIP
MinVoltSelector
ResetTypeCrv1 TRST1_C
TRST1
OR
Comparator PU_ST2_A
VA < V2< Voltage Phase Phase 1
Selector
PU_ST2_B
Comparator OpMode2 Phase 2
VB < V2< 1 out of 3 Pickup
2 out of 3 t2 PU_ST2_C
3 out of 3 Phase 3 t2Reset
Comparator IntBlkStVal2 &
VC < V2< Trip PU_ST2
Output OR
Logic
PICKUP TRST2_A
Step 2
TRST2_B
Time integrator
tIReset2 TRIP
MinVoltSelector
ResetTypeCrv2 TRST2_C
TRST2
OR
PICKUP
OR
TRIP
OR
ANSI05000012-3-en.vsd
ANSI05000012 V3 EN-US
Figure 354: Schematic design of Two step undervoltage protection UV2PTUV (27)
M13290-1 v17
11.2.1 Identification
M17002-1 v8
3U>
SYMBOL-C-2U-SMALLER-THAN V2 EN-US
Overvoltages may occur in the power system during abnormal conditions such as sudden power loss,
tap changer regulating failures, and open line ends on long lines.
Two step overvoltage protection (OV2PTOV, 59) function can be used to detect open line ends, normally
then combined with a directional reactive over-power function to supervise the system voltage. When
triggered, the function will cause an alarm, switch in reactors, or switch out capacitor banks.
OV2PTOV (59) has two voltage steps, each of them with inverse or definite time delayed.
OV2PTOV (59) has a high reset ratio to allow settings close to system service voltage.
OV2PTOV (59)
V3P* TRIP
BLOCK TRST1
BLKTR1 TRST1_A
BLK1 TRST1_B
BLKTR2 TRST1_C
BLK2 TRST2
TRST2_A
TRST2_B
TRST2_C
PICKUP
PU_ST1
PU_ST1_A
PU_ST1_B
PU_ST1_C
PU_ST2
PU_ST2_A
PU_ST2_B
PU_ST2_C
ANSI06000277-2-en.vsd
ANSI06000277 V2 EN-US
11.2.4 Signals
PID-3535-INPUTSIGNALS v7
11.2.5 Settings
PID-3535-SETTINGS v7
Two step overvoltage protection OV2PTOV (59) is used to detect high power system voltage. OV2PTOV
(59) has two steps with separate time delays. If one-, two- or three-phase voltages increase above the
set value, a corresponding PICKUP signal is issued. OV2PTOV (59) can be set to PICKUP/TRIP, based
on 1 out of 3, 2 out of 3 or 3 out of 3 of the measured voltages, being above the set point. If the voltage
remains above the set value for a time period corresponding to the chosen time delay, the corresponding
trip signal is issued.
The time delay characteristic is individually chosen for the two steps, and can be either definite time or
inverse time delayed.
The voltage related settings are made in percent of the global set base voltage VBase, which is set in
kV, phase-to-phase.
The setting of the analog inputs are given as primary phase-to-ground or phase-to-phase voltage.
OV2PTOV (59) will trip if the voltage gets higher than the set percentage of the set base voltage VBase.
This means operation for phase-to-ground voltage over:
All the three voltages are measured continuously, and compared with the set values, Pickup1 for Step 1
and Pickup2 for Step 2. The parameters OpMode1 and OpMode2 influence the requirements to activate
the PICKUP outputs. Either 1 out of 3, 2 out of 3 or 3 out of 3 measured voltages have to be higher than
the corresponding set point to issue the corresponding PICKUP signal.
The time delay for the two steps can be either definite time delay (DT) or inverse time delay (TOV). For
the inverse time delay four different modes are available:
• inverse curve A
• inverse curve B
• inverse curve C
• customer programmable inverse curve
TD
t=
V − Vpickup >
Vpickup >
EQUATION1625 V2 EN-US (Equation 156)
where:
Vpickup> Set value for step 1 and step 2
V Measured voltage
TD ⋅ 480
t= + 0.035
V − Vpickup >
32 ⋅ − 0.5
Vpickup >
ANSIEQUATION2287 V3 EN-US (Equation 157)
TD ⋅ 480
t= + 0.035
V − Vpickup >
32 ⋅ − 0.5
Vpickup >
ANSIEQUATION2288 V2 EN-US (Equation 158)
The customer programmable curve is defined by the below equation, where A, B, C, D, k and p are
settings:
TD × A
t= P
+D
æ V - Vpickup ö
çB× -C÷
è Vpickup ø
EQUATION1616 V1 EN-US (Equation 159)
When the denominator in the expression is equal to zero the time delay will be infinity. There will
be an undesired discontinuity. Therefore, a tuning parameter CrvSatn is set to compensate for this
phenomenon. In the voltage interval Vpickup up to Vpickup · (1.0 + CrvSatn/100) the used voltage will
be: Vpickup · (1.0 + CrvSatn/100). If the programmable curve is used this parameter must be calculated
so that:
CrvSatn
B× -C > 0
100
EQUATION1435 V1 EN-US (Equation 160)
If the Programmable inverse curve is chosen for operation and Equation 160 does not satisfy
based on the set values, no TRIP signal is issued. However, START signal is set and
maintained as long as the measured quantity for operation is above the set start level of step.
The highest phase (or phase-to-phase) voltage is always used for the inverse time delay integration,
see figure 356. The details of the different inverse time characteristics are shown in section "Inverse
characteristics".
Voltage
IDMT Voltage
VA
VB
VC
Time
ANSI05000016-2-en.vsd
ANSI05000016 V2 EN-US
Figure 356: Voltage used for the inverse time characteristic integration
Operation of the trip signal requires that the overvoltage condition continues for at least the user set time
delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by selected
voltage level dependent time curves for the inverse time mode (TOV). If the PICKUP condition, with
respect to the measured voltage ceases during the delay time, and is not fulfilled again within a user
defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and tIReset2 for the inverse
time) the corresponding PICKUP output is reset, after that the defined reset time has elapsed. Here it
should be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled again and
it is not sufficient for the signal to only return back to the hysteresis area. The hysteresis value for each
step is settable HystAbsn (where n means either 1 or 2 respectively) to allow a high and accurate reset
of the function. For OV2PTOV (59) the TOV reset time is constant and does not depend on the voltage
fluctuations during the drop-off period. However, there are three ways to reset the timer: either the timer
is reset instantaneously, or the timer value is frozen during the reset time, or the timer value is linearly
decreased during the reset time.
tIReset1
tIReset1
Voltage
PICKUP
TRIP
PU_Overvolt1
HystAbs1
Measured
Voltage
Time
PICKUP t
TRIP
Time Linearly
Integrator
decreased
Frozen Timer
t
Time
Instantaneous
ANSI05000019-3-en.vsd
ANSI05000019 V3 EN-US
Figure 357: Voltage profile not causing a reset of the PICKUP signal for step 1, and inverse time delay at different reset types
tIReset1
Voltage
PICKUP TRIP
PICKUP
HystAbs1
Pickup1
Measured
Voltage
Time
PICKUP t
TRIP
Time
Integrator Frozen Timer
Time
ANSI05000020 V3 EN-US
Figure 358: Voltage profile causing a reset of the PICKUP signal for step 1, and inverse time delay at different reset types
When definite time delay is selected, the function will trip as shown in figure 359. Detailed information
about individual stage reset/operation behavior is shown in figure 360 and figure 361 respectively. Note
that by setting tResetn = 0.0s (where n means either 1 or 2 respectively), instantaneous reset of the
definite time delayed stage is ensured.
PU_ST1
V tReset1 t1
a
a>b t t
TRST1
Vpickup>
b AND
OFF ON
Delay Delay
ANSI10000100-2-en.vsd
ANSI10000100 V2 EN-US
Figure 359: Logic diagram for step 1, definite time delay, DT operation
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000037-2-en.vsd
ANSI10000037 V2 EN-US
Figure 360: Example for step 1, Definite Time Delay stage 1 reset
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000038-2-en.vsd
ANSI10000038 V2 EN-US
It is possible to block Two step overvoltage protection OV2PTOV, (59) partially or completely, by binary
input signals where:
The voltage measuring elements continuously measure the three phase-to-ground voltages or the three
phase-to-phase voltages. Recursive Fourier filters or true RMS filters of input voltage signals are used.
The phase voltages are individually compared to the set value, and the highest voltage is used for the
inverse time characteristic integration. A special logic is included to achieve the 1 out of 3, 2 out of
3 or 3 out of 3 criteria to fulfill the PICKUP condition. The design of Two step overvoltage protection
(OV2PTOV, 59) is schematically described in figure 362.
VA Comparator PU_ST1_A
VA > Phase A
Pickup 1 Voltage Phase
Selector PU_ST1_B
VB Comparator
OpMode1 Phase B
VB >
Pickup 1 1 out of 3 Pickup
2 out of 3 t1 PU_ ST1_C
3 out of 3 Phase C
VC Comparator t1Reset
VC > &
Pickup 1 Phase C Trip PU_ST1
OR
Output
Logic
PICKUP TRST1-A
Step1
TRST1_B
Time integrator TRIP
MaxVoltSelect
tIReset1
ResetTypeCrv1 TRST1_C
TRST1
OR
Comparator
VA > PU_ST2_A
Pickup 2 Voltage Phase Phase A
Selector
PU_ST2_B
Comparator OpMode2 Phase B
VB >
Pickup 2 1 out of 3
2 out of 3 PU_ST2_C
3 out of 3 Pickup
Phase C
Comparator t2
VC > t2Reset
Pickup 2 & PU_ST2
OR
Trip
Output
PICKUP Logic TRST2-A
Step 2 TRST2-B
Time integrator TRIP
MaxVoltSelect tIReset2
ResetTypeCrv2 TRST2-C
TRST2
OR
OR PICKUP
TRIP
OR
ANSI05000013-2-en.vsd
_ .
ANSI05000013 V2 EN-US
Figure 362: Schematic design of Two step overvoltage protection OV2PTOV (59)
M13304-1 v16
11.3.2 Identification
SEMOD54295-2 v6
IEC15000108 V1 EN-US
Residual voltages may occur in the power system during ground faults.
Two step residual overvoltage protection (ROV2PTOV (59N)) function calculates the residual voltage
from the three-phase voltage input transformers or measures it from a single voltage input transformer
fed from a broken delta or neutral point voltage transformer.
ROV2PTOV (59N) has two voltage steps, each with inverse or definite time delay.
ROV2PTOV (59N)
V3P* TRIP
BLOCK TRST1
BLKTR1 TRST2
BLK1 PICKUP
BLKTR2 PU_ST1
BLK2 PU_ST2
ANSI06000278-2-en.vsd
ANSI06000278 V2 EN-US
11.3.5 Signals
PID-7438-INPUTSIGNALS v1
11.3.6 Settings
PID-7438-SETTINGS v1
Two step residual overvoltage protection ROV2PTOV (59N) is used to detect a high residual voltage.
The residual voltage can be measured directly from a voltage transformer in the neutral of a power
transformer or from a three-phase voltage transformer, where the secondary windings are connected in
an open delta. Another possibility is to measure the three phase-to-ground voltages, and calculate the
corresponding residual voltage internally in the IED. ROV2PTOV (59N) has two steps with separate time
delays. If the residual voltage remains above the set value for a time period corresponding to the chosen
time delay, the corresponding TRIP signal is issued.
The time delay characteristic is individually chosen for the two steps and can be either definite time
delay or inverse time delay.
The voltage-related settings are made in percent of the base voltage, which is set in kV, phase-phase.
The set UBase value is divided by sqrt(3) before the set value is calculated.
The residual voltage is measured continuously, and compared with the set values, Pickup1 and Pickup2.
To avoid oscillations of the output PICKUP signal, a settable hysteresis has been included.
The time delay for the two steps can be either definite time delay (DT) or inverse time delay (TOV). For
the inverse time delay four different modes are available:
• inverse curve A
• inverse curve B
• inverse curve C
• customer programmable inverse curve
TD
t=
æ V - Vpickup > ö
ç ÷
è Vpickup > ø
ANSIEQUATION2422 V1 EN-US (Equation 161)
where:
Vn> Set value for step 1 and step 2
V Measured voltage
TD × 480
t= 2.0
- 0.035
æ V - Vpickup > ö
ç 32 × - 0.5 ÷
è Vpickup > ø
ANSIEQUATION2423 V1 EN-US (Equation 162)
TD × 480
t= 3.0
+ 0.035
æ V - Vpickup > ö
ç 32 × - 0.5 ÷
è Vpickup > ø
ANSIEQUATION2421 V1 EN-US (Equation 163)
TD × A
t= P
+D
æ V - Vpickup ö
çB× -C÷
è Vpickup ø
EQUATION1616 V1 EN-US (Equation 164)
When the denominator in the expression is equal to zero, the time delay will be infinite. There will
be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate for this
phenomenon. In the voltage interval Vpickup up to Vpickup · (1.0 + CrvSatn/100) the used voltage will
be: Vpickup · (1.0 + CrvSatn/100). If the programmable curve is used this parameter must be calculated
so that:
CrvSatn
B× -C > 0
100
EQUATION1440 V1 EN-US (Equation 165)
If the Programmable inverse curve is chosen for operation and Equation 165 does not satisfy
based on the set values, no TRIP signal is issued. However, START signal is set and
maintained as long as the measured quantity for operation is above the set start level of step.
The details of the different inverse time characteristics are shown in section "Inverse characteristics".
TRIP signal issuing requires that the residual overvoltage condition continues for at least the user set
time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by some
special voltage level dependent time curves for the inverse time mode (TOV).
If the PICKUP condition, with respect to the measured voltage ceases during the delay time, and is not
fulfilled again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1
and tIReset2 for the inverse time) the corresponding PICKUP output is reset, after the defined reset time
has elapsed.
Here it should be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled
again and it is not sufficient for the signal to only return back to the hysteresis area. Also, notice that for
the overvoltage function, TOV reset time is constant and does not depend on the voltage fluctuations
during the drop-off period.
There are three ways to reset the timer: the timer is reset instantaneously, the timer value is frozen
during the reset time, or the timer value is linearly decreased during the reset time. See figure 364 and
figure 365.
tIReset1
tIReset1
Voltage
PICKUP
TRIP
PU_Overvolt1
HystAbs1
Measured
Voltage
Time
PICKUP t
TRIP
Time
Linearly
Integrator
decreased
Frozen Timer
t
Time
Instantaneous
ANSI05000019-3-en.vsd
ANSI05000019 V3 EN-US
Figure 364: Voltage profile not causing a reset of the PICKUP signal for step 1, and inverse time delay
tIReset1
Voltage
PICKUP TRIP
PICKUP
HystAbs1
Pickup1
Measured
Voltage
Time
PICKUP t
TRIP
Time
Integrator Frozen Timer
Time
ANSI05000020 V3 EN-US
Figure 365: Voltage profile causing a reset of the PICKUP signal for step 1, and inverse time delay
When definite time delay is selected, the function will trip as shown in figure 366. Detailed information
about individual stage reset/operation behavior is shown in figure 367 and figure 368 respectively. Note
that by setting tResetn = 0.0s, instantaneous reset of the definite time delayed stage is ensured.
PU_ST1
V tReset1 t1
a
a>b t t
TRST1
Vpickup>
b AND
OFF ON
Delay Delay
ANSI10000100-2-en.vsd
ANSI10000100 V2 EN-US
Figure 366: Logic diagram for step 1, Definite time delay, DT operation
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000037-2-en.vsd
ANSI10000037 V2 EN-US
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000038-2-en.vsd
ANSI10000038 V2 EN-US
It is possible to block two step residual overvoltage protection ROV2PTOV (59N) partially or completely
by binary input signals where:
The voltage measuring elements continuously measure the residual voltage. Recursive Fourier filters
filter the input voltage signal for the rated frequency. The residual voltage is compared to the set
value, and is also used for the inverse time characteristic integration. The design of the function is
schematically described in figure 369.
Comparator Phase 1
VN PU_ ST1
VN >
Pickup 1
Pickup TRST1
PICKUP t1
tReset1
&
Trip
Time integrator Output
tIReset1 TRIP Logic
ResetTypeCrv1 Step 1
Comparator PU_ST2
Phase 1
VN >
TRST2
Pickup2 Pickup
t2
PICKUP tReset2
& PICKUP
Trip OR
Time integrator Output
tIReset2 TRIP Logic
ResetTypeCrv2 Step 2 TRIP
OR
ANSI05000748-2-en.vsd
ANSI05000748 V2 EN-US
Figure 369: Schematic design of Two step residual overvoltage protection ROV2PTOV (59N)
11.4.1 Identification
M14867-1 v3
U/f >
SYMBOL-Q V1 EN-US
When the laminated core of a power transformer or generator is subjected to a magnetic flux density
beyond its design limits, stray flux will flow into non-laminated components that are not designed to carry
flux. This will cause eddy currents to flow. These eddy currents can cause excessive heating and severe
damage to insulation and adjacent parts in a relatively short time. The function has settable inverse
operating curves and independent alarm stages.
OEXPVPH (24)
I3P* TRIP
V3P* PICKUP
BLOCK ALARM
RESET
ANSI05000329-2-en.vsd
ANSI05000329 V2 EN-US
11.4.4 Signals
PID-8005-INPUTSIGNALS v1
11.4.5 Settings
PID-8005-SETTINGS v1
Modern design transformers are more sensitive to overexcitation than earlier types. This is a result of
the more efficient designs and designs which rely on the improvement in the uniformity of the excitation
level of modern systems. If an emergency that causes overexcitation does occur, transformers may be
damaged unless corrective action is taken. Transformer manufacturers recommend an overexcitation
protection as a part of the transformer protection system.
Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such conditions may occur when a transformer unit is loaded, but are more likely to arise
when the transformer is unloaded, or when loss of load occurs. Transformers directly connected to
generators are in particular danger to experience an overexcitation conditions. It follows from the
fundamental transformer equation, see equation 166, that the peak flux density Bmax is directly
proportional to induced voltage E, and inversely proportional to frequency f and turns n.
E = 4.44 × f × n × Bmax× A
EQUATION898 V2 EN-US (Equation 166)
E f
M ( p.u.) =
( Vr ) ( fn )
ANSIEQUATION2296 V1 EN-US (Equation 167)
Disproportional variations in quantities E and f may give rise to core overfluxing. If the core flux density
Bmax increases to a point above saturation level (typically 1.9 Tesla), the flux will no longer be contained
within the core, but will extend into other (non-laminated) parts of the power transformer and give rise to
eddy current circulations.
Protection against overexcitation is based on calculation of the relative volt per hertz (V/Hz) ratio.
Protection initiates a reduction of excitation, and if this fails, or if this is not possible, the TRIP signal will
disconnect the transformer from the source after a delay ranging from seconds to minutes, typically 5-10
seconds.
Overexcitation protection may be of particular concern on directly connected generator unit Step-up
Transformer. Directly connected generator-transformers are subjected to a wide range of frequencies
during the acceleration and deceleration of the turbine. In such cases, OEXPVPH (24) may trip the field
breaker during a start-up of a machine, by means of the overexcitation ALARM signal. If this is not
possible, the power transformer can be disconnected from the source, after a delay, by the TRIP signal.
The IEC 60076 - 1 standard requires that transformers operate continuously at not more than 10%
above rated voltage at no load, and rated frequency. At no load, the ratio of the actual generator terminal
voltage to the actual frequency should not exceed 1.1 times the ratio of transformer rated voltage to the
rated frequency on a sustained basis, see equation 168.
E Vn
£ 1.1 ×
f fn
EQUATION1630 V1 EN-US (Equation 168)
E Pickup1
£
f fn
ANSIEQUATION2297 V2 EN-US (Equation 169)
where:
Pickup1 is the maximum continuously allowed voltage at no load, and rated frequency.
Pickup1 is a setting parameter. The setting range is 100% to 180%. If the user does not know exactly
what to set, then the default value for Pickup1 = 110 % given by the IEC 60076-1 standard shall be
used.
E f
M ( p.u.) =
Vn fn
ANSIEQUATION2299 V1 EN-US (Equation 170)
It is clear from the above formula that, for an unloaded power transformer, M = 1 for any E and f, where
the ratio E/f is equal to Vn/fn. A power transformer is not overexcited as long as the relative excitation is
M ≤ Pickup1, Pickup1 expressed in % of Vn/fn.
The overexcitation protection algorithm is fed with an input voltage V which is in general not the induced
voltage E from the fundamental transformer equation. For no load condition, these two voltages are the
same, but for a loaded power transformer the internally induced voltage E may be lower or higher than
the voltage V which is measured and fed to OEXPVPH (24), depending on the direction of the power
flow through the power transformer, the power transformer side where OEXPVPH (24) is applied, and
the power transformer leakage reactance of the winding. It is important to specify in the application
configuration on which side of the power transformer OEXPVPH (24) is placed.
As an example, at a transformer with a 15% short circuit impedance Xsc, the full load, 0.8 power factor,
105% voltage on the load side, the actual flux level in the transformer core, will not be significantly
different from that at the 110% voltage, no load, rated frequency, provided that the short circuit
impedance X can be equally divided between the primary and the secondary winding: XLeakage =
XLeakage1 = XLeakage2 = Xsc / 2 = 0.075 pu.
OEXPVPH (24) calculates the internal induced voltage E if XLeakage (meaning the leakage reactance
of the winding where OEXPVPH (24) is connected) is known to the user. The assumption taken for
two-winding power transformers that XLeakage = Xsc / 2 is unfortunately most often not true. For a
two-winding power transformer the leakage reactances of the two windings depend on how the windings
are located on the core with respect to each other. In the case of three-winding power transformers the
situation is still more complex. If a user has the knowledge on the leakage reactance, then it should
applied. If a user has no idea about it, XLeakage can be set to Xc/2. OEXPVPH (24) protection will then
take the given measured voltage V, as the induced voltage E.
If one phase-to-phase voltage is available from the side where overexcitation protection is applied,
then Overexcitation protection OEXPVPH (24) shall be set to measure this voltage, MeasuredV. The
particular voltage which is used determines the two currents that must be used. This must be chosen
with the setting MeasuredI.
It is extremely important that MeasuredV and MeasuredI are set to same value.
If, for example, voltage Vab is fed to OEXPVPH(24), then currents Ia, and Ib must be applied. From
these two input currents, current Iab = Ia - Ib is calculated internally by the OEXPVPH (24) algorithm.
The phase-to-phase magnitude and frequency of the voltage must be both higher than 20% of the
rated value, when any of the two quantities are below this threshold, otherwise the protection algorithm
exits without calculating the excitation. ERROR output is set to 1, and the displayed value of relative
excitation V/Hz shows 0.000.
If three phase-to-ground voltages are available from the side where overexcitation is connected, then
OEXPVPH (24) shall be set to measure positive sequence voltage and current. In this case the positive
sequence voltage and the positive sequence current are used by OEXPVPH (24). A check is made if the
positive sequence magnitude and frequency are higher than 20% of the rated phase-to-ground voltage
and rated frequency respectively, when any of the two quantities are below this threshold, OEXPVPH
(24) exits immediately, and no excitation is calculated. ERROR output is set to 1, and the displayed
value of relative excitation V/Hz shows 0.000.
• OEXPVPH (24) can be connected to any power transformer side, independent from the power flow.
• The side with a possible load tap changer must not be used.
Basically there are two different delay laws available to choose between:
The so called IEEE law approximates a square law and has been chosen based on analysis of the
various transformers’ overexcitation capability characteristics. They can match the transformer core
capability well.
0.18 × TD 0.18 × TD
top = 2
= 2
æ M ö overexcitation
ç PUV Hz - 1 ÷
è ø
ANSIEQUATION2298 V2 EN-US (Equation 171)
where:
M the relative excitation
Pickup1 is maximum continuously allowed voltage at no load, and rated frequency, in pu and
TD is time multiplier for inverse time functions, see figure 372.
Parameter TD (“time delay multiplier setting”) selects one delay curve from the family of curves.
æ Vmeasured ö
ç ÷ Vmeasured frated
M =
è fmeasured ø = ×
æ VBase ö VBase fmeasured
ç ÷
è frated ø
ANSIEQUATION2404 V1 EN-US (Equation 172)
An analog overexcitation relay would have to evaluate the following integral expression, which means to
look for the instant of time t = top according to equation 173.
top
ò ( M ( t ) - Pickup1)
2
dt ³ 0.18 × TD
0
A digital, numerical relay will instead look for the lowest j (that is, j = n) where it becomes true that:
å ( M( j) - PUV / Hz )
2
Dt × ³ 0.18 × TD
j=k
where:
Dt is the time interval between two successive executions of OEXPVPH (24) and
M(j) - Pickup1 is the relative excitation at (time j) in excess of the normal (rated) excitation which is given as Vn/fn.
As long as M > Pickup1 (that is, overexcitation condition), the above sum can only be larger with time,
and if the overexcitation persists, the protected transformer will be tripped at j = n.
Inverse delays as per figure 372, can be modified (limited) by two special definite delay settings, namely
t_MaxTripDelay and t_MinTripDelay, see figure 371.
delay in s
t_MaxTrip
Delay
overexcitation
t_MinTripDelay
ANSI99001067-2-
en.vsd
ANSI99001067 V2 EN-US
A definite maximum time, t_MaxTripDelay, can be used to limit the operate time at low degrees of
overexcitation. Inverse delays longer than t_MaxTripDelay will not be allowed. In case the inverse delay
is longer than t_MaxTripDelay, OEXPVPH (24) trips after t_MaxTripDelay seconds.
A definite minimum time, t_MinTripDelay, can be used to limit the operate time at high degrees of
overexcitation. In case the inverse delay is shorter than t_MinTripDelay, OEXPVPH (24) function trips
after t_MinTripDelay seconds. The inverse delay law is not valid for values exceeding Mmax. The delay
will be tMin, irrespective of the overexcitation level, when values exceed Mmax (that is, M>Pickup1).
1000
100
TD = 60
TD = 20
TD = 10
10 TD = 9
TD = 8
TD = 7
TD = 6
TD = 5
TD = 4
TD = 3
TD = 2
TD = 1
1
1 2 3 4 5 10 20 30 40
OVEREXCITATION IN % (M-Emaxcont)*100)
en01000373_ansi.vsd
ANSI01000373 V1 EN-US
The critical value of excitation M is determined indirectly via OEXPVPH (24) setting Pickup2. Pickup2
can be thought of as a no-load voltage at rated frequency, where the inverse law should be replaced
by a short definite delay, t_MinTripDelay. If, for example, Pickup2 = 140 %, then M is according to
equation 175.
( Pickup2 f )
M= = 1.40
Vn/fn
ANSIEQUATION2286 V1 EN-US (Equation 175)
The Tailor-Made law allows a user to design an arbitrary delay characteristic. In this case the interval
between M = Pickup1, and M = Mmax is automatically divided into five equal subintervals, with six
delays. (settings t1, t2, t3, t4, t5 and t6) as shown in figure 373. These times should be set so that t1 =>
t2 => t3 => t4 => t5 => t6.
The upper V/Hz limit for the Tailor-Made characteristic is always the greater value among the following
two values in %:
• 1.10 x Pickup1
• Pickup2
The reason is to prevent the loss of accuracy of the Tailor-Made characteristic when small set value for
Pickup2 is used.
delay in s
t_MaxTripDelay
under- t_MinTripDelay
excitation Overexcitation M-E maxcont
0 M max - E maxcont Excitation M
Emaxcont M max
99001068_ansi.vsd
ANSI99001068 V1 EN-US
Delays between two consecutive points, for example t3 and t4, are obtained by linear interpolation.
Should it happen that t_MaxTripDelay be lower than, for example, delays t1, and t2, the actual delay
would be t_MaxTripDelay. Above Mmax, the delay can only be t_MinTripDelay.
Overexcitation protection OEXPVPH (24) is basically a thermal protection; therefore a cooling process
has been introduced. Exponential cooling process is applied. Parameter Setting tool is an OEXPVPH
(24) setting, with a default time constant t_CoolingK of 20 minutes. This means that if the voltage
and frequency return to their previous normal values (no more overexcitation), the normal temperature
is assumed to be reached not before approximately 5 times t_CoolingK minutes. If an overexcitation
condition would return before that, the time to trip will be shorter than it would be otherwise.
A monitored data value, TMTOTRIP, is available on the local HMI and in PCM600. This value is an
estimation of the remaining time to trip (in seconds), if the overexcitation remained on the level it had
when the estimation was done. This information can be useful during small or moderate overexcitation
situations.
If the overexcitation is so low that the valid delay is t_MaxTripDelay, then the estimation of the remaining
time to trip is done against t_MaxTripDelay.
The relative excitation M, shown on the local HMI and in PCM600 has a monitored data value VPERHZ
and is calculated from the expression:
E f
M ( p.u.) =
Vn fn
ANSIEQUATION2299 V1 EN-US (Equation 176)
If VPERHZ value is less than setting Pickup1 (in %), the power transformer is underexcited. If VPERHZ
is equal to Pickup1 (in %), the excitation is exactly equal to the power transformer continuous capability.
If VPERHZ is higher than Pickup1, the protected power transformer is overexcited. For example, if
VPERHZ = 1.100, while Pickup1 = 110 %, then the power transformer is exactly on its maximum
continuous excitation limit.
The monitored data value THERMSTA shows the thermal status of the protected power transformer
iron core. THERMSTA gives the thermal status in % of the trip value which corresponds to 100%.
THERMSTA should reach 100% at the same time, as TMTOTRIP reaches 0 seconds. If the protected
power transformer is then for some reason not switched off, THERMSTA shall go over 100%.
If the delay as per IEEE law, or Tailor-made Law, is limited by t_MaxTripDelay, and/or t_MinTripDelay,
then the Thermal status will generally not reach 100% at the same time, when tTRIP reaches 0 seconds.
For example, if, at low degrees of overexcitation, the very long delay is limited by t_MaxTripDelay, then
the OEXPVPH (24) TRIP output signal will be set to 1 before the Thermal status reaches 100%.
A separate step, AlarmPickup, is provided for alarming purpose. It is normally set 2% lower than
(Pickup1) and has a definite time delay, tAlarm. This will give the operator an early warning.
BLOCK
AlarmPickup
ALARM
0-tMax
t>tAlarm &
0
tAlarm
M>Pickup1
TRIP
&
Pickup1
V3P
Calculation
of internal
Ei TD
M
M=
I3P
induced (Ei / f) M IEEE law &
voltage Ei (Vn / fn)
OR
0-tMax
M
0
Tailor-made law
t_MaxTripDelay
M>Pickup2
Xleakage 0-tMin
0 t>tMin
Pickup2 t_MinTripDelay
ANSI05000162-3-en.vsd
ANSI05000162 V3 EN-US
Figure 374: A simplified logic diagram of the Overexcitation protection OEXPVPH (24)
Simplification of the diagram is in the way the IEEE and Tailor-made delays are calculated. The cooling
process is not shown. It is not shown that voltage and frequency are separately checked against their
respective limit values.
(0.18 × TD)
IEEE : t =
( M - 1) 2
where M = (E/f)/(Vn/fn)
Minimum time delay for inverse (0.000–60.000) s ±1.0% or ±45 ms, whichever is greater
function
Maximum time delay for inverse (0.00–9000.00) s ±1.0% or ±45 ms, whichever is greater
function
Alarm time delay (0.00–9000.00) ±1.0% or ±45 ms, whichever is greater
The healthy condition close to the rated values (that is, V/Hz below the set pickup value)
must be applied first when the operate time of a function is tested. Otherwise, an additional
delay of up to 50 ms should be added to stated operate times.
11.5.2 Identification
SEMOD167723-2 v3
A voltage differential monitoring function is available. It compares the voltages from two three phase sets
of voltage transformers and has one sensitive alarm step and one trip step.
VDCPTDV (87V)
V3P1* TRIP
V3P2* PICKUP
BLOCK ALARM
V1LOW
V2LOW
VDIFF_A
VDIFF_B
VDIFF_C
ANSI06000528 V3 EN-US
11.5.5 Signals
PID-8244-INPUTSIGNALS v1
11.5.6 Settings
GUID-7C74203F-0C71-4177-AAE2-CB3210CB6B1C v1
The Voltage differential protection function VDCPTDV (87V) is based on comparison of the magnitudes
of the two voltages connected in each phase. Possible differences between the ratios of the two Voltage/
Capacitive voltage transformers can be compensated for with a ratio correction factors RF_X. The
voltage difference is evaluated and if it exceeds the alarm level VDAlarm or trip level VDTrip signals for
alarm (ALARM output) or trip (TRIP output) is given after definite time delay tAlarm respectively tTrip.
The two three phase voltage supplies are also supervised with undervoltage settings V1Low and V2Low.
The outputs for loss of voltage V1LOW resp V2LOW will be activated. The V1 voltage is supervised for
loss of individual phases whereas the V2 voltage is supervised for loss of all three phases.
Loss of all V1 or all V2 voltages will block the differential measurement. This blocking can be switched
off with setting BlkDiffAtULow = No.
VDCPTDV(87V) function can be blocked from an external condition with the binary BLOCK input. It can,
for example, be activated from Fuse failure supervision function FUFSPVC.
To allow easy commissioning the measured differential voltage is available as service value. This allows
simple setting of the ratio correction factor to achieve full balance in normal service.
VDTrip_A
AND
VDTrip_B O
AND 0 0-tTrip TRIP
R 0-tReset 0 AND
VDTrip_C
AND
AND PICKUP
VDAlarm_A
AND
VDAlarm_B O 0-tAlarm
AND ALARM
R 0 AND
VDAlarm_C
AND
V1Low_A
V1Low_C AND
OR
BlkDiffAtULow
V2Low_A
V2Low_C
BLOCK
en06000382_2_ansi.vsd
ANSI06000382 V3 EN-US
11.6.1 Identification
SEMOD171954-2 v2
Loss of voltage check (LOVPTUV (27)) is suitable for use in networks with an automatic system
restoration function. LOVPTUV (27) issues a three-pole trip command to the circuit breaker, if all three
phase voltages fall below the set value for a time longer than the set time and the circuit breaker
remains closed.
The operation of LOVPTUV (27) is supervised by the fuse failure supervision FUFSPVC.
LOVPTUV (27)
V3P* TRIP
BLOCK PICKUP
CBOPEN
VTSU
ANSI07000039-2-en.vsd
ANSI07000039 V2 EN-US
11.6.4 Signals
PID-3519-INPUTSIGNALS v6
11.6.5 Settings
PID-3519-SETTINGS v6
The operation of Loss of voltage check LOVPTUV (27) is based on line voltage measurement.
LOVPTUV (27) is provided with a logic, which automatically recognizes if the line was restored for
at least tRestore before starting the tTrip timer. All three phases are required to be low before the output
TRIP is activated. The PICKUP output signal indicates pickup.
Additionally, LOVPTUV (27) is automatically blocked if only one or two phase voltages have been
detected low for more than tBlock.
LOVPTUV (27) operates again only if the line has been restored to full voltage for at least tRestore.
Operation of the function is also inhibited by fuse failure and open circuit breaker information signals, by
their connection to dedicated inputs of the function block.
Due to undervoltage conditions being continuous the trip pulse is limited to a length set by setting tPulse.
The operation of LOVPTUV (27) is supervised by the fuse-failure function (BLKV input) and the
information about the open position (CBOPEN) of the associated circuit breaker.
The BLOCK input can be connected to a binary input of the IED in order to receive a block command
from external devices or can be software connected to other internal functions of the IED itself in order
to receive a block command from internal functions. LOVPTUV (27) is also blocked when the IED is in
TEST status and the function has been blocked from the HMI test menu. (Blocked=Yes).
TEST
TEST-ACTIVE
AND
Blocked = Yes
PICKUP
BLOCK OR
PU_V_B AND
only 1 or 2 phases are low for
Latched at least 10 s (not three)
PU_V_C Enable
AND
OR 0-tBlock
0
OR 0-tRestore
Set Enable
0 OR
ANSI07000089_2_en.vsd
ANSI07000089 V2 EN-US
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Radial feeder protection PAPGAPC U< 27
The radial feeder protection (PAPGAPC (27)) function is used to provide protection of radial feeders
having passive loads or weak end in-feed sources. It is possible to achieve fast tripping using
communication system with remote end or delayed tripping not requiring communication or upon
communication system failure. For fast tripping, scheme communication is required. Delayed tripping
does not require scheme communication.
The PAPGAPC (27) function performs phase selection using measured voltages. Each phase voltage is
compared to the opposite phase-phase voltage. A phase is deemed to have a fault if its phase voltage
drops below a settable percentage of the opposite phase-phase voltage. The phase - phase voltages
include memory. This memory function has a settable time constant.
The voltage-based phase selection is used for both fast and delayed tripping. To achieve fast tripping,
scheme communication is required. Delayed tripping does not require scheme communication. It is
possible to permit delayed tripping only upon failure of the communications channel by blocking the
delayed tripping logic with a communications channel healthy input signal.
On receipt of the communications signal, phase selective outputs for fast tripping are set based on the
phase(s) in which the phase selection function has operated.
For delayed tripping, single pole and three pole delays are separately and independently settable.
Furthermore, it is possible to enable or disable single pole and three pole delayed tripping. For single
phase faults, it is possible to include a residual current check in the tripping logic. Three pole tripping is
always selected for phase selection on more than one phase. Three pole tripping will also occur if the
residual current exceeds the set level during fuse failure for a time longer than the three pole trip delay
time.
PAPGAPC (27)
I3P* TRIP
V3P* TRINP_3P
BLOCK TR_A
BLKTR TR_B
BLKST TR_C
BLKDLFLT ARST
FUSEFAIL ARST3PH
COMOK ARST_A
CR ARST_B
52A ARST_C
POLEDISC
ANSI14000058-1-en.vsd
ANSI14000024 V1 EN-US
PID-4140-INPUTSIGNALS v9
PID-4140-SETTINGS v9
The faulted phase selection is based on voltage measurement. Each phase voltage magnitude (rms) is
compared with the quadrature phase – phase voltage, which is obtained by passing full wave rectified
signal through an exponential filter.
The filter updates the output if the output magnitude is lower than input voltage. However, when the input
voltage is lower than output magnitude, the output decreases with a settable time constant of Tau. The
desired filter response is depicted in Figure380.
en01000140.vsd
IEC14000006 V2 EN-US
Phase x is deemed to have faulted if the phase x voltage is lower than filtered quadrature phase – phase
voltage times VPhSel< set value. The phase selection for remaining phases can be performed in the
similar way. The logic diagram for faulted phase selection is shown in Figure 381.
Z-1
V3P* ABS
MAX
-t ×
EXP
×
Tau ÷
× a PHSx
a<b
3 ÷ × b
VPhSel <
ANSI14000007-1-en.vsd
ANSI14000007 V1 EN-US
PAPGAPC (27) detects the presence of residual current if the residual current exceeds the set Pickup_N
value and lasts for a period of 600 ms.
The output TRIN is high after a set time of tResCurr if the setting ResCurrOper is enabled.
I3P*
a STIN
a>b 0
b 600 ms
Pickup_N tResCurr
0 TRIN
ResCurrOper &
BLOCK
BLKTR &
ANSI14000008-1-en.vsd
ANSI14000008 V1 EN-US
Operation at the remote end of the line with passive loads or weak sources is obtained as follows. The
fault clearing at remote end is initiated by CR signal received from the other end of the feeder. Fast fault
clearing can be enabled by the FastOperation setting. The function is enabled for 650 ms upon receiving
the carrier signal from the other end. It generates the pickup signal PUx depending on the status of the
faulty phase(s). The presence of FUSEFAIL inhibits the operation of fault clearance on faulty phase(s)
and the corresponding logic diagram is depicted in Figure 383. The fast fault clearance operation is
blocked upon failure of the communication channel input COMOK.
650 ms
CR
&
FUSEFAIL
COMOK
& & PUA
FastOperation
PHSA
& PUB
PHSB
& PUC
PHSC
ANSI14000009-2-en.vsd
ANSI14000009 V2 EN-US
Delayed fault clearance does not require scheme communication. It is possible to permit delayed
tripping upon the failure of the communication channel input COMOK.
It is possible to select delayed single- and three pole tripping by choosing the appropriate
settings Del1PhOp and Del3PhOp. Furthermore, time delays for single- and three pole tripping can
independently be set by t1Ph and t3Ph.
For single phase faults, ResCurrCheck is included in the tripping logic. It is also possible to select either
single- or three pole tripping for single phase faults occurring in the system. Three pole tripping is always
selected for phase selection of more than one phase.
In case of a fuse failure condition, that is FUSEFAIL is high, single- and three pole tripping are inhibited,
however, three pole tripping occurs if the residual current exceeds the set level during fuse failure for a
time longer than the three pole trip delay time of t3Ph.
The inputs BLKDLFLT and COMOK inhibit the delayed operation for faulty phase(s).
Pickup signal PUx is enabled as soon as the fault is detected in any phase(s).
COMOK
&
FastOperation
BLKDLFLT &
FUSEFAIL
STIN
≥1 &
ResCurrCheck
Del1PhOp
t1Ph PUA
PHSA & &
0 ≥1
PUB
PHSB & t1Ph &
0 ≥1
PUC
PHSC & t1Ph &
0 ≥1
≥1 &
&
Del3PhOp
≥2 & ≥1 t3Ph
0
&
ANSI14000010-2-en.vsd
ANSI14000010 V2 EN-US
The pickup signals for each phase are generated from both the fast fault clearance and delayed fault
clearance. Upon receiving the pickup signal PUx in phase(s), the corresponding phase trip signal TRLx
is issued. A general trip signal, TRIP is also generated.
The single or three phase operation of autorecloser depends on the status of CBCLD and the existence
of pole discrepancy, indicated by the input POLEDISC. If conditions for reclosing are fulfilled, a pickup
signal ARSTLx is issued for the faulty phase(s).
A general pickup signal, ARST is also generated. If more than one phase seems to be detected faulty,
three phase autoreclosing signal ARST3PH is issued.
The binary input BLOCK can be used to block the function. The activation of the BLOCK input deactivates
all outputs.
Pickup output signals ARSTLx, ARST and ARST3PH are blocked by enabling BLKST input and the
activation of the BLKTR input deactivates all trip outputs.
PUA
TR_A
&
PUB
TR_B
&
PUC
TR_C
&
≥1 TRIP
&
BLOCK
BLKTR ≥1
BLKST ≥1
& ARST_A
&
& ARST_B
&
& ARST_C
&
POLEDISC
CBCLD &
0 ≥1
100 ms ≥1 ARST
&
≥1 ARST3PH
&
ANSI14000011-2-en.vsd
ANSI14000011 V2 EN-US
Figure 385: Simplified logic diagram for trip and autoreclose logic
12.1.1 Identification
M14865-1 v6
f<
SYMBOL-P V1 EN-US
Underfrequency protection (SAPTUF (81)) measures frequency with high accuracy, and is used for load
shedding systems, remedial action schemes, gas turbine startup and so on. Separate definite time
delays are provided for trip and restore.
The operation is based on positive sequence voltage measurement and requires two phase-phase or
three phase-neutral voltages to be connected. For information about how to connect analog inputs, refer
to Application manual /IED application /Analog inputs /Setting guidelines .
SAPTUF (81)
V3P* TRIP
BLOCK PICKUP
BLKTRIP RESTORE
BLKREST BLKDMAGN
FREQ
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12.1.4 Signals
PID-6752-INPUTSIGNALS v2
PID-6752-OUTPUTSIGNALS v2
12.1.5 Settings
PID-6752-SETTINGS v2
Underfrequency protection SAPTUF (81) is used to detect low power system frequency. SAPTUF (81)
can either have a definite time delay or a voltage magnitude dependent time delay. If the voltage
magnitude dependent time delay is applied, the time delay will be longer if the voltage is higher, and the
delay will be shorter if the voltage is lower. If the frequency remains below the set value for a time period
corresponding to the chosen time delay, the corresponding trip signal is issued. To avoid an unwanted
trip due to uncertain frequency measurement at low voltage magnitude, a voltage controlled blocking of
the function is available, that is, if the voltage is lower than the set blocking voltage IntBlockLevel, the
function is blocked and no PICKUP or TRIP signal is issued.
The fundamental frequency of the measured input voltage is measured continuously, and compared
with the set value, PUFrequency. The frequency function is dependent on the voltage magnitude. If
the voltage magnitude decreases below the setting IntBlockLevel, SAPTUF (81) gets blocked, and the
output BLKDMAGN is issued. All voltage settings are made in percent of the setting VBase, which
should be set as a phase-phase voltage in kV.
To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
The time delay for underfrequency protection SAPTUF (81) can be either a settable definite time delay
or a voltage magnitude dependent time delay, where the time delay depends on the voltage level; a high
voltage level gives a longer time delay and a low voltage level causes a short time delay. For the definite
time delay, the setting tDelay sets the time delay.
For the voltage dependent time delay the measured voltage level and the settings VNom, VMin,
Exponent, t_MaxTripDelay and t_MinTripDelay set the time delay according to Figure 387 and Equation
178. The setting TimerMode is used to decide what type of time delay to apply.
Trip signal issuing requires that the underfrequency condition continues for at least the user set time
delay tDelay. If the PICKUP condition, with respect to the measured frequency ceases during this user
set delay time, and is not fulfilled again within a user defined reset time, tReset, the PICKUP output
is reset, after that the defined reset time has elapsed. Here it should be noted that after leaving the
hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only
return back to the hysteresis area.
The total time delay consists of the set value for time delay plus the minimum operate time of
the start function (80-90 ms).
On the RESTORE output of SAPTUF (81) a 100ms pulse is issued, after a time delay corresponding to
the setting of tRestore, when the measured frequency returns to the level corresponding to the setting
RestoreFreq, after an issue of the TRIP output signal. If tRestore is se to 0.000 s the restore functionality
is disabled, and no output will be given.
Since the fundamental frequency in a power system is the same all over the system, except some
deviations during power oscillations, another criterion is needed to decide, where to take actions,
based on low frequency. In many applications the voltage level is very suitable, and in most cases
is load shedding preferable in areas with low voltage. Therefore, a voltage dependent time delay has
been introduced, to make sure that load shedding, or other actions, take place at the right location.
At constant voltage, V, the voltage dependent time delay is calculated according to Equation 178
undervoltage and overvoltage functions.
Exponent
é V - VMin ù
t=ê × ( t _ MaxTripDelay - t _ MinTripDelay ) + t _ MinTripDelay
ëVNom - VMin ûú
EQUATION1559 V1 EN-US (Equation 178)
where:
t is the voltage dependent time delay (at constant voltage),
V is the measured voltage
Exponent is a setting,
VMin, VNom are voltage settings corresponding to
t_MaxTripDelay, t_MinTripDelay are time settings.
VMin = 90%
= 100%
t_MaxTripD = 1.0 s
elay
t_MinTripD = 0.0 s
elay
Exponent = 0, 1, 2, 3, and 4
1
0
1
Exponenent
TimeDlyOperate [s]
2
3
0.5 4
0
90 95 100
V [% of VBase]
en05000075_ansi.vsd
ANSI05000075 V1 EN-US
Figure 387: Voltage dependent inverse time characteristics for underfrequency protection SAPTUF (81). The time delay to
trip is plotted as a function of the measured voltage, for the Exponent = 0, 1, 2, 3, 4 respectively.
It is possible to block underfrequency protection SAPTUF (81) partially or completely, by binary input
signals or by parameter settings, where:
If the measured voltage level decreases below the setting of IntBlockLevel, both the PICKUP and the
TRIP outputs are blocked.
The frequency measuring element continuously measures the frequency of the positive sequence
voltage and compares it to the setting PUFrequency. The frequency signal is filtered to avoid
transients due to switchings and faults. The time integrator can trip either due to a definite delay
time or to the special voltage dependent delay time. When the frequency has returned back to the
setting of RestoreFreq, the RESTORE output is issued after the time delay tRestore. The design of
underfrequency protection SAPTUF (81) is schematically described in figure 388.
BLKDMAGN
BLOCK
block PICKUP
OR
V < IntBlockLevel
Pickup
&
pickup Trip
Voltage
output
Definite timer
logic TRIP
or
Voltage based timer
Frequency
f < PUFrequency
tReset trip
tDelay
AND
BLKTRIP
ANSI16000041-1-en.vsdx
ANSI16000041 V1 EN-US
Exponent
é U - UMin ù
t=ê × ( tMax - tMin) + tMin
ëUNom - UMin úû
U = U measured
EQUATION1182 V2 EN-US
Note: The stated accuracy is valid for the voltage range 50 V – 250 V secondary.
Table Note:
1) The settings and test conditions are in accordance with IEC 60255-181 standard (section 6.2 – 6.7).
12.2.1 Identification
M14866-1 v4
f>
SYMBOL-O V1 EN-US
Overfrequency protection function (SAPTOF (81)) is applicable in all situations, where reliable detection
of high fundamental power system frequency is needed.
Overfrequency occurs because of sudden load drops or shunt faults in the power network. Close to the
generating plant, generator governor problems can also cause over frequency.
SAPTOF (81) measures frequency with high accuracy, and is used mainly for generation shedding and
remedial action schemes. It is also used as a frequency stage initiating load restoring. A definite time
delay is provided for trip.
The operation is based on positive sequence voltage measurement and requires two phase-phase or
three phase-neutral voltages to be connected. For information about how to connect analog inputs, refer
to Application manual /IED application /Analog inputs /Setting guidelines .
SAPTOF (81)
V3P* TRIP
BLOCK PICKUP
BLKTRIP BLKDMAGN
FREQ
ANSI06000280-2-en.vsd
ANSI06000280 V2 EN-US
12.2.4 Signals
PID-6751-INPUTSIGNALS v2
12.2.5 Settings
PID-6751-SETTINGS v2
Overfrequency protection SAPTOF (81) is used to detect high power system frequency. SAPTOF (81)
has a settable definite time delay. If the frequency remains above the set value for a time period
corresponding to the chosen time delay, the corresponding TRIP signal is issued. To avoid an unwanted
TRIP due to uncertain frequency measurement at low voltage magnitude, a voltage controlled blocking
of the function is available, that is, if the voltage is lower than the set blocking voltage IntBlockLevel, the
function is blocked and no PICKUP or TRIP signal is issued.
The fundamental frequency of the positive sequence voltage is measured continuously, and compared
with the set value, PUFrequency. Overfrequency protection SAPTOF (81) is dependent on the voltage
magnitude. If the voltage magnitude decreases below the setting IntBlockLevel, SAPTOF (81) is blocked
and the output BLKDMAGN is issued. All voltage settings are made in percent of the VBase, which
should be set as a phase-phase voltage in kV. To avoid oscillations of the output PICKUP signal, a
hysteresis has been included.
The time delay for Overfrequency protection SAPTOF (81) is a settable definite time delay, specified by
the setting tDelay.
TRIP signal issuing requires that the overfrequency condition continues for at least the user set time
delay, tDelay. If the PICKUP condition, with respect to the measured frequency ceases during this user
set delay time, and is not fulfilled again within a user defined reset time, tReset, the PICKUP output is
reset, after that the defined reset time has elapsed. It is to be noted that after leaving the hysteresis
area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only return
back to the hysteresis area.
The total time delay consists of the set value for time delay plus minimum trip time of the
pickup function (80 - 90 ms).
It is possible to block overfrequency protection SAPTOF (81) partially or completely, by binary input
signals or by parameter settings, where:
If the measured voltage level decreases below the setting of IntBlockLevel, both the PICKUP and the
TRIP outputs are blocked.
The frequency measuring element continuously measures the frequency of the positive sequence
voltage and compares it to the setting PUFrequency. The frequency signal is filtered to avoid transients
due to switchings and faults in the power system. The time integrator operates due to a definite delay
time. The design of overfrequency protection SAPTOF (81) is schematically described in figure 390.
BLKDMAGN
BLOCK
block PICKUP
OR
V < IntBlockLevel
Pickup
&
pickup Trip
Voltage
output
logic TRIP
Definite timer
Frequency
f > StartFrequency tReset
trip
tDelay
AND
BLKTRIP
ANSI16000042-1-en.vsdx
ANSI16000042 V1 EN-US
12.3.1 Identification
M14868-1 v4
df/dt >
<
SYMBOL-N V1 EN-US
The rate-of-change of frequency protection function (SAPFRC (81)) gives an early indication of a main
disturbance in the system. SAPFRC (81) measures frequency with high accuracy, and can be used
for generation shedding, load shedding and remedial action schemes. SAPFRC (81) can discriminate
between a positive or negative change of frequency. A definite time delay is provided for trip.
SAPFRC (81) is provided with an undervoltage blocking. The operation is based on positive sequence
voltage measurement and requires two phase-phase or three phase-neutral voltages to be connected.
For information about how to connect analog inputs, refer to Application manual/IED application/
Analog inputs/Setting guidelines .
SAPFRC (81)
V3P* TRIP
BLOCK PICKUP
BLKTRIP RESTORE
BLKREST BLKDMAGN
ANSI06000281-2-en.vsd
ANSI06000281 V2 EN-US
12.3.4 Signals
PID-6754-INPUTSIGNALS v2
PID-6754-OUTPUTSIGNALS v2
12.3.5 Settings
PID-6754-SETTINGS v2
Rate-of-change frequency protection SAPFRC (81) is used to detect fast power system frequency
changes at an early stage. SAPFRC (81) has a settable definite time delay. If the rate-of-change of
frequency remains below the set value, for negative rate-of-change, for a time period equal to the
chosen time delay, the TRIP signal is issued. If the rate-of-change of frequency remains above the set
value, for positive rate-of-change, for a time period equal to the chosen time delay, the TRIP signal is
issued. To avoid an unwanted trip due to uncertain frequency measurement at low voltage magnitude a
voltage controlled blocking of the function is available, that is, if the voltage is lower than the set blocking
voltage IntBlockLevel the function is blocked and no PICKUP or TRIP signal is issued. If the frequency
recovers, after a frequency decrease, a restore signal is issued.
The rate-of-change of the fundamental frequency of the selected voltage is measured continuously,
and compared with the set value, PUFreqGrad. Rate-of-change frequency protection SAPFRC (81)
is also dependent on the voltage magnitude. If the voltage magnitude decreases below the setting
IntBlockLevel , SAPFRC (81) is blocked, and the output BLKDMAGN is issued. The sign of the setting
PUFreqGrad, controls if SAPFRC (81) reacts on a positive or on a negative change in frequency. If
SAPFRC (81) is used for decreasing frequency that is, the setting PUFreqGrad has been given a
negative value, and a trip signal has been issued, then a 100 ms pulse is issued on the RESTORE
output, when the frequency recovers to a value higher than the setting RestoreFreq. A positive setting of
PUFreqGrad, sets SAPFRC (81) to PICKUP and TRIP for frequency increases.
To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
Rate-of-change frequency protection SAPFRC (81) has a settable definite time delay, tDelay.
Trip signal issuing requires that the rate-of-change of frequency condition continues for at least the user
set time delay, tDelay. If the PICKUP condition, with respect to the measured frequency ceases during
the delay time, and is not fulfilled again within a user defined reset time, tReset, the PICKUP output
is reset, after that the defined reset time has elapsed. Here it should be noted that after leaving the
hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only
return back into the hysteresis area.
The RESTORE output of SAPFRC (81) is set, after a time delay equal to the setting of tDelay, when
the measured frequency has returned to the level corresponding to RestoreFreq, after an issue of the
TRIP output signal. If tRestore is set to 0.000 s the restore functionality is disabled, and no output will be
given. The restore functionality is only active for lowering frequency conditions and the restore sequence
is disabled if a new negative frequency gradient is detected during the restore period, defined by the
settings RestoreFreq and tRestore.
Rate-of-change frequency protection (SAPFRC, 81) can be partially or totally blocked, by binary input
signals or by parameter settings, where:
If the measured voltage level decreases below the setting of IntBlockLevel, both the PICKUP and the
TRIP outputs are blocked.
Rate-of-change frequency protection (SAPFRC, 81) measuring element continuously measures the
frequency of the selected voltage and compares it to the setting PUFreqGrad. The frequency signal
is filtered to avoid transients due to power system switchings and faults. The time integrator operates
with a definite delay time. When the frequency has returned back to the setting of RestoreFreq, the
RESTORE output is issued after the time delay tRestore, if the TRIP signal has earlier been issued. The
sign of the setting PUFreqGrad is essential, and controls if the function is used for raising or lowering
frequency conditions. The design of SAPFRC (81) is schematically described in figure 392.
BLKDMAGN
BLOCK
block
OR
Voltage
V < IntBlockLevel
PICKUP
Pickup
Rate-of-change
&
of Frequency pickup
If Trip
[StartFreqGrad<0 output
AND logic
Definite timer
df/dt < StartFreqGrad] pickup
TRIP
OR
tReset
[StartFreqGrad>0
AND
tDealy
df/dt > StartFreqGrad]
Then
PICKUP trip
AND
BLKTRIP
RESTORE
Frequency restore
f > RestoreFreq
> tRestore
AND
BLKREST
ANSI16000040-1-en.vsdx
ANSI16000040 V1 EN-US
Q 2.2.6 -
R 2.2.6 Minimum value changed to 0.01 for k_OC1 and k_OC2 settings
13.1.2 Identification
M14886-2 v3
13.1.3 Functionality
M13083-11 v9
The General current and voltage protection (CVGAPC) can be utilized as a negative sequence current
protection detecting unsymmetrical conditions such as open phase or unsymmetrical faults.
CVGAPC can also be used to improve phase selection for high resistive ground faults, outside the
distance protection reach, for the transmission line. Three functions are used, which measures the
neutral current and each of the three phase voltages. This will give an independence from load currents
and this phase selection will be used in conjunction with the detection of the ground fault from the
directional ground fault protection function.
CVGAPC
I3P* TRIP
V3P* TROC1
BLOCK TROC2
BLKOC1 TRUC1
BLKOC1TR TRUC2
ENMLTOC1 TROV1
BLKOC2 TROV2
BLKOC2TR TRUV1
ENMLTOC2 TRUV2
BLKUC1 PICKUP
BLKUC1TR PU_OC1
BLKUC2 PU_OC2
BLKUC2TR PU_UC1
BLKOV1 PU_UC2
BLKOV1TR PU_OV1
BLKOV2 PU_OV2
BLKOV2TR PU_UV1
BLKUV1 PU_UV2
BLKUV1TR BLK2ND
BLKUV2 DIROC1
BLKUV2TR DIROC2
VDIRLOW
CURRENT
ICOSFI
VOLTAGE
VIANGLE
ANSI05000372-2-en.vsd
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13.1.5 Signals
PID-8152-INPUTSIGNALS v1
PID-8152-OUTPUTSIGNALS v1
13.1.6 Settings
PID-8152-SETTINGS v1
General current and voltage protection (CVGAPC) function is always connected to three-phase current
and three-phase voltage input in the configuration tool, but it will always measure only one current and
one voltage quantity selected by the end user in the setting tool.
The user can select a current input, by a setting parameter CurrentInput, to measure one of the current
quantities shown in table 428.
The user can select a voltage input, by a setting parameter VoltageInput, to measure one of the voltage
quantities shown in table 429:
Note that the voltage selection from table 429 is always applicable regardless the actual external VT
connections. The three-phase VT inputs can be connected to IED as either three phase-to-ground
voltages, VA, VB, and VC or three phase-to-phase voltages and VAB, VBC, and VCA. This information
about actual VT connection is entered as a setting parameter for the pre-processing block, which will
then be taken care automatically.
The user can select one of the current quantities shown in table 430 for built-in current restraint feature:
The parameter settings for the base quantities, which represent the base (100%) for pickup levels of all
measuring stages shall be entered as setting parameters for every CVGAPC function.
1. rated phase-to-earth current of the protected object in primary amperes, when the measured Current
Quantity is selected from 1 to 9, as shown in table "".
2. rated phase current of the protected object in primary amperes multiplied by √3 (1.732 x Iphase),
when the measured Current Quantity is selected from 10 to 15, as shown in table "".
1. rated phase-to-ground voltage of the protected object in primary kV, when the measured Voltage
Quantity is selected from 1 to 9, as shown in table "".
2. rated phase-to-phase voltage of the protected object in primary kV, when the measured Voltage
Quantity is selected from 10 to 15, as shown in table "".
Two overcurrent protection steps are available. They are absolutely identical and therefore only one will
be explained here.
Overcurrent step simply compares the magnitude of the measured current quantity (see table 428)
with the set pickup level. Non-directional overcurrent step will pickup if the magnitude of the measured
current quantity is bigger than this set level. However depending on other enabled built-in features this
overcurrent pickup might not cause the overcurrent step pickup signal. Pickup signal will only come if all
of the enabled built-in features in the overcurrent step are fulfilled at the same time.
The overcurrent protection step can be restrained by a second harmonic component in the measured
current quantity (see table 428). However it shall be noted that this feature is not applicable when one of
the following measured currents is selected:
This feature will prevent overcurrent step pickup if the second-to-first harmonic ratio in the measured
current exceeds the set level.
The overcurrent protection step operation can be made dependent on the relevant phase angle between
measured current phasor (see table 428) and measured voltage phasor (see table 429). In protection
terminology it means that the General currrent and voltage protection (CVGAPC) function can be made
directional by enabling this built-in feature. In that case overcurrent protection step will only trip if the
current flow is in accordance with the set direction (Forward, which means towards the protected object,
or Reverse, which means from the protected object). For this feature it is of the outmost importance
to understand that the measured voltage phasor (see table 429) and measured current phasor (see
table 428) will be used for directional decision. Therefore it is the sole responsibility of the end user to
select the appropriate current and voltage signals in order to get a proper directional decision. CVGAPC
function will NOT do this automatically. It will simply use the current and voltage phasors selected by the
end user to check for the directional criteria.
Table 431 gives an overview of the typical choices (but not the only possible ones) for these two
quantities from traditional directional relays.
Table 431: Typical current and voltage choices for directional feature
Unbalance current or voltage measurement shall not be used when the directional feature is enabled.
Two types of directional measurement principles are available, I & V and IcosPhi&V. The first principle,
referred to as "I & V" in the parameter setting tool, checks that:
• the magnitude of the measured current is bigger than the set pick-up level
• the phasor of the measured current is within the operating region (defined by the relay trip angle,
ROADir parameter setting; see figure 394).
V=-3V0
RCADir
Operate region
MTA line
ANSI05000252-2-en.vsd
IEC05000252-ANIS V2 EN-US
where:
RCADir is 75°
ROADir is 50°
The second principle, referred to as "IcosPhi&V" in the parameter setting tool, checks that:
• that the product I·cos(Φ) is bigger than the set pick-up level, where Φ is angle between the current
phasor and the mta line
• that the phasor of the measured current is within the operating region (defined by the I·cos(Φ) straight
line and the relay trip angle, ROADir parameter setting; see figure 394).
V=-3V0
Operate region
MTA line
IEC05000253-2-en.vsdx
ANSI05000253 V2 EN-US
where:
RCADir is 75°
ROADir is 50°
Note that it is possible to decide by a parameter setting how the directional feature shall behave when
the magnitude of the measured voltage phasor falls below the pre-set value. User can select one of the
following three options:
It shall also be noted that the memory duration is limited in the algorithm to 100 ms. After that time the
current direction will be locked to the one determined during memory time and it will re-set only if the
current fails below set pickup level or voltage goes above set voltage memory limit.
The overcurrent protection step operation can be made dependent of a measured voltage quantity
(see table 429). Practically then the pickup level of the overcurrent step is not constant but instead
decreases with the decrease in the magnitude of the measured voltage quantity. Two different types of
dependencies are available:
PickupCurr_OC1
VDepFact_OC1 * PickupCurr_OC1
VLowLimit_OC1 VHighLimit_OC1
Selected Voltage
Magnitude
en05000324_ansi.vsd
ANSI05000324 V1 EN-US
Figure 396: Example for OC1 step current pickup level variation as function of measured voltage magnitude in Slope mode
of operation
PickupCurr_OC1
VDepFact_OC1 *
PickupCurr_OC1
en05000323_ansi.vsd
ANSI05000323 V1 EN-US
Figure 397: Example for OC1 step current pickup level variation as function of measured voltage magnitude in Step mode of
operation
This feature will simply change the set overcurrent pickup level in accordance with magnitude variations
of the measured voltage. It shall be noted that this feature will as well affect the pickup current value for
calculation of trip times for IDMT curves (overcurrent with IDMT curve will trip faster during low voltage
conditions).
The overcurrent protection step operation can be made dependent of a restraining current quantity (see
table 430). Practically then the pickup level of the overcurrent step is not constant but instead increases
with the increase in the magnitude of the restraining current.
Imeasured
StartCurr_OC2
StartCurr_OC1
Atan(RestrCoeff)
Restraint
IEC05000255 V2 EN-US
This feature will simply prevent overcurrent step to pickup if the magnitude of the measured current
quantity is smaller than the set percentage of the restrain current magnitude. However this feature will
not affect the pickup current value for calculation of trip times for IDMT curves. This means that the
IDMT curve trip time will not be influenced by the restrain current magnitude.
When set, the pickup signal will start definite time delay or inverse (IDMT) time delay in accordance
with the end user setting. If the pickup signal has value one for longer time than the set time delay, the
overcurrent step will set its trip signal to one. Reset of the pickup and trip signal can be instantaneous or
time delay in accordance with the end user setting.
Two undercurrent protection steps are available. They are absolutely identical and therefore only one will
be explained here. Undercurrent step simply compares the magnitude of the measured current quantity
(see table 428) with the set pickup level. The undercurrent step will pickup and set its pickup signal to
one if the magnitude of the measured current quantity is smaller than this set level. The pickup signal will
start definite time delay with set time delay. If the pickup signal has value one for longer time than the set
time delay the undercurrent step will set its trip signal to one. Reset of the pickup and trip signal can be
instantaneous or time delay in accordance with the setting.
Two overvoltage protection steps are available. They are absolutely identical and therefore only one will
be explained here.
Overvoltage step simply compares the magnitude of the measured voltage quantity (see table 429) with
the set pickup level. The overvoltage step will pickup if the magnitude of the measured voltage quantity
is bigger than this set level.
The pickup signal will start definite time delay or inverse (IDMT) time delay in accordance with the end
user setting. If the pickup signal has value one for longer time than the set time delay, the overvoltage
step will set its trip signal to one. Reset of the pickup and trip signal can be instantaneous or time delay
in accordance with the end user setting.
If the Prog. inv. curve is chosen for operation and the set parameters B_OVx and C_OVx
(where x = 1, 2) do not satisfy the equation (B_OVx * 0.02 - C_OVx > 0.0), then no TRIP
signal is issued. However, START signal is set and maintained as long as the measured
quantity for operation is above the set start level of step.
Two undervoltage protection steps are available. They are absolutely identical and therefore only one
will be explained here.
Undervoltage step simply compares the magnitude of the measured voltage quantity (see table 429)
with the set pickup level. The undervoltage step will pickup if the magnitude of the measured voltage
quantity is smaller than this set level.
The pickup signal will start definite time delay or inverse (IDMT) time delay in accordance with the end
user setting. If the pickup signal has value one for longer time than the set time delay, the undervoltage
step will set its trip signal to one. Reset of the pickup and trip signal can be instantaneous or time delay
in accordance with the end user setting.
If the Prog. inv. curve is chosen for operation and the set parameters B_UVx and C_UVx
(where x = 1, 2) do not satisfy the equation (B_UVx * 0.02 - C_UVx > 0.0), then no TRIP
signal is issued. However, START signal is set and maintained as long as the measured
quantity for operation is below the set start level of step.
The simplified internal logics, for CVGAPC function are shown in the following figures.
The following currents and voltages are inputs to the multipurpose protection function. They must all be
expressed in true power system (primary) Amperes and kilovolts.
1. Instantaneous values (samples) of currents & voltages from one three-phase current and one three-
phase voltage input.
2. Fundamental frequency phasors from one three-phase current and one three-phase voltage input
calculated by the pre-processing modules.
3. Sequence currents & voltages from one three-phase current and one three-phase voltage input
calculated by the pre-processing modules.
1. Selects one current from the three-phase input system (see table 428) for internally measured
current.
2. Selects one voltage from the three-phase input system (see table 429) for internally measured
voltage.
3. Selects one current from the three-phase input system (see table 430) for internally measured
restraint current.
CURRENT
UC1
nd TRUC1
2 Harmonic
Selected current restraint
PU_UC2
UC2
TRUC2
2nd Harmonic
restraint
PU_OC1
OC1 TROC1
nd
2 Harmonic BLK2ND
restraint OR
Selected restraint current
Current restraint
DIROC1
Directionality
Voltage control /
restraint
PU_OC2
OC2 TROC2
2nd Harmonic
restraint
Current restraint OR
VDIRLOW
Directionality DIROC2
Voltage control /
restraint
PU_OV1
OV1 TROV1
PU_OV2
OV2 TROV2
PU_UV1
Selected voltage
UV1 TRUV1
PU_UV2
UV2 TRUV2
VOLTAGE
en05000170_ansi.vsd
ANSI05000170 V1 EN-US
Figure 399: CVGAPC function main logic diagram for built-in protection elements
1. The selected currents and voltage are given to built-in protection elements. Each protection element
and step makes independent decision about status of its PICKUP and TRIP output signals.
2. More detailed internal logic for every protection element is given in the following four figures.
3. Common PICKUP and TRIP signals from all built-in protection elements & steps (internal OR logic)
are available from multipurpose function as well.
a Freeze Timers
a>b AND
BlkLevel2nd b
Voltage
control or Directionality DIR_OK Inverse
time
restraint check selected
feature
ANSI05000831‐2‐en.vsdx
ANSI05000831 V2 EN-US
Figure 400: Simplified internal logic diagram for built-in first overcurrent step that is, OC1 (step OC2 has the same internal logic)
BLKUC1TR
a
a>b Freeze Timer
AND
BlkLevel2nd b
Enable
second Second harmonic
harmonic check
a TRUC1
b>a
DEF AND
b
PickupCurr_UC1
AND
Operation_UC1=On
PU_UC1
BLKUC1
ANSI05000750‐2‐en.vsdx
ANSI05000750 V2 EN-US
Figure 401: Simplified internal logic diagram for built-in first undercurrent step that is, UC1 (step UC2 has the same internal logic)
Inverse
Operation_OV1=On
Inverse time
BLKOV1 selected
en05000751_ansi.vsd
ANSI05000751 V1 EN-US
Figure 402: Simplified internal logic diagram for built-in first overvoltage step OV1 (step OV2 has the same internal logic)
Inverse
Operation_UV1=On
Inverse time
BLKUV1 selected
en05000752_ansi.vsd
ANSI05000752 V1 EN-US
Figure 403: Simplified internal logic diagram for built-in first undervoltage step UV1 (step UV2 has the same internal logic)
When enabled, the 2nd harmonic blocking function applied in UC1, UC2, OC1 and OC2
is used to freeze the Definite and/or the Inverse Characteristics internal timers. When the
function detects a 2nd harmonic higher than the set threshold, the internal function timers
are frozen but PICKUP outputs continues to be active as long as the measured current is
above the set pickup level. Internal timers will again resume timing when harmonic content
becomes smaller than the set threshold and the measured current is higher than the pickup
value. If TRIP output is already active when harmonic blocking signal appears the TRIP
output will not be affected.
The multi-purpose filter function block (SMAIHPAC) is arranged as a three-phase filter. It has very
much the same user interface (e.g. inputs and outputs) as the standard pre-processing function block
SMAI. However the main difference is that it can be used to extract any frequency component from
the input signal. Thus it can, for example, be used to build sub-synchronous resonance protection for
synchronous generator.
SMAIHPAC
BLOCK AI3P
G3P* AI1
AI2
AI3
AI4
IEC13000180-1-en.vsd
IEC13000180 V1 EN-US
PID-6733-INPUTSIGNALS v1
PID-6733-SETTINGS v1
For all four analogue input signals into this filter (i.e. three phases and the residual quantity) the input
samples from the TRM module which are coming at rate of 20 samples per fundamental system cycle
are first stored. When enough samples are available in the internal memory, the phasor values at
set frequency defined by the setting parameter SetFrequency are calculated. The following values are
internally available for each of the calculated phasors:
• Magnitude
• Phase angle
• Exact frequency of the extracted signal
Note that the special filtering algorithm is used to extract these phasors. This algorithm is different from
the standard one-cycle Digital Fourier Filter typically used by the numerical IEDs. This filter provides
extremely good accuracy of measurement and excellent noise rejection, but at the same time it has
much slower response time. It is capable to extract phasor (i.e. magnitude, phase angle and actual
frequency) of any signal (e.g. 37,2Hz) present in the waveforms of the connected CTs and/or VTs. The
magnitude and the phase angle of this phasor are calculated with very high precision. For example
the magnitude and phase angle of the phasor can be estimated even if it has magnitude of one per
mille (i.e. 1‰ ) in comparison to the dominating signal (e.g. the fundamental frequency component).
Several instances of this function block are provided. These instances are fully synchronized between
each-other in respect of phase angle calculation. Thus if two multi-purpose filters are used for some
application, one for current and the second one for the voltage signals, the power values (i.e. P &
Q) at the set frequency can be calculated from them by the over-/under-power function or CVMMXN
measurement function block.
In addition to these phasors the following quantities are internally calculated as well:
In order to properly calculate phase-to-phase phasors from the individual phase phasors or vice versa,
the setting parameters ConnectionType is provided. It defines what quantities (i.e. individual phases or
phase-to-phase quantities) are physically connected to the IED analogue inputs by wiring. Then the IED
knows which one of them are the measured quantities and the other one is then internally calculated.
This setting is only important for the VT inputs, because the CTs are typically wye connected all the time.
Thus when this filter is used in conjunction with multi-purpose protection function or overcurrent function
or over-voltage function or over-power function many different protection applications can be arranged.
For example the following protection, monitoring or measurement features can be realized:
The filter output can also be connected to the measurement function blocks such as
CVMMXN (Measurements), CMMXU (Phase current measurement), VMMXU (Phase-phase voltage
measurement), etc.
The filter has as well additional capability to report the exact frequency of the extracted signal. Thus the
user can check the actual frequency of some phenomenon in the power system (e.g. frequency of the
sub-synchronous currents) and compare it with expected value obtained previously by either calculation
or simulation. For the whole three-phase filter group the frequency of the signal connected to the first
input (i.e. phase A) is reported. This value can be then used either by over-/under-frequency protections
or reported to the built-in HMI or any other external client via the measurement blocks such is the
CVMMXN.
How many samples in the memory are used for the phasor calculation depends on the setting parameter
FilterLength. Table 436 gives overview of the used number of samples for phasor calculation by the filter.
Note that the used number of samples is always a power of number two.
Note that the selected value for the parameter FilterLength automatically defines certain filter properties
as described below:
First in order to secure proper filter operation the selected length of the filter shall always be longer than
three complete periods of the signal which shall be extracted. Actually the best results are obtained if
at least five complete periods are available within the filtering window. Thus, this filter feature will limit
which filter lengths can be used to extract low frequency signals. For example if 16,7 Hz signal shall be
extracted the minimum filter length in milliseconds shall be:
1000
3× = 180ms
16.7
EQUATION000028 V1 EN-US (Equation 179)
Thus based on the data from Table 436 the minimum acceptable value for this parameter would be
“FilterLength = 0.2 s” but more accurate results will be obtained by using “FilterLength = 0.5 s”
Second feature which is determined by the selected value for parameter FilterLength is the capability
of the filter to separate the desired signal from the other disturbing signals which may have similar
frequency value. Note that the filter output will be the phasor with the highest magnitude within certain
“pass frequency band” around the SetFrequency. Table 437 defines the natural size of this pass
frequency band for the filter, depending on the selected value for parameter FilterLength.
Value for parameter FilterLength For 50Hz power system For 60Hz power system
0.1 s ±22.5 Hz ±27.0 Hz
0.2 s ±11.5 Hz ±14.0 Hz
0.5 s ±6.0 Hz ±7.2 Hz
1.0 s ±3.0 Hz ±3.6 Hz
2.0 s ±1.5 Hz ±1.8 Hz
4.0 s ±0.8 Hz ±1.0 Hz
Thus the longer length of the filter the better capability it has to reject the disturbing signals close to the
required frequency component and any other noise present in the input signal waveform. For example
if 46 Hz signal wants to be extracted in 50Hz power system, then from Table 437 it can be concluded
that “FilterLength=1,0 s” shall be selected as a minimum value. However if frequency deviation of the
fundamental frequency signal in the power system are taken into account it may be advisable to select
“FilterLength=2,0 s” for such application.
Note that in case when no clear magnitude peak exist in the set pass frequency band the filter will return
zero values for the phasor magnitude and angle while the signal frequency will have value minus one.
Finally the set value for parameter FilterLength also defines the response time of the filter after a step
change of the measured signal. The filter will correctly estimate the new signal magnitude once 75% of
the filter length has been filed with the new signal value (i.e. after the change).
If for any reason this natural frequency band shall be extended (e.g. to get accurate but wider filter)
it is possible to increase the pass band by entering the value different from zero for parameter
FreqBandWidth. In such case the total filter pass band can be defined as:
Example if in 60Hz system the selected values are “FilterLength =1.0 s” and “FreqBandWidth = 5.0” the
total filter pass band will be ±(3.6+5.0/2)= ± 6.1 Hz.
It shall be noted that the phasor calculation is relatively computation demanding (required certain
amount of the CPU processing time). In order to control the CPU usage for this filter, the setting
parameter OverLap is used. This setting parameter defines how often the new phasor value is
calculated during time period defined by the set value for the parameter FilterLength (see Table
436). The following list gives some examples how this parameter influence the calculation rate for the
extracted phasor:
• when OverLap=0% the new phasor value is calculated only once per FilterLength
• when OverLap=50% the new phasor value is calculated two times per FilterLength
• when OverLap=75% the new phasor value is calculated four times per FilterLength
• when OverLap=90% the new phasor value is calculated ten times per FilterLength
Filterlength of SMAIHPAC shall be properly coordinated with the operate times of the
functions that are consuming SMAIHPAC data, in order to prevent inadvertent operation.
In the following Figure an example from an installation of this filter on a large, 50 Hz turbo generator
with a rating in excess of 1000 MVA is presented. In this installation filter is used to measure the stator
sub-synchronous resonance currents. For this particular installation the following settings were used for
the filter:
• SetFrequency= 31.0 Hz
• FilterLength= 1.0 s
• OverLap = 75%
• FreqBandWidth= 0.0 Hz
IEC13000178-2-en.vsd
IEC13000178 V3 EN-US
The data shown in the Figure comes from the COMTRADE file captured by the IED. The following traces
are presented in this Figure.
b) RMS value of the sub-synchronous resonance current extracted by the filter in primary amperes.
c) Frequency of the extracted sub-synchronous resonance current provided by the filter in Hz.
Note the very narrow scale on the y-axle for b) and c). Such small scale as well indicates with which
precision and consistency the filter calculates the phasor magnitude and frequency of the extracted
stator sub-synchronous current component.
With above given settings the sub-synchronous current magnitude and frequency are calculated
approximately four times per second (that is, correct value is four times per 1024 ms).
15.1.1 Identification
M14870-1 v6
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Current circuit supervision CCSSPVC - 87
Open or short circuited current transformer cores can cause unwanted operation of many protection
functions such as differential, ground-fault current and negative-sequence current functions.
Current circuit supervision (CCSSPVC, 87) compares the residual current from a three phase set of
current transformer cores with the neutral point current on a separate input taken from another set of
cores on the current transformer.
A detection of a difference indicates a fault in the circuit and is used as alarm or to block protection
functions expected to give inadvertent tripping.
CCSSPVC (87)
I3P* FAIL
IREF* ALARM
BLOCK
ANSI13000304-1-en.vsd
ANSI13000304 V1 EN-US
15.1.4 Signals
PID-6806-INPUTSIGNALS v2
15.1.5 Settings
PID-6806-SETTINGS v2
Current circuit supervision CCSSPVC (87) compares the absolute value of the vectorial sum of the
three phase currents |ΣIphase| and the numerical value of the residual current |Iref| from another current
transformer set, shown in Figure 406.
The FAIL output will be set to high when the following criteria are fulfilled:
• The numerical value of the difference |ΣIphase| – |Iref| is higher than 80% of the numerical value of the
sum |ΣIphase| + |Iref|.
• The numerical value of the current |ΣIphase| – |Iref| is equal to or higher than the set trip value IMinOp.
• No phase current has exceeded Pickup_Block during the last 10 ms.
• CCSSPVC (87) is enabled by setting Operation = Enabled.
The FAIL output remains activated 100 ms after the AND-gate resets when being activated for more
than 20 ms. If the FAIL lasts for more than 150 ms an ALARM will be issued. In this case the FAIL and
ALARM will remain activated 1 s after the AND-gate resets. This prevents unwanted resetting of the
blocking function when phase current supervision element(s) trip, for example, during a fault.
IA IA I>1.054 * IMinOp
IB IB +
IC -
IC
+ +
Iref Iref + x -
0,8
I>IP>Block
10 ms AND
OR FAIL
OR t
40 ms 100 ms
ANSI05000463-2-en.vsd
ANSI05000463 V2 EN-US
Figure 406: Simplified logic diagram for Current circuit supervision CCSSPVC (87)
| åI phase | - | I ref |
Slope = 1
Operation
Slope = 0.8
area
I MinOp
| åI phase | + | I ref |
99000068.vsd
IEC99000068 V1 EN-US
Due to the formulas for the axis compared, |SIphase | - |I ref | and |S I phase | + | I ref |
respectively, the slope can not be above 1.
15.2.1 Identification
M14869-1 v5
Function description8 IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Fuse failure supervision FUFSPVC - -
The aim of the fuse failure supervision function (FUFSPVC) is to block voltage measuring functions
at failures in the secondary circuits between the voltage transformer and the IED in order to avoid
inadvertent operations that otherwise might occur.
The fuse failure supervision function basically has three different detection methods, negative sequence
and zero sequence based detection and an additional delta voltage and delta current detection.
The negative sequence detection algorithm is recommended for IEDs used in isolated or high-
impedance grounded networks. It is based on the negative-sequence quantities.
The zero sequence detection is recommended for IEDs used in directly or low impedance grounded
networks. It is based on the zero sequence measuring quantities.
The selection of different operation modes is possible by a setting parameter in order to take into
account the particular grounding of the network.
A criterion based on delta current and delta voltage measurements can be added to the fuse failure
supervision function in order to detect a three phase fuse failure, which in practice is more associated
with voltage transformer switching during station operations.
FUFSPVC
I3P* BLKZ
V3P* BLKV
BLOCK 3PH
52A DLD1PH
MCBOP DLD3PH
89B PU_DI
BLKTRIP PU_DI_A
PU_DI_B
PU_DI_C
PU_DV
PU_DV_A
PU_DV_B
PU_DV_C
ANSI14000065-1-en.vsd
ANSI14000065 V1 EN-US
15.2.4 Signals
PID-3492-INPUTSIGNALS v9
15.2.5 Settings
PID-3492-SETTINGS v9
The zero and negative sequence function continuously measures the currents and voltages in all three
phases and calculates, see figure 409:
The measured signals are compared with their respective set values 3V0PU and 3I0PU, 3V2PU and
3I2PU.
The function enable the internal signal FuseFailDetZeroSeq if the measured zero-sequence voltage is
higher than the set value 3V0PU and the measured zero-sequence current is below the set value 3I0PU.
The function enable the internal signal FuseFailDetNegSeq if the measured negative sequence voltage
is higher than the set value 3V2PU and the measured negative sequence current is below the set value
3I2PU.
A drop out delay of 100 ms for the measured zero-sequence and negative sequence current will prevent
a false fuse failure detection at un-equal breaker opening at the two line ends.
Sequence Detection
3I0PU CurrZeroSeq
IA
Zero 3I0
sequence
filter CurrNegSeq
a
IB a>b 100 ms
b 0
Negative 3I2
sequence
IC filter FuseFailDetZeroSeq
AND
a
a>b 100 ms
3I2PU b 0
FuseFailDetNegSeq
AND
3V0PU
VoltZeroSeq
VA
Zero
sequence
a 3V0
a>b
b
filter
VB VoltNegSeq
Negative
sequence a 3V2
a>b
VC filter b
3V2PU
ANSI10000036-2-en.vsd
ANSI10000036 V2 EN-US
The calculated values 3V0, 3I0, 3I2 and 3V2 are available as service values on local HMI and monitoring
tool in PCM600.
The output signals 3PH, BLKV and BLKZ as well as the signals DLD1PH and DLD3PH from dead line
detections are blocked if any of the following conditions occur:
The input BLOCK signal is a general purpose blocking signal of the fuse failure supervision function.
It can be connected to a binary input of the IED in order to receive a block command from external
devices or can be software connected to other internal functions of the IED itself in order to receive a
block command from internal functions. Through OR gate it can be connected to both binary inputs and
internal function outputs.
The input BLKTRIP is intended to be connected to the trip output from any of the protection functions
included in the IED. When activated for more than 20 ms, the operation of the fuse failure is blocked; a
fixed drop-out timer prolongs the block for 100 ms. The aim is to increase the security against unwanted
operations during the opening of the breaker, which might cause unbalance conditions for which the fuse
failure might operate.
The output signal BLKZ will also be blocked if the internal dead line detection is activated. The dead line
detection signal has a 200 ms drop-out time delay.
The input signal MCBOP is supposed to be connected via a terminal binary input to the N.C. auxiliary
contact of the miniature circuit breaker protecting the VT secondary circuit. The MCBOP signal sets the
output signals BLKV and BLKZ in order to block all the voltage related functions when the MCB is open
independent of the setting of OpModeSel selector. The additional drop-out timer of 150 ms prolongs the
presence of MCBOP signal to prevent the unwanted operation of voltage dependent function due to non
simultaneous closing of the main contacts of the miniature circuit breaker.
The input signal 89b is supposed to be connected via a terminal binary input to the N.C. auxiliary contact
of the line disconnector. The 89b signal sets the output signal BLKV in order to block the voltage related
functions when the line disconnector is open. The impedance protection function is not affected by the
position of the line disconnector since there will be no line currents that can cause malfunction of the
distance protection. If 89b=0 it signifies that the line is connected to the system and when the 89b=1 it
signifies that the line is disconnected from the system and the block signal BLKV is generated.
The output BLKV can be used for blocking the voltage related measuring functions (undervoltage
protection, energizing check and so on) except for the impedance protection.
The function output BLKZ shall be used for blocking the impedance protection function.
A simplified diagram for the functionality is found in figure 410. The calculation of the changes of
currents and voltages is based on a sample analysis algorithm. The calculated delta quantities are
compared with their respective set values DIPU and DVPU. The algorithm detects a fuse failure if a
sufficient change in voltage without a sufficient change in current is detected in each phase separately.
The following quantities are calculated in all three phases:
The internal FuseFailDetDVDI signal is activated if the following conditions are fulfilled:
• The magnitude of the phase-ground voltage has been above VPPU for more than 1.5 cycles (i.e. 30
ms in a 50 Hz system)
• The magnitude of DV in three phases are higher than the corresponding setting DVPU
In addition to the above conditions, at least one of the following conditions shall be fulfilled in order to
activate the internal FuseFailDetDVDI signal:
• The magnitude of the phase currents in three phases are higher than the setting IPPU
• The circuit breaker is closed (52A = True)
The first criterion means that detection of failure in three phases together with high current for the three
phases will set the output. The measured phase current is used to reduce the risk of false fuse failure
detection. If the current on the protected line is low, a voltage drop in the system (not caused by fuse
failure) may be followed by current change lower than the setting DIPU, and therefore a false fuse failure
might occur.
The second criterion requires that the delta condition shall be fulfilled at the same time as circuit breaker
is closed. If this is an important disadvantage, connect the 52A input to FALSE , then only the first
criterion can enable the delta function. If the DVDI detection of three phases set the internal signal
FuseFailDetDVDI at the level high, then the signal FuseFailDetDVDI will remain high as long as the
voltage of three phases are lower then the setting VPPU.
In addition to fuse failure detection, two internal signals DeltaV and DeltaI are also generated by the
delta current and delta voltage DVDI detection algorithm. The internal signals DelatV and DeltaI are
activated when a sudden change of voltage, or respectively current, is detected. The detection of the
sudden change is based on a sample analysis algorithm. In particular DelatV is activated if at least three
consecutive voltage samples are higher then the setting DVPU. In a similar way DelatI is activated if
at least three consecutive current samples are higher then the setting DIPU. When DeltaV or DeltaI
are active, the output signals PU_DV_A, PU_DV_B, PU_DV_C and respectively PU_DI_A, PU_DI_B,
PU_DI_C, based on a sudden change of voltage or current detection, are activated with a 20 ms time off
delay. The common pickup output signals PU_DV or PU_DI are activated with a 60 ms time off delay, if
any sudden change of voltage or current is detected.
The delta function (except the sudden change of voltage and current detection) is
deactivated by setting the parameter OpDVDI to Disabled.
DVDI Detection
DVDI detection Phase 1
IA
IB
IC DI detection based on sample analysis
DIPU DeltaIA
VA
IA DeltaIB
DVDI detection Phase 2
IB DeltaVB
IC
VB Same logic as for phase 1
IA
DVDI detection Phase 3 DeltaIC
IB
DeltaVC
IC
VC Same logic as for phase 1
VA
a
a<b
b
IA
a
a>b
50P b AND
OR AND
52A AND OR
VB
a
a<b
b
IB
a
a>b
b AND
OR AND
AND OR
VC
a
a<b
b
IC
a
a>b
b AND
OR AND
AND OR FuseFailDetDVDI
AND
ANSI12000166-3-en.vsd
ANSI12000166 V3 EN-US
Figure 410: Simplified logic diagram for the DV/DI detection part
intBlock
PU_DI
AND
DeltaIA 0
20 ms OR AND PU_DI_A
DeltaIB
0
20 ms PU_DI_B
AND
DeltaIC 0
20 ms
PU_DI_C
AND
AND PU_DV
DeltaVA 0 PU_DV_A
20 ms OR AND
DeltaVB 0
20 ms PU_DV_B
AND
DeltaVC 0
20 ms
PU_DV_B
AND
ANSI12000165-2-en.vsd
ANSI12000165 V2 EN-US
Figure 411: Internal signals DeltaV or DeltaI and the corresponding output signals
A simplified diagram for the functionality is found in figure 412. A dead phase condition is indicated if
both the voltage and the current in one phase is below their respective setting values VDLDPU and
IDLDPU. If at least one phase is considered to be dead the output DLD1PH and the internal signal
DeadLineDet1Ph is activated. If all three phases are considered to be dead the output DLD3PH is
activated
IC
a
a<b
b
IDLDPU
DeadLineDet1Ph
VA
a AND
a<b
b OR DLD1PH
AND
VB
a AND
a<b
b
AND DLD3PH
VC AND
a AND
a<b
b
VDLDPU
intBlock
ANSI0000035-1-en.vsd
ANSI0000035 V1 EN-US
Figure 412: Simplified logic diagram for Dead Line detection part
A simplified diagram for the functionality is found in figure 413. The fuse failure supervision function
(FUFSPVC) can be switched on or off by the setting parameter Operation to Enabled or Disabled.
For increased flexibility and adaptation to system requirements an operation mode selector, OpModeSel,
has been introduced to make it possible to select different operating modes for the negative and zero
sequence based algorithms. The different operation modes are:
The delta function can be activated by setting the parameter OpDVDI to Enabled. When selected it
operates in parallel with the sequence based algorithms.
If the fuse failure situation is present for more than 5 seconds and the setting parameter SealIn is set
to Enabled it will be sealed in as long as at least one phase voltage is below the set value VSealInPU.
This will keep the BLKV and BLKZ signals activated as long as any phase voltage is below the set value
VSealInPU. If all three phase voltages drop below the set value VSealInPU and the setting parameter
SealIn is set to Enabled the output signal 3PH will also be activated. The signals 3PH, BLKV and BLKZ
signals will now be active as long as any phase voltage is below the set value VSealInPU.
If SealIn is set to Enabled the fuse failure condition is stored in the non-volatile memory in the IED. At
start-up of the IED (due to auxiliary power interruption or re-start due to configuration change) it uses the
stored value in its non-volatile memory and re-establishes the conditions that were present before the
shut down. All phase voltages must be greater than VSealInPU before fuse failure is de-activated and
resets the signals BLKU, BLKZ and 3PH.
The output signal BLKV will also be active if all phase voltages have been above the setting VSealInPU
for more than 60 seconds, the zero or negative sequence voltage has been above the set value 3V0PU
and 3V2PU for more than 5 seconds, all phase currents are below the setting IDLDPU (criteria for open
phase detection) and the circuit breaker is closed (input 52a is activated).
If a MCB is used then the input signal MCBOP is to be connected via a binary input to the N.C. auxiliary
contact of the miniature circuit breaker protecting the VT secondary circuit. The MCBOP signal sets the
output signals BLKV and BLKZ in order to block all the voltage related functions when the MCB is open
independent of the setting of OpModeSel or OpDVDI. An additional drop-out timer of 150 ms prolongs
the presence of MCBOP signal to prevent the unwanted operation of voltage dependent function due to
non simultaneous closing of the main contacts of the miniature circuit breaker.
The input signal 89b is supposed to be connected via a terminal binary input to the N.C. auxiliary contact
of the line disconnector. The 89b signal sets the output signal BLKV in order to block the voltage related
functions when the line disconnector is open. The impedance protection function does not have to be
affected since there will be no line currents that can cause malfunction of the distance protection.
TEST ACTIVE
AND
BlocFuse = Yes
BLOCK intBlock
OR
BLKTRIP 20 ms 100 ms
AND t t
FusefailStarted
AND
Any VL < VSealInPU
FuseFailDetDUDI
AND 5s
OpDVDI = Enabled
OR t
FuseFailDetZeroSeq
AND
AND
FuseFailDetNegSeq
AND
V2I2 OR
V0I0 OR
V0I0 OR V2I2
OpModeSel
V0I0 AND V2I2
OptimZsNs
OR
CurrZeroSeq
a AND
CurrNegSeq a>b
b
AND
200 ms
DeadLineDet1Ph AND BLKZ
t OR AND
150 ms
MCBOP t
AND BLKV
60 s
t OR OR
All VL > VSealInPU
AND
VoltZeroSeq 5s
VoltNegSeq OR t
AllCurrLow
52a
89b
ANSI10000033-3-en.vsd
ANSI10000033 V3 EN-US
Figure 413: Simplified logic diagram for fuse failure supervision function, Main logic
Different protection functions within the protection IED operates on the basis of measured voltage at the
relay point. Some example of protection functions are:
These functions can operate unintentionally, if a fault occurs in the secondary circuits between voltage
instrument transformers and the IED. These unintentional operations can be prevented by fuse failure
supervision (VDSPVC).
VDSPVC is designed to detect fuse failures or faults in voltage measurement circuit, based on phase
wise comparison of voltages of main and pilot fused circuits. VDSPVC blocking output can be configured
to block functions that need to be blocked in case of faults in the voltage circuit.
VDSPVC (60)
V3P1* MAINFUF
V3P2* PILOTFUF
BLOCK V1AFAIL
V1BFAIL
V1CFAIL
V2AFAIL
V2BFAIL
V2CFAIL
ANSI14000057-1-en.vsd
ANSI12000142 V2 EN-US
15.3.4 Signals
PID-3485-INPUTSIGNALS v8
15.3.5 Settings
PID-3485-SETTINGS v8
VDSPVC requires six voltage inputs, which are the three phase voltages on main and pilot fuse groups.
The initial voltage difference between the two groups is theoretical zero in the healthy condition. Any
subsequent voltage difference will be due to a fuse failure.
If the main fuse voltage becomes smaller than the pilot fuse voltage (vMainA < vPilotA or vMainB <
vPilotB or vMainC < vPilotC) and the voltage difference exceeds the operation level (Vdif Main block),
a blocking signal will be initiated to indicate the main fuse failure and block the voltage-dependent
functions. In addition, the function also indicates the phase in which the voltage reduction has occurred.
If the pilot fuse voltage becomes smaller than the main fuse voltage (vPilotA < vMainA or vPilotB <
vMainB or vPilotC < vMainC) and the voltage difference exceeds the operation level (Vdif Pilot alarm),
an alarm signal will be initiated to indicate the pilot fuse failure and also the faulty phase where the
voltage reduction occurred.
When SealIn is set to Enabled and the fuse failure has last for more than 5 seconds, the blocked
protection functions will remain blocked until normal voltage conditions are restored above the VSealIn
setting. Fuse failure outputs are deactivated when normal voltage conditions are restored.
a 5s
a<b AND OR t
0
VSealIn b
SealIn=0
vPilotA
+
vMainA -
MAX a V1AFAIL
OR
a>b AND
Vdif Main block b MAINFUF
OR
0
MIN ABS a
a>b AND V2AFAIL
Vdif Pilot alarm b
BLOCK
OR PILOTFUF
vPilotB V1BFAIL
vMainB Phase B, same as Phase A V2BFAIL
vPilotC V1CFAIL
vMainC Phase C, same as Phase A V2CFAIL
ANSI12000144-3-en.vsd
ANSI12000144 V3 EN-US
15.4.1 Identification
GUID-C7108931-DECA-4397-BCAF-8BFF3B57B4EF v2
Delta supervision function is used to quickly detect (sudden) changes in the network. This can, for
example, be used to detect faults in the power system networks and islanding in grid networks. Voltage
based delta supervision (DELVSPVC) (78V) is needed at the grid interconnection point.
DELVSPVC (78V)
V3P* BFI_3P
BLOCK PICKUP_A
PICKUP_B
STARTL3
STRISE
STRISE_A
STRISE_B
STRISEL3
STLOW
STLOW_A
STLOW_B
STLOWL3
DELMAG_A
DELMAG_B
DELMAGL3
ANSI18000007‐1‐en.vsdx
ANSI18000007 V1 EN-US
15.4.4 Signals
PID-7097-INPUTSIGNALS v1
15.4.5 Settings
PID-7097-SETTINGS v1
The delta supervision function DELVSPVC (78V) is a phase segregated function with the following
features.
Signal pre‐processing
fundamental DFT
opMode= RMS/DFTMag
harmonic extraction
Magnitude based STARTMAG
delta calculation DELMAGLx
MinValueCheck AND
BLOCK
ANSI18000008-1-en.vsdx
ANSI18000008 V1 EN-US
Figure 417: Simplified logic diagram for voltage based delta supervision DELVSPVC(78V)
The setting UminVmin is used to check and release the signals for the delta supervision. The delta
detection is blocked for 2 cycles by UminVmin comparator for angle shift mode.
• Instantaneous 1 cycle
• Instantaneous 2 cycle
• True RMS
• DFT mag
• Vector Shift
This method uses the instantaneous samples for delta detection. The logic of this scheme is shown in
Figure 418. The instantaneous difference between the present sample and the one cycle (or two cycle)
old sample is used for the delta detection. The change (delta) is verified for three continuous samples in
order to release the start signal. Once the start signal is set, any subsequent change in sample values
within 60 ms will not be detected. The DELU> setting will be set in % of UB. The sample based delta is
selectable for one cycle/two cycle operation, based on the OpMode setting.
‐ Abs
60ms
>
StartSampleDelta
AND t
DelU>
q‐1
q‐1
IEC17000199-2-en.vsdx
IEC17000199 V2 EN-US
Figure 418: Simplified logic diagram for sample based delta detection
This mode uses the RMS or DFT magnitude value of the voltage signal for the delta detection. The logic
of this scheme is given in Figure 419. Difference between the present value and the old value is used for
the delta detection. The old value is chosen based on the setting DeltaT, which is defined as the number
of old power cycles.
The function has an execution cycle time of 3 ms. For a DeltaT setting of 3, the old value is
60 ms. Therefore, accuracy of the old cycle data depends upon the execution cycle.
The output of the comarator is ascertained for half a cycle before releasing a STARTMAG signal. In
DELVSPVC, the DelU> setting is set in % of UB. RMS based delta will have poor accuracy if the signal
contains harmonics and other frequency components. DFT Mag based delta will operate better in these
conditions.
Additional information for the STARTRISE and STARTLOW outputs of the delta are also available in
this mode. The STARTRISE and STARTLOW outputs will be sealed by the start signal. These outputs
explains the reason for the STARTMAG signal.
Seal‐in STARTLOW
logic
0.1
>
IEC17000200-2-en.vdsx
IEC17000200 V2 EN-US
Figure 419: Simplified logic diagram for RMS/DFT based delta detection
The Vector shift selection in the OpMode setting is used to set the DELVSPVC function to operate. A
change in magnitude will not have any impact on this supervision. Angle shift is measured based on
the half cycle time (HCTime) as shown in Figure 420. The figure shows a waveform shift of 40 degree
in the voltage waveform. There are two half cycle times which are affected by this angle shift namely,
HCTime(k-1) and HCTime(k). A cumulative difference of two HCTime difference is calculated to get an
accurate estimate of the angle shift. This angle shift is compared with DelUang> setting to release the
STARTANGLE signal.
The logic for this mode is given in Figure 421. The DelUAng> setting will be set in absolute degrees.
Voltage
Angle shift
IEC17000210-1-en.vsdx
IEC17000210 V1 EN-US
Angle measurement is affected by system parameters such as frequency, load or generation. Hence, a
stabilization of the angle is also present in this mode of operation. The measured frequency is compared
with the 2 cycles old value. If the change is greater than 0.2 Hz, the STARTANGLE signal is blocked.
The output will release Angle shift mode when the measured frequency difference is continuously less
than 0.2 Hz for 2 cycles. The general logic is presented in Figure 421. In this mode STLOW, STRISE,
STLOWLx and STRISELx outputs will not be used and set as FALSE.
DelUang> STARTANGLE
Frequency difference of last 2 cycles AND
> AND
0.2 Hz
IEC18000902-1-en.vsdx
IEC18000902 V1 EN-US
Figure 421: Simplified logic diagram for angle based delta detection
15.5.1 Identification
GUID-0B735A27-6A7D-40E1-B981-91B689608495 v1
Delta supervision function is used to quickly detect (sudden) changes in the network. This can, for
example, be used to detect disturbances in the power system network. Current based delta supervision
(DELISPVC) (7I) provides selectivity between load change and the fault.
Present power system has many power electronic devices or FACTS devices, which injects a large
number of harmonics into the system. The function has additional features of 2nd harmonic blocking
and 3rd harmonic pickup level adaption. The 2nd harmonic blocking secures the operation during the
transformer charging, when high inrush currents are supplied into the system.
DELISPVC (7I)
I3P* BFI_3P
BLOCK STARTL1
STARTL2
STARTL3
STRISE
STRISEL1
STRISEL2
STRISEL3
STLOW
STLOWL1
STLOWL2
STLOWL3
ADAPTVAL
HARM2BLK
DELMAGL1
DELMAGL2
DELMAGL3
ANSI18000005-1-en.vsdx
ANSI18000005 V1 EN-US
15.5.4 Signals
PID-7098-INPUTSIGNALS v1
15.5.5 Settings
PID-7098-SETTINGS v1
The delta supervision function is a phase segregated function. Following are the features of
DELISPVC(7I):
Signal pre‐processing
fundamental DFT
opMode= RMS/DFTMag
harmonic extraction
Magnitude based STARTMAG
delta calculation DELMAGLx
DFTMagToComp
rd
3 harmonic based ADAPTVAL
adaption nd HARM2BLK
2 harmonic
blocking
AND
MinValueCheck
BLOCK
ANSI18000006-1-en.vsdx
ANSI18000006 V1 EN-US
Figure 423: Simplified logic diagram for current based delta supervision DELISPVC(7I)
The setting Imin is used to check and release the signals for the delta supervision. This setting can be
used to obtain selectivity between load current and fault current.
• Instantaneous 1 cycle
• Instantaneous 2 cycle
• True RMS
• DFT mag
This method uses the buffer of instantaneous sample for delta detection. The logic of this scheme is
given in Figure 424. The instantaneous difference between the present sample and the one cycle (or
two cycle) old sample is used for the delta detection. The change (vectorial delta) is verified for three
continuous samples in order to release the pickup signal. This delta calculation is affected by angle or
magnitude or both changes in the signal in the last one cycle/two cycle. It is also known as vectorial
delta scheme. Once the pickup signal is set, any subsequent change in sample values within 60 ms will
not be detected. The DelI> setting will be set in % of IB. The sample based delta is selectable for one
cycle/two cycle operation, based on the OpMode setting.
‐
60ms
Abs
> AND
StartSampleDelta
t
DelI>
q‐1
q‐1
IEC17000191-2-en.vsdx
IEC17000191 V2 EN-US
Figure 424: Simplified logic diagram for sample based delta detection
This mode uses the RMS or DFT magnitude value of the current signal for the delta detection. The logic
of this scheme is given in Figure 425. Difference between the present value and the old value is used for
the delta detection. The old value is chosen based on the setting DeltaT, which is defined as the number
of old power cycles.
The function has an execution cycle of 3 ms. For a DeltaT setting of 3, the old value is 60
ms. Therefore, accuracy of the old cycle data depends upon the execution cycle.
The output of the comparator is ascertained for half a cycle before releasing a STARTMAG signal. In
DELISPVC(7I), the DelI> setting is set in % of IB.
Additional information for the STARTRISE and STARTLOW outputs of the delta are also available in
this mode. The STARTRISE and STARTLOW outputs will be sealed by the pickup signal. These outputs
explains the reason for the STARTMAG signal.
Seal‐in STARTLOW
logic
0.1
>
Seal‐in STARTRISE
> logic
RMS Input Delay defined by ‐0.1
DeltaT
0. 5 cycle
‐ Abs STARTMAG
> t
DelI>
IEC17000192-2-en.vsdx
IEC17000192 V2 EN-US
Figure 425: Simplified logic diagram for RMS based delta detection
Presence of the harmonics is another reason for maloperation of the delta based protection. The
2nd harmonic blocking is an additional security feature in this function. It can be enabled by the
EnaHarm2Blk setting. If the ratio of 2nd harmonic frequency signal magnitude to the fundamental
frequency magnitude is greater than the set level harmBlkLev, then this feature will block the pickup
signal of the delta protection. The logic for this functionality is shown in Figure 426. The tON of 1.25
cycle is added to ensure a reliable harmonic blocking. The tOFF of 2 cycles is added to block the
operation during any sudden increase in the current load.
EnaHarm2Blk
2 cycles
t HARM2BLK
DFTInput‐2ndHarm AND
< 1.25 cycle
t
DFTInput ‐ fundamental
X
HarmBlkLev
IEC17000194-2-en.vsdx
IEC17000194 V2 EN-US
Figure 426: Simplified logic diagram for 2nd harmonic blocking logic
Present days power system network has high amount of the 3rd
harmonics presence due to heavy
power electronic devices. In such case, many networks modify the settings based on the 3rd harmonic
present in the system. Delta supervision can be adapted based on the 3rd harmonic present in the
signal. When OpMode is set to DFTMag and EnStValAdap is set to is Enable, then the setting DelI> will
change based on the StValGrad setting if the third harmonic is greater than the set level defined by the
Harm3Level setting. The logic for this functionality is shown in Figure 427.
DeltaMode = DFTMag
EnStValAdap = Enable/Disable
2 cycle
t ADAPTSTLEV
rd
DFTInput ‐ 3 Harmonics AND
< 1.25 cycle
DFTInput ‐ fundamental t
X
Harm3Lev
StValGrad X T DeltaMagToComp
F
DelI>
IEC17000195-2-en.vsdx
IEC17000195 V2 EN-US
Figure 427: Simplified logic diagram for 3rd harmonic restrain of MagStVal setting
Since this mode is adaptably changing the setting, the tOFF time is mandatory to ensure the reliable
operation during any sudden change.
15.6.1 Identification
GUID-66CFBA71-B3A4-489F-B7F4-F1909B75E1DD v1
Delta supervision functions are used to quickly detect (sudden) changes in the power system. Real
input delta supervision (DELSPVC) function is a general delta function. It is used to detect the change
measured qualities over a settable time period, such as:
• Power
• Reactive power
• Temperature
• Frequency
• Power factor
DELSPVC
BLOCK START
INPUT STRISE
STLOW
DELREAL
IEC17000202-1-en.vsdx
IEC17000202 V1 EN-US
15.6.4 Signals
PID-7096-INPUTSIGNALS v1
15.6.5 Settings
PID-7096-SETTINGS v1
Delta supervision of real input DELSPVC is a general delta function with the following features:
Seal‐in STARTLOW
Logic
>
0.1
Seal‐in STARTRISE
Logic
REALIN Delay defined by >
‐0.1
DeltaT
0. 5 cycle
‐ Abs
> t
DelStLevel
tHold
& t
>
MinStVal
IEC17000203-1-en.vsdx
IEC17000203 V1 EN-US
The setting MinStVal is used to check and release the signals for the delta supervision. In its initial
condition, during the first time a real value signal is detected (ascertained by the MinStVal comparator),
the delta detection is blocked for operation for the next 11 cycles. These 11 cycles are used to block any
unwanted operation during the initialization of the function.
The outputs STARTRISE and STARTLOW are released based on the difference (respectively above and
below) from the old value at the instant when the START signal is released.
Section 16 Control
16.1 Synchronism check, energizing check, and
synchronizing SESRSYN (25) IP14558-1 v4
16.1.1 Identification
M14889-1 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Synchrocheck, energizing check, SESRSYN 25
and synchronizing
sc/vc
SYMBOL-M V1 EN-US
The Synchronizing function allows closing of asynchronous networks at the correct moment including
the breaker closing time, which improves the network stability.
Synchrocheck, energizing check, and synchronizing (SESRSYN (25)) function checks that the voltages
on both sides of the circuit breaker are in synchronism, or with at least one side dead to ensure that
closing can be done safely.
SESRSYN (25) function includes a built-in voltage selection scheme for double bus and breaker-and-a-
half or ring busbar arrangements.
Manual closing as well as automatic reclosing can be checked by the function and can have different
settings.
For systems, which can run asynchronously, a synchronizing feature is also provided. The main purpose
of the synchronizing feature is to provide controlled closing of circuit breakers when two asynchronous
systems are in phase and can be connected. The synchronizing feature evaluates voltage difference,
phase angle difference, slip frequency and frequency rate of change before issuing a controlled closing
of the circuit breaker. Breaker closing time is a setting.
SESRSYN (25)
V3PB1* SYNOK
V3PB2* AUTOSYOK
V3PL1* AUTOENOK
V3PL2* MANSYOK
BLOCK MANENOK
BLKSYNCH TSTSYNOK
BLKSC TSTAUTSY
BLKENERG TSTMANSY
BUS1_OP TSTENOK
BUS1_CL VSELFAIL
BUS2_OP B1SEL
BUS2_CL B2SEL
LINE1_OP L1SEL
LINE1_CL L2SEL
LINE2_OP SYNPROGR
LINE2_CL SYNFAIL
VB1OK VOKSYN
VB1FF VDIFFSYN
VB2OK FRDIFSYN
VB2FF FRDIFFOK
VL1OK FRDERIVA
VL1FF VOKSC
VL2OK VDIFFSC
VL2FF FRDIFFA
STARTSYN PHDIFFA
TSTSYNCH FRDIFFM
TSTSC PHDIFFM
TSTENERG INADVCLS
AENMODE VDIFFME
MENMODE FRDIFFME
PHDIFFME
VBUS
VLINE
MODEAEN
MODEMEN
ANSI14000060-1-en.vsd
ANSI10000046 V2 EN-US
16.1.4 Signals
PID-6724-INPUTSIGNALS v1
16.1.5 Settings
PID-6724-SETTINGS v2
The synchronism check feature measures the conditions across the circuit breaker and compares them
to set limits. The output for closing operation is given when all measured quantities are simultaneously
within their set limits.
The energizing check feature measures the bus and line voltages and compares them to both high and
low threshold detectors. The output is given only when the actual measured quantities match the set
conditions.
The synchronizing feature measures the conditions across the circuit breaker, and also determines the
angle change occurring during the closing delay of the circuit breaker, from the measured slip frequency.
The output is given only when all measured conditions are simultaneously within their set limits. The
closing of the output is timed to give closure at the optimal time including the time needed for the circuit
breaker and the closing circuit operation.
The voltage difference, frequency difference and phase angle difference values are measured in the IED
centrally and are available for the synchronism check function for evaluation. By setting the phases used
for SESRSYN, with the settings SelPhaseBus1, SelPhaseBus2, SelPhaseLine1 and SelPhaseLine2, a
compensation is made automatically for the voltage amplitude difference and the phase angle difference
caused if different setting values are selected for both sides of the breaker. If needed, an additional
phase angle adjustment can be done for selected line voltage with the PhaseShift setting.
Some restrictions when using CBConfig selections 1½ bus CB, 1½ bus alt.CB and Tie CB
are described in Table 478 Such restriction are applicable only when a power transformer
is connected in the diameter and VT used for synchrocheck function is located on the other
side of the transformer.
For double bus single circuit breaker and breaker-and-a-half circuit breaker arrangements, the
SESRSYN (25) function blocks have the capability to make the necessary voltage selection. For double
bus single circuit breaker arrangements, selection of the correct voltage is made using auxiliary contacts
of the bus disconnectors. For breaker-and-a-half circuit breaker arrangements, correct voltage selection
is made using auxiliary contacts of the bus disconnectors as well as the circuit breakers.
The internal logic for each function block as well as, the input and outputs, and the setting parameters
with default setting and setting ranges is described in this document. For application related information,
please refer to the application manual.
M14833-3 v5
The logic diagrams that follow illustrate the main principles of the SESRSYN function components such
as Synchrocheck, Synchronizing, Energizing check and Voltage selection, and are intended to simplify
the understanding of the function.
When the function is set to OperationSC = Enabled, the measuring will start.
The function will compare the bus and line voltage values with the set values for VHighBusSC and
VHighLineSC.
If both sides are higher than the set values, the measured values are compared with the set values
for acceptable frequency, phase angle and voltage difference: FreqDiffA, FreqDiffM, PhaseDiffA,
PhaseDiffM and V DiffSC. If additional phase angle adjustment is done with the PhaseShift setting,
the adjustment factor is deducted from the line voltage before the comparison of the phase angle values.
The frequency on both sides of the circuit breaker is also measured. The frequencies must not deviate
from the rated frequency more than ±5Hz. The frequency difference between the bus frequency and the
line frequency is measured and may not exceed the set value FreqDiff.
Two sets of settings for frequency difference and phase angle difference are available and used for the
manual closing and autoreclose functions respectively, as required.
The inputs BLOCK and BLKSC are available for total block of the complete SESRSYN (25) function
and selective block of the Synchronism check function respectively. Input TSTSC will allow testing of the
function where the fulfilled conditions are connected to a separate test output.
The outputs MANSYOK and AUTOSYOK are activated when the actual measured conditions match the
set conditions for the respective output. The output signal can be delayed independently for MANSYOK
and AUTOSYOK conditions.
A number of outputs are available as information about fulfilled checking conditions. VOKSC shows that
the voltages are high, VDIFFSC, FRDIFFA, FRDIFFM, PHDIFFA, PHDIFFM shows when the voltage
difference, frequency difference and phase angle difference are out of limits.
Output INADVCLS, inadvertent circuit breaker closing, indicates that the circuit breaker has been closed
at wrong phase angle by mistake. The output is activated, if the voltage conditions are fulfilled at the
same time the phase angle difference between bus and line is suddenly changed from being larger than
60 degrees to smaller than 5 degrees.
OperationSC = Enabled
AND TSTAUTSY
AND
TSTSC
BLKSC AND
BLOCK OR
AUTOSYOK
AND
tSCA
AND 0-60 ms
0
VDiffSC
AND 50 ms
0
VHighBusSC
VOKSC
AND
VHighLineSC
VDIFFSC
1
FRDIFFA
FreqDiffA 1
PHDIFFA
PhaseDiffA 1
VDIFFME
voltageDifferenceValue
FRDIFFME
frequencyDifferenceValue
PHDIFFME
phaseAngleDifferenceValue
100 ms
AND 0 INADVCLS
PhDiff > 60° 32 ms AND
PhDiff < 5°
ANSI07000114-4-en.vsd
ANSI07000114 V4 EN-US
Figure 431: Simplified logic diagram for the auto synchronism function
When the function is set to OperationSynch = Enabled the measuring will be performed.
The function will compare the values for the bus and line voltage with the set values for VHighBusSynch
and VHighLineSynch, which is a supervision that the voltages are both live. Also the voltage difference
is checked to be smaller than the set value for VDiffSynch, which is a p.u value of set voltage
base values. If both sides are higher than the set values and the voltage difference between bus
and line is acceptable, the measured values are compared with the set values for acceptable
frequency FreqDiffMax and FreqDiffMin, rate of change of frequency FreqRateChange and phase angle
CloseAngleMax.
The measured frequencies between the settings for the maximum and minimum frequency will initiate
the measuring and the evaluation of the angle change to allow operation to be sent at the right moment
including the set tBreaker time. The calculation of the operation pulse sent in advance is using the
measured SlipFrequency and the set tBreaker time. To prevent incorrect closing pulses, a maximum
closing angle between bus and line is set with CloseAngleMax. To minimize the moment stress when
synchronizing near a power station, a narrower limit for CloseAngleMax needs to be used.
When setting the value for tBreaker the following should be considered:
• The closing time of contact on a Binary Out Module (BOM) is appr.4ms and on a Static Output Module
(SOM) appr. 1ms.
• The operating time of any auxilliary relays in the closing circuit.
• Mechanical closing time of the breaker primary contacts.
The setting CloseAngleMax is only a limitation under which which combination of the SlipFrequency and
CB closing time the Synchronizing feature is capable to operate.
For example, when CloseAngleMax = 30 deg. and tBreaker = 0.1 s then the Synchronizing feature can
handle up to 0.833 Hz as shown below:
Figure 432 below shows the dependencies between tBreaker and slip frequency for the SYNOK release
with CloseAngleMax set to 15 or 30 degrees.
1000
800
15 30
600
tBreaker [ms]
400
15 30
200
30
15
15
0
Figure 432: Dependencies between tBreaker and Slip frequency with different CloseAngleMax values
Voltage values are measured in the IED and are available for evaluation by the Synchronism check
function.
The function measures voltages on the busbar and the line to verify whether they are live or dead. This
is done by comparing with the set values VLiveBusEnerg and VDeadBusEnerg for bus energizing and
VLiveLineEnerg and VDeadLineEnerg for line energizing.
The frequency on both sides of the circuit breaker is also measured. The frequencies must not deviate
from the rated frequency more than +/-5Hz.
The Energizing direction can be selected individually for the Manual and the Automatic functions
respectively. When the conditions are met the outputs AUTOENOK and MANENOK respectively will be
activated if the fuse supervision conditions are fulfilled. The output signal can be delayed independently
for MANENOK and AUTOENOK conditions. The Energizing direction can also be selected by an integer
input AENMODE respective MENMODE, which for example, can be connected to a Binary to Integer
function block (B16I). Integers supplied shall be 1=Off, 2=DLLB, 3=DBLL and 4= Both. Not connected
input will mean that the setting is done from Parameter Setting tool. The active position can be read on
outputs MODEAEN resp MODEMEN. The modes are 0=OFF, 1=DLLB, 2=DBLL and 3=Both.
The inputs BLOCK and BLKENERG are available for total block of the complete SESRSYN (25) function
respective block of the Energizing check function. TSTENERG will allow testing of the function where
the fulfilled conditions are connected to a separate test output.
manEnergOpenBays
MANENOK
OR
TSTENERG
BLKENERG
OR
BLOCK
selectedFuseOK
VLiveBusEnerg
AND 0 – 60 s
DLLB OR tManEnerg
VDeadLineEnerg AND
OR 0
AND
BOTH
ManEnerg
VDeadBusEnerg
DBLL
AND
VLiveLineEnerg
TSTENOK
ManEnergDBDL AND AND
VMaxEnerg
fBus and fLine ±5 Hz
ANSI14000031-1-en.vsd
ANSI14000031 V1 EN-US
TSTENERG
BLKENERG
OR
BLOCK
selectedFuseOK
VLiveBusEnerg
DLLB 50ms 0 – 60 s
AND
OR t tAutoEnerg
AND OR
0 AUTOENOK
VDeadLineEnerg AND
BOTH
AutoEnerg
VDeadBusEnerg
DBLL
AND
VLiveLineEnerg
TSTENOK
VMaxEnerg AND
ANSI14000030-2-en.vsdx
ANSI14000030 V2 EN-US
BLKENERG
BLOCK OR manEnergOpenBays
AND
ManEnerg
1½ bus CB
CBConfig AND
B1QOPEN
LN1QOPEN AND
OR
B1QCLD
B2QOPEN
AND
LN2QOPEN
B2QCLD
AND
Tie CB
AND
AND
OR
AND
IEC14000032-1-en.vsd
IEC14000032 V1 EN-US
External fuse failure signals or signals from a tripped fuse switch/MCB are connected to binary inputs
that are configured to the inputs of SESRSYN (25) function in the IED. Alternatively, the internal
signals from fuse failure supervision can be used when available. There are two alternative connection
possibilities. Inputs labelled OK must be connected if the available contact indicates that the voltage
circuit is healthy. Inputs labelled FF must be connected if the available contact indicates that the voltage
circuit is faulty.
The VB1OK/VB2OK and VB1FF/VB2FF inputs are related to the busbar voltage and the VLNOK and
VLNFF inputs are related to the line voltage. Configure them to the binary input or function outputs that
indicate the status of the external fuse failure of the busbar and line voltages. In the event of a fuse
failure, the energizing check function is blocked. The synchronism check function requires full voltage on
both sides, thus no blocking at fuse failure is needed.
The voltage selection module including supervision of included voltage transformers for the different
arrangements is a basic part of the SESRSYN (25) function and determines the voltages fed to
the Synchronizing, Synchrocheck and Energizing check functions. This includes the selection of the
appropriate Line and Bus voltages and MCB supervision.
The voltage selection type to be used is set with the parameter CBConfig.
If No voltage sel. is set the voltages used will be V-Line1 and V-Bus1. This setting is also used in the
case when external voltage selection is provided. Fuse failure supervision for the used inputs must also
be connected.
The voltage selection function, selected voltages, and fuse conditions are used for the Synchronism
check and Energizing check inputs.
For the disconnector positions it is advisable to use (NO) a and (NC) b type contacts to supply
Disconnector Open and Closed positions but, it is also possible to use an inverter for one of the
positions.
If breaker or disconnector positions not are available for deciding if energizing is allowed, it is considered
to be allowed to manually energize. This is only allowed for manual energizing in breaker-and-a-half and
Tie breaker arrangements. Manual energization of a completely open diameter in 1 1/2 CB switchgear is
allowed by internal logic.
Voltage selection for a single circuit breaker with double busbars M14838-3 v11
The setting CBConfig selected for Double Bus activates the voltage selection for single CB and
double busbars. This function uses the binary input from the disconnectors auxiliary contacts BUS1_OP-
BUS1_CL for Bus 1, and BUS2_OP-BUS2_CL for Bus 2 to select between bus 1 and bus 2 voltages.
If the disconnector connected to bus 1 is closed and the disconnector connected to bus 2 is opened or
both disconnectors are closed, the bus 1 voltage is used. All other combinations use the bus 2 voltage.
The outputs B1SEL and B2SEL respectively indicate the selected Bus voltage.
The function checks the fuse failure signals for bus 1, bus 2 and line voltage transformers. Inputs
VB1OK-VB1FF supervise the MCB for Bus 1 and VB2OK-VB2FF supervises the MCB for Bus 2. VL1OK
and VL1FF supervises the MCB for the Line voltage transformer. The inputs fail (FF) or healthy (OK) can
alternatively be used dependent on the available signal. If a VT failure is detected in the selected voltage
source an output signal VSELFAIL is set. This output signal is true if the selected bus or line voltages
have a VT failure. This output as well as the function can be blocked with the input signal BLOCK. The
function logic diagram is shown in figure 436.
BUS1_OP
B1SEL
BUS1_CL AND
BUS2_OP B2SEL
NOT
BUS2_CL AND
invalidSelection
AND
bus1Voltage busVoltage
bus2Voltage
VB1OK AND
VB1FF OR
OR selectedFuseOK
AND
VB2OK AND
VB2FF OR VSELFAIL
AND
VL1OK
VL1FF OR
BLOCK
en05000779_2_ansi.vsd
ANSI05000779 V2 EN-US
Figure 436: Logic diagram for the voltage selection function of a single circuit breaker with double busbars
Note that with breaker-and-a-half schemes three Synchronism check functions must be used for the
complete diameter. Below, the scheme for one Bus breaker and the Tie breaker is described.
With the setting parameter CBConfig the selection of actual CB location in the 1½ circuit breaker
switchgear is done. The settings are: 1½ bus CB, 1½ alt. bus CB or Tie CB.
This voltage selection function uses the binary inputs from the disconnectors and circuit breakers
auxiliary contacts to select the right voltage for the SESRSYN function. For the bus circuit breaker one
side of the circuit breaker is connected to the busbar and the other side is connected either to line 1, line
2 or the other busbar depending on the selection of voltage circuit.
The fuse supervision is connected to VL1OK-VL1FF, VL2OK-VL2FF and with alternative Healthy or
Failing fuse signals depending on what is available from each fuse (MCB).
The tie circuit breaker is connected either to bus 1 or line 1 voltage on one side and the other side is
connected either to bus 2 or line 2 voltage. Four different output combinations are possible, bus to bus,
bus to line, line to bus and line to line.
Some restrictions when using CBConfig selections 1½ bus CB, 1½ bus alt.CB and Tie CB
are described in Table 478. Such restriction are applicable only when a power transformer
is connected in the diameter and VT used for synchrocheck function is located on the other
side of the transformer.
Table 478: Limitations for VT selection regarding selected value for CBConfig
CBConfig setting Possible closing Used GblBaseSel settings PhaseShift setting Conclusion
between has impact on
1½ bus CB Bus1 - Line1 GblBaseSelBus => Bus1 Line1
GblBaseSelLine => Line1
Bus1 - Line2 GblBaseSelBus => Bus1 Line2
GblBaseSelLine => Line2
Bus1 - Bus2 GblBaseSelBus => Bus1 No impact Bus1 and Bus2 must
GblBaseSelBus => Bus2 have same base voltage.
GblBaseSelLine has no impact PhaseShift setting has no
impact.
1½ bus alt.CB Bus2 - Line2 GblBaseSelBus => Bus2 Line2
GblBaseSelLine => Line2
Bus2 - Line1 GblBaseSelBus => Bus2 Line1
GblBaseSelLine => Line1
Bus2 - Bus1 GblBaseSelBus => Bus2 No impact Bus2 and Bus1 must
GblBaseSelBus => Bus1 have same base voltage.
GblBaseSelLine has no impact PhaseShift setting has no
impact.
Tie CB Bus1 - Line2 GblBaseSelBus => Bus1 Line2
GblBaseSelLine => Line2
Bus1 - Bus2 GblBaseSelBus => Bus1 No impact Bus1 and Bus2 must
GblBaseSelBus => Bus2 have same base voltage.
GblBaseSelLine has no impact PhaseShift setting has no
impact.
Bus2 - Line1 GblBaseSelBus => Bus2 Line1
GblBaseSelLine => Line1
Line1 - Line2 GblBaseSelLine => Line1 Line2 Line1 and Line2 must have
GblBaseSelLine => Line2 same base voltage.
GblBaseSelBus has no affect
The function also checks the fuse failure signals for bus 1, bus 2, line 1 and line 2. If a VT failure
is detected in the selected voltage an output signal VSELFAIL is set. This output signal is true if the
selected bus or line voltages have a MCB trip. This output as well as the function can be blocked with
the input signal BLOCK. The function block diagram for the voltage selection of a bus circuit breaker is
shown in figure 437 and for the tie circuit breaker in figure 438.
LINE1_OP
AND
L1SEL
LINE1_CL
BUS1_OP
L2SEL
BUS1_CL AND AND
B2SEL
OR
LINE2_OP
LINE2_CL AND invalidSelection
AND
BUS2_OP AND
BUS2_CL AND
line1Voltage lineVoltage
line2Voltage
bus2Voltage
VB1OK
VB1FF OR
OR selectedFuseOK
VB2OK AND
AND
VB2FF OR
VSELFAIL
VL1OK AND
AND
VL1FF OR
VL2OK
AND
VL2FF OR
BLOCK
en05000780_2_ansi.vsd
ANSI05000780 V2 EN-US
Figure 437: Simplified logic diagram for the voltage selection function for a bus circuit breaker in a breaker-and-a-half arrangement
LINE1_OP
AND
L1SEL
LINE1_CL
B1SEL
NOT
BUS1_OP AND
AND
BUS1_CL AND
line1Voltage busVoltage
bus1Voltage
LINE2_OP
L2SEL
LINE2_CL AND
B2SEL
NOT
invalidSelection
OR
BUS2_OP AND
AND
BUS2_CL AND
line2Voltage lineVoltage
bus2Voltage
VB1OK AND
VB1FF OR
OR selectedFuseOK
VB2OK AND
AND
VB2FF OR
VSELFAIL
VL1OK AND
AND
VL1FF OR
VL2OK
AND
VL2FF OR
BLOCK
en05000781_2_ansi.vsd
ANSI05000781 V2 EN-US
Figure 438: Simplified logic diagram for the voltage selection function for the tie circuit breaker in breaker-and-a-half arrangement.
16.2.1 Identification
M14890-1 v8
Up to five reclosing shots can be performed. The first shot can be single-, two-, and /or three-phase
depending on the type of the fault and the selected auto reclosing mode.
Several auto reclosing functions can be provided for multi-breaker arrangements. A priority circuit allows
one circuit breaker to reclose first and the second will only close if the fault proved to be transient.
Each auto reclosing function can be configured to co-operate with the synchrocheck function.
SMBRREC (79)
ON BLOCKED
OFF SETON
BLKON READY
BLKOFF ACTIVE
RESET SUCCL
INHIBIT UNSUCCL
RI INPROGR
RI_HS 1PT1
TRSOTF 2PT1
SKIPHS 3PT1
ZONESTEP 3PT2
TR2P 3PT3
TR3P 3PT4
THOLHOLD 3PT5
CBREADY PERMIT1P
52A PREP3P
PLCLOST CLOSECMD
SYNC WFMASTER
WAIT COUNT1P
RSTCOUNT COUNT2P
MODEINT COUNT3P1
COUNT3P2
COUNT3P3
COUNT3P4
COUNT3P5
COUNTAR
MODE
ABORTED
SYNCFAIL
INHIBOUT
ANSI06000189-3-en.vsd
ANSI06000189 V3 EN-US
16.2.4 Signals
PID-6796-INPUTSIGNALS v2
16.2.5 Settings
PID-6797-SETTINGS v2
Before describing the auto reclosing function it is first necessary to define the following terminology:
The auto reclosing function can be in one of the following five statuses:
“Inactive” GUID-BF80C969-FCBE-4CAB-BF71-9590A2DB433C v2
The auto recloser is in “inactive” status when the following conditions are fulfilled:
The function will not react on any start from protection trips while in “inactive” status and no automatic
reclosing is possible.
“Ready” GUID-04F154EC-E236-40A4-A3E0-7624A2F6B132 v2
The function is in “ready” status when the following conditions are fulfilled:
The function is in “in progress” status when the following condition is fulfilled:
Start can be initiated by either protection trip command or circuit breaker position change. The second
starting alternative is only possible when enabled by a setting.
In “in progress” status the dead time starts and the status ceases when the dead time expires. Then
circuit breaker close command is given and the function changes its state into the "reclaim time" status.
The auto recloser is in “reset time” status while the following conditions are fulfilled:
A new start signal during “reset time” status forces the function to proceed to next shot and change state
into “in progress” status, as long as the last shot is not reached.
“Blocked” GUID-9C38B1BE-3772-49AE-B4B3-391CE15D5CD2 v2
The function is in “blocked” status when an external blocking signal exists. No auto reclosing is possible
in “blocked” status. Only an external signal for cancellation of the blocking can cancel this status.
From Table 484 below it is possible to see which status transitions are possible. When the auto recloser
is for instance in “inactive” status only two transition are possible:
• transition to “ready” status when the circuit breaker is ready and closed
• transition to “blocked” status by external blocking
The empty cells in the table indicate that no such transition is possible.
To comprehend this chapter better it is essential to first read chapters “Status descriptions“ and
“Description of the status transition” carefully.
The logic for most of the explained inputs, outputs, settings and internal signals, described in this
chapter, is shown in Figure 445. Other figures mentioned are in some way connected or cooperate with
Figure 445.
Before going into details in the following chapters, the short functional/feature summary is given below.
The auto reclosing function is multi-shot capable and suitable for both high-speed and delayed auto
reclosing. The function can be set to perform a single-shot, two-shot, three-shot, four-shot or five-shot
reclosing sequence. Dead times for all shots can be set independently.
• protection operation
• circuit breaker operation (when enabled by setting StartByCBOpen=On)
At the end of the dead time, provided that other conditions are fulfilled, a circuit breaker close command
signal is given. The other conditions to be fulfilled are:
• input signal SYNC is true, which typically indicates that power systems on the two sides of the circuit
breaker are in synchronism
• and that input signal CBREADY is true, typically indicating that circuit breaker springs are charged.
If a circuit breaker close command is given successfully at the end of the dead time, a reclaim time
starts. If the circuit breaker does not trip again within reclaim time, the auto recloser indicates a
successful reclosing and resets into "ready" status. If the protection trips again during the reclaim
time, the sequence advances to the next shot. If all reclosing attempts have been made and the circuit
breaker does not remain closed, the auto recloser indicates an unsuccessful reclosing. Each time a
breaker close command is given, a shot counter is incremented by one.
The auto recloser can be switched Off or On with a setting or by external control inputs. With the setting
Operation = On, the auto recloser is activated and with the setting Operation = Off it is deactivated. With
the settings Operation = On and ExternalCtrl = On, the activation and deactivation is made by signal
pulses to the ON and OFF inputs, for example, from a control system or by a control switch.
If the input conditions 52A and CBREADY, from the circuit breaker, are not fulfilled while switching the
auto recloser on, the auto recloser changes into “inactive” status and the output SETON is activated
(high). The auto recloser is not ready for auto reclosing. If, however, the circuit breaker is closed and
ready when switching the auto recloser on, the output READY is activated and the function is prepared
to start the auto reclosing cycle. The circuit breaker must have been closed for at least the set value for
setting tCBClosedMin before a start is accepted. The logic for Off or On operation is shown in Figure
440.
Operation
AND S SETON
ExternalCtrl OR
R
ON AND
OR
OFF AND
StartByCBOpen
START AND
STARTHS AND
100ms OR
autoInitiate
AND OR initiate
100ms
AND
TRSOTF
startThermal AND
CBReady
120ms
CBREADY OR S
t AND start
AND
AND
tCBClosedMin R
52A
t
52a AND
count0 AND READY
inhibit
OR
INHIBIT
ANSI16000153-1-en.vsdx
ANSI16000153 V1 EN-US
The auto reclosing mode is selected with the setting ARMode. As an alternative to the setting, the mode
can be selected by connecting an integer, for example from function block B16I, to the MODEINT input.
The six possible modes are described in Table 485 below with their corresponding MODEINT integer
value.
When a valid integer is connected to the input MODEINT the selected setting ARMode will be invalid
and the MODEINT input value will be used instead. The selected mode is reported as an integer on the
MODE output.
Please note that tripping mode of the IED is defined in Trip Logic function block SMPPTRC. For example
for two-phase faults either 2ph or 3ph tripping and consequent auto reclosing can be selected
Table 485: Type of reclosing shots at different settings of “ARMode” or integer inputs to "MODEINT"
MODEINT (Integer) ARMode Type of fault 1st shot 2nd - 5th shot
1ph 3ph 3ph
1 3ph 2ph 3ph 3ph
3ph 3ph 3ph
1ph 1ph 3ph
2 1/2/3ph 2ph 2ph 3ph
3ph 3ph 3ph
Table continues on next page
MODEINT (Integer) ARMode Type of fault 1st shot 2nd - 5th shot
1ph 1ph 3ph
3 1/2ph 2ph 2ph 3ph
3ph - -
1ph 1ph 3ph
4 1ph+1x2ph 2ph 2ph -
3ph - -
1ph 1ph 3ph
5 1/2ph+1x3ph 2ph 2ph 3ph
3ph 3ph –
1ph 1ph 3ph
6 1ph+1x2/3ph 2ph 2ph -
3ph 3ph -
A maximum of five auto reclosing shots can be selected with the setting NoOfShots. Every shot has its
own dead time setting.
The first shot differs from the other shots by the possibility to extend its dead time and to utilize up to
four different time settings for it.
For the first shot, there are separate settings for single-, two- and three-phase dead times, t1 1Ph,
t1 2Ph and t1 3Ph. If only the START input signal is applied, and an auto-reclosing program with
single-phase reclosing is selected, the auto reclosing dead time t1 1Ph will be used. If one of the TR2P
or TR3P inputs is activated in in parallel with the START input, the auto reclosing dead time for either
two-phase or three-phase auto reclosing is used.
There is also a separate time setting facility for three-phase high-speed auto reclosing, t1 3PhHS. This
high-speed auto reclosing is activated by the STARTHS input and is used when auto reclosing is done
without the requirement of synchrocheck conditions to be fulfilled. The high-speed dead time shall be
set shorter than normal first shot three-phase dead time. Note that if high-speed three-phase shot is not
successful the auto reclosing sequence will continue with shot two.
A time extension delay, tExtended t1, can be added to the dead time delay for the first shot. It is
intended to come into use if the communication channel for permissive line protection is lost. In a case
like this there can be a significant time difference in fault clearance at the two line ends, where a longer
auto reclosing dead time can be useful. This time extension is controlled by the setting Extended t1 and
the PLCLOST input. The logic for control of extended dead time is shown in Figure441 and Figure 445.
Time extension delay is not possible to add to the three-phase high-speed auto reclosing dead time, t1
3PhHS.
Extended t1
AND extendTime
PLCLOST
OR
initiate AND
AND
start
IEC16000155-1-en.vsdx
IEC16000155 V1 EN-US
Shots 2 to 5 are all three-phase shots and have only one corresponding time setting each, t2 3Ph, t3
3Ph, t4 3Ph and t5 3Ph.
When a start is applied to the auto function, it status will change from “ready” status to “in progress”
status. When the dead time has expired, the close command is issued and the reclaim time is started
and the “in progress” status will change to “reclaim time” status.
The usual way to start a reclosing sequence, is to start it when a selective line protection tripping
has occurred, by applying a signal to the START input. If the auto reclosing mode with only three-
phase reclosing is selected, activation of the START input will start the three-phase dead timer. When
alternatively the START input signal is applied, and an auto reclosing mode with single-phase reclosing
is selected, the auto reclosing dead time for single-phase is used. However if one of the TR2P or TR3P
inputs is activated in connection with the START input, the auto reclosing dead time for two-phase or
three-phase auto reclosing is used. The STARTHS input (start high-speed reclosing) can also be used
to start a separate, high-speed three-phase dead time in which case the synchrocheck condition will be
bypassed.
To start a new auto reclosing cycle, a number of conditions of input signals need to be fulfilled. The
inputs are:
• CBREADY: circuit breaker is ready for a reclosing cycle, for example, charged operating gear.
• CBCLOSED: to ensure that the circuit breaker was closed when the line fault occurred and start was
applied. The CBCLOSED condition must be present for more that the settable time tCBClosedMin.
• no BLKON or INHIBIT signal is present.
When the start has been accepted, the internal signals “start” and “initiate” are set. The internal signal
“start” is latched and the internal signal “initiate” follows the length of the signal on the START input. The
latched signal “start” can be interrupted by a signal to the INHIBIT input.
The auto recloser is normally started by selective tripping. It is either a zone 1 or communication aided
trip, or a general trip. If the general trip is used the auto recloser must be blocked, via the INHIBIT
input, from all back-up tripping. The breaker failure function must always be connected to inhibit the auto
recloser. START makes a first shot with synchrocheck conditions to be fulfilled, STARTHS makes its first
shot without any fulfilled synchrocheck conditions. The TRSOTF “trip by switch onto fault” input starts
shots 2 to 5. It may be connected to the “switch onto fault” output of line protection if multi-shot auto
reclosing is used.
In normal circumstances, the auto recloser is started with a protection trip command which resets quickly
due to fault clearing. In case the start signal lasts for a too long time, the user can set a maximum start
pulse duration tLongStartInh. This start pulse duration time is controlled by setting LongStartInhib. When
the start pulse duration signal is longer than the set maximum start pulse duration, the auto reclosing
sequence will be interrupted in the same way as if the INHIBIT input was set to true. The logic for the
control of long start pulse duration is shown in Figure 442.
LongStartInhib
start
AND
tLongStartInh
initiate
t
longStartInhibit
OR
Extended t1 AND
t13PhExtTimeout
IEC16000154-1-en.vsdx
IEC16000154 V1 EN-US
If the user wants to start the auto recloser from circuit breaker open position instead of the protection trip
signals, this starting mode is selected by enabling a setting StartByCBOpen. Typically, a circuit breaker
auxiliary contact of type normally open (NO) shall be connected to the CBCLOSED and START inputs.
Then the circuit breaker status change from closed to open will generate an auto reclosing start pulse of
limited length (100ms) subject to the usual auto recloser checks. The auto reclosing sequence continues
then as usual. Signals from manual tripping and other functions, which shall prevent auto reclosing,
need to be connected to the INHIBIT input. The logic for start from circuit breaker open position is shown
in Figure 440.
The function can also be set to proceed to the next reclosing shot (if selected) even if the external start
signal is not received but the breaker is still not closed. The user can set a required time delay for
the auto recloser to proceed without a new start with setting tAutoContWait. Also the synchrocheck
conditions not fulfilled will also make the auto recloser to proceed to next shot. This automatic
proceeding of shots is controlled by setting AutoContinue and is shown in figure 443.
tAutoContWait
t
AND
commandCloseCB
AND S
R
OR
AND
OR
cbClosed AND autoInitiate
synchroCheckOK
AutoContinue
IEC16000156-1-en.vsdx
IEC16000156 V1 EN-US
The BLKON input is used to block the auto recloser for example, when certain special service conditions
arise. The auto recloser can also be blocked by an unsuccessful reclosing attempt. This is controlled
by the setting BlockByUnsucCl. When the auto recloser is blocked it immediately resets to its initial
conditions and the ACTIVE output is unactivated. The BLOCKED output indicates that the auto recloser
is blocked. To unblock the auto recloser the BLKOFF input must be activated.
The RESET input is used to reset the auto recloser to its initial conditions. When initial starting
conditions are fulfilled again, after a reset, the auto recloser is ready for a new reclosing sequence.
If the INHIBIT input is activated it is reported on the INHIBOUT output. To ensure reliable interruption
and temporary blocking of the auto recloser a reset time delay tInhibit is used. The auto recloser will be
blocked the time set in tInhibit after the deactivation of the INHIBIT input. The following internal inhibit
signals are also affected by the setting tInhibit:
• inhibitWaitForMaster: after expiration of the tWaitForMaster time for the WAIT input to reset, the
reclosing cycle of the slave is inhibited.
• longStartInhibit: if start pulse duration is longer than the tLongStartInh time, the reclosing cycle is
inhibited.
The ABORTED output indicates that the auto recloser is inhibited while it was in one of following internal
states:
The SYNCFAIL output indicates that the auto recloser is inhibited because the synchrocheck or
energizing check condition has not been fulfilled within the set time interval, tSync. The ABORTED
output will also be activated.
The behavior of the functionality described above is described in Table 486 and Table 487 below.
Table 486: BLKON, BLKOFF, RESET, INHIBIT and SYNC behavior when the function is in "ready" status
Table 487: BLKON, BLKOFF, RESET, INHIBIT and SYNC behavior when the function is in "in progress" status
When the function has started and the dead time has elapsed during the auto reclosing sequence,
certain conditions must be fulfilled before the circuit breaker closing command is issued. In three-phase
reclosing, a synchrocheck and/or energizing check can be used. It is possible to use a synchrocheck
function in the same physical device or an external one. The synchrocheck release signal shall be
connected to the auto reclosing SYNC input. If reclosing without synchrocheck is preferred the SYNC
input can be set to TRUE (set high) permanently. The synchrocheck release signal is not checked
for single-phase or two-phase auto reclosing. When a three-phase high-speed reclosing started by
STARTHS input, synchronization is not checked either, and the state of the SYNC input is disregarded.
The SYNC input shall be true within a set time interval, tSync. If it is not, the auto reclosing is interrupted
and the SYNCFAIL and ABORTED outputs are activated.
By choosing CBReadyType = CO (circuit breaker ready for a Close-Open sequence) the readiness of
the circuit breaker is also checked before issuing the circuit breaker closing command. If the circuit
breaker has a readiness contact of type CBReadyType = OCO (circuit breaker ready for an Open-Close-
Open sequence) this condition may not be fulfilled during the dead time and at the moment of auto
reclosure. The Open-Close-Open condition was however checked at the start of the auto reclosing cycle
and it is then likely that the circuit breaker is prepared for a Close-Open sequence.
The reclaim timer, tReclaim, is started each time a circuit breaker closing command is given. If no start
occurs within this time, the auto recloser will reset. A new start received in “reclaim time” status will
move the auto recloser to “in progress” status and next shot as long as the final shot is not reached.
The auto recloser will reset and enter “inactive” status if a new start is given during the final reclaim time.
This will also happen if the circuit breaker has not been closed within set time interval tUnsucCl after
each circuit breaker close command. The latter case is controlled by setting UnsucClByCBChk. The
auto reclosing sequence is considered unsuccessful for both above cases and the UNSUCCL output is
activated.
If the circuit breaker closing command is given and the circuit breaker is closed within the set time
interval tUnsucCl, the SUCCL output is activated after the set time interval tSuccessful. The logic for
successful and unsuccessful reclosing indication is shown in Figure 444.
initiate
reclaimTimeStarted AND
OR
AND UNSUCCL
OR tUnsucCl S
AND t unsuccessful
cbClosed
AND
UnsucClByCBChk
count0
OR R
tUnsucCl tSuccessful
AND SUCCL
commandCloseCB t AND S t
R
OR
IEC16000157-1-en.vsdx
IEC16000157 V1 EN-US
Figure 445 shows the logic for most parts of an auto reclosing sequence. Figure 445 should be read
together with the other logic diagrams to get the whole picture.
IEC16000158 V1 EN-US
TR2P and INPROGR
TR3P NoOfShots 1PT1
startThermal OR 2PT1
Technical manual
selection 3PT1
Dead time
reclaimTimeStarted 3PT2
tExtended t1 tExtended t1 is 3PT3
1MRK506370-UUS Rev. S
tSync
SYNC AND t SYNCFAIL
inProgress AND
reclaimTimeStarted OR
CBReadyType wait AND ABORTED
CB OR
AND
readiness
AND inhibitWaitForMaster tInhibit
CBReady check t
OR
longStartInhibit count0
OR Counter COUNT1P
inhibitThermalStart COUNT2P
CutPulse inProgress COUNT3P1
AND Set COUNT3P2
OR COUNT3P3
OR COUNT3P4
AND
AND COUNT3P5
Reset COUNTAR
tPulse
Follow CB CLOSECB
OR
AND AND
RSTCOUNT
RESET
BLKON
BLKOFF
INHIBIT INHIBOUT
IEC16000158-1-en.vsdx
A number of outputs from the function keeps track of the actual state in the auto reclosing sequence.
745
Control
Section 16
Section 16 1MRK506370-UUS Rev. S
Control
The possible statuses are described in Table 488 below. Their mapping to output signals and their
corresponding IEC 61850 integer value is also given in the table. Mapping from IEC 61850 Ed2 standard
is also shown for the AutoRecSt data object.
Table 488: Auto reclosing status reported by IEC 61850 in priority order
Data object AutoRecSt Description for mapped Mapped output signals / Description in IEC 61850
value signals Comments Ed2
1 Ready READY Ready
2 In Progress INPROGR In Progress
3 Successful SUCCL Successful
4 Waiting for trip
5 Trip issued by protection
6 Fault disappeared
7 Wait to complete CLOSECMD Wait to complete
8 Circuit breaker closed
9 Cycle unsuccessful UNSUCCL
10
-1 Aborted by synchrocheck fail SYNCFAIL
11 Aborted ABORTED Aborted
-2 Set On, Not Ready SETON = 1, READY = 0,
ACTIVE = 0, SUCCL = 0,
UNSUCC = 0, INPROG = 0
-3 Set Off, Not Ready SETON = 0
-99 Others Means that auto recloser
is in transitional state, that
should not be visible in
steady state situation
There are several counters within the function. One for each shot and type of fault and one overall
counter for total number of circuit breaker closing commands. All counters can be reset to zero using
either the HMI command or the RSTCOUNT input or by an IEC 61850 command.
The circuit breaker closing command, CLOSECMD output is a pulse with settable duration by setting
tPulse. For circuit breakers without anti-pumping function, close pulse cutting can be used. This is
controlled by the setting CutPulse. In case of a new auto recloser start pulse, the breaker closing
command pulse is cut (interrupted). The minimum duration of the closing pulse is always 50ms.
The prepare three-phase trip, PREP3P output is usually connected to the trip function SMPPTRC to
force the coming trip to be three-phase. If the auto recloser cannot make a single-phase or two-phase
reclosing, the start from the trip function should be three-phase.
The permit single-phase trip, PERMIT1P output is the inverse of the PREP3P output. It can be
connected to a binary output relay for connection to external protection or trip relays. In case of a
total loss of auxiliary power, the output relay drops and does not allow single-phase trip.
The setting Follow CB can be used to prevent close command to be issued when dead time has expired
and circuit breaker is already closed (e.g. by manual close command). If a new start is received after the
dead time expiration the auto recloser will advance to next shot.
If input SKIPHS is activated, and simultaneously STARTHS input is initiated then actually normal three-
phase shot one with dead time "t1 3Ph" will be started.
The ZONESTEP input is used when coordination between local auto reclosers and down stream auto
reclosers is needed. If function is in "ready" status and this input is activated the auto recloser increases
its actual shot number by one and enters directly the “reclaim time” status for shot one. If a start is
received during the reclaim time, the function will proceed with the next shot (e.g. starting dead time for
shot two). Every new pulse on the ZONESTEP input will further increase the shot number. Note that
ZONESTEP input will have such effect only if local start signal was not activated, as shown in Figure
445. The setting NoOfShots limits of course the maximum number of available shots. This functionality is
controlled by the setting ZoneSeqCoord.
By activating the THOLHOLD input the auto recloser is set on hold. It can be connected to a thermal
overload protection trip signal which resets only when the thermal content has fallen to an acceptable
level, for example, 70%. As long as the signal is high, indicating that the line is hot, the auto reclosing
is halted. When the signal resets, a reclosing cycle will continue. This may cause a considerable delay
between start of the auto recloser and the breaker closing command. An external logic limiting this time
and activating the INHIBIT input can be used. The THOLHOLD input can also be used to set the auto
recloser on hold, for longer or shorter time periods, for other purposes if for some reason the auto
recloser needs to be halted. The logic for thermal protection hold is shown in Figure 446.
start inhibitThermalStart
THOLHOLD AND AND S
q-1 20ms
startThermal
AND
inhibit OR
IEC16000159-1-en.vsdx
IEC16000159 V1 EN-US
The auto recloser is set as master or slave in multi-breaker arrangements with sequential reclosing
with the setting Priority. The auto recloser for the first circuit breaker, e.g. near the busbar, is set as
master (when Priority=High) and the auto recloser for the second circuit breaker is set as slave (when
Priority=Low). While the master is in progress, it issues the WFMASTER output. After an unsuccessful
reclosing the WFMASTER output is also maintained by the UNSUCCL output.
When activating the WAIT input, in the auto recloser set as slave, every dead timer is changed to
the value of setting tSlaveDeadTime and holds back the auto reclosing operation. When the WAIT
input is reset at the time of a successful reclosing of the first circuit breaker, the slave is released to
continue the reclosing sequence after the set tSlaveDeadTime. The reason for shortening the time,
for the normal dead timers with the value of tSlaveDeadTime, is to give the slave permission to react
almost immediately when the WAIT input resets. The mimimum settable time for tSlaveDeadTime is
0.1sec because both master and slave should not send the breaker closing command at the same time.
The slave should take the duration of the breaker closing time of the master into consideration before
sending the breaker closing command. A setting tWaitForMaster sets a maximum wait time for the WAIT
input to reset. If the wait time expires, the reclosing cycle of the slave is inhibited. The maximum wait
time, tWaitForMaster for the second circuit breaker is set longer than the auto reclosing dead time plus
a margin for synchrocheck conditions to be fulfilled for the first circuit breaker. Typical setting is 2sec. In
single circuit breaker applications, the setting Priority is set to None. The logic for master-slave is shown
in Figure 447.
Master:
High (Master)
Priority
WFMASTER
inProgress AND
unsuccessful OR
Slave:
Low (Slave)
Priority
inhibitWaitForMaster
AND
start tWaitForMaster
AND t
WAIT
wait
AND slaveDeadTime
AND S
inhibit
commandCloseCB R
OR
reclaimTimeStarted
IEC16000160-1-en.vsdx
IEC16000160 V1 EN-US
If reclosing of the first circuit breaker is unsuccessful, the UNSUCCL output connected to the INHIBIT
input of the slave unit interrupts the reclosing sequence of the latter. The signals can be cross-connected
to allow simple changing of the priority by just setting the High and the Low priorities without changing
the configuration. The 52A inputs from each circuit breaker are important in multi-breaker arrangements
to ensure that the circuit breaker was closed at the beginning of the sequence. If the High priority
breaker was not closed its auto reclosing sequence will not start and the low priority breaker will just
continue its auto reclosing sequence in accordance with its normal settings.
Some examples of the timing of internal and external signals at typical transient and permanent faults
are shown below in Figure 448 to 451.
Fault
CBCLOSED
Closed Open Closed
CBREADY
START
SYNC
tReclaim
READY
INPROGR
1PT1
ACTIVE
CLOSECB t1 1Ph tPulse
PREP3P
SUCCL
Time
ANSI04000196-3-en.vsd
ANSI04000196 V3 EN-US
Fault
CB POS Open
Closed Open C C
CB READY
TR3P
SYNC
READY
INPROGR
3PT1 t1 3Ph
3PT2 t2 3Ph
ACTIVE tReset
PREP3P
UNSUCCL
Time
en04000197_ansi.vsd
ANSI04000197 V1 EN-US
Fault
AR01-CBCLOSED
AR01-CBREADY(CO)
AR01-RI
AR01-TR3P
AR01-SYNC
AR01-READY
AR01-INPROGR
AR01-1PT1
AR01-T1
AR01-T2
AR01-CLOSECMD t1s
AR01-P3P
AR01-UNSUC
tReset
en04000198_ansi.vsd
ANSI04000198 V1 EN-US
Figure 450: Permanent single-phase fault, single-pole trip, single-shot reclosing, ARMode=1/2/3ph
Fault
AR01-CBCLOSED
AR01-CBREADY(CO)
AR01-RI
AR01-TR3P
AR01-SYNC
AR01-READY
AR01-INPROGR
AR01-1PT1
AR01-T1
AR01-T2
t2
AR01-CLOSECMD t1s
AR01-P3P
AR01-UNSUC
tReset
en04000199_ansi.vsd
ANSI04000199 V1 EN-US
Figure 451: Permanent single-phase fault, single-pole trip, two-shot reclosing, ARMode=1ph + 1*2ph
The interlocking functionality blocks the possibility to operate high-voltage switching devices, for
instance when a disconnector is under load, in order to prevent material damage and/or accidental
human injury.
Each control IED has interlocking functions for different switchyard arrangements, each handling the
interlocking of one bay. The interlocking functionality in each IED is not dependent on any central
function. For the station-wide interlocking, the IEDs communicate via the station bus or by using hard
wired binary inputs/outputs.
The interlocking conditions depend on the circuit configuration and status of the system at any given
time.
The interlocking function consists of software modules located in each control IED. The function is
distributed and not dependent on any central function. Communication between modules in different
bays is performed via the station bus.
The reservation function (see section "Functionality") is used to ensure that HV apparatuses that might
affect the interlock are blocked during the time gap, which arises between position updates. This can
be done by means of the communication system, reserving all HV apparatuses that might influence
the interlocking condition of the intended operation. The reservation is maintained until the operation is
performed.
After the selection and reservation of an apparatus, the function has complete data on the status of all
apparatuses in the switchyard that are affected by the selection. Other operators cannot interfere with
the reserved apparatus or the status of switching devices that may affect it.
The open or closed positions of the HV apparatuses are inputs to software modules distributed in the
control IEDs. Each module contains the interlocking logic for a bay. The interlocking logic in a module
is different, depending on the bay function and the switchyard arrangements, that is, double-breaker
or breaker-and-a-half bays have different modules. Specific interlocking conditions and connections
between standard interlocking modules are performed with an engineering tool. Bay-level interlocking
signals can include the following kind of information:
The interlocking module is connected to the surrounding functions within a bay as shown in figure 452.
Apparatus control
Interlocking
modules
modules in
SCILO SCSWI
other bays SXSWI
Apparatus control
modules
Interlocking SCILO SCSWI SXCBR 152
module
Apparatus control
modules
SCILO SCSWI SXSWI
en04000526_ansi.vsd
ANSI04000526 V1 EN-US
Bays communicate via the station bus and can convey information regarding the following:
• Ungrounded busbars
• Busbars connected together
• Other bays connected to a busbar
• Received data from other bays is valid
Station bus
Disc 189 and 289 closed Disc 189 and 289 closed WA1 ungrounded
WA1 ungrounded
WA1 and WA2 interconn
...
WA1 not grounded WA1 not grounded
WA2 not grounded WA2 not grounded WA1 and WA2 interconn
WA1 and WA2 interconn WA1 and WA2 interconn in other bay
..
WA1
WA2
189 289 189 289 189 289 189G 289G
152
152 152
989 989
en05000494_ansi.vsd
ANSI05000494 V1 EN-US
When invalid data such as intermediate position, loss of a control IED, or input board error are used as
conditions for the interlocking condition in a bay, a release for execution of the function will not be given.
On the local HMI an override function exists, which can be used to bypass the interlocking function in
cases where not all the data required for the condition is valid.
• The interlocking conditions for opening or closing of disconnectors and grounding switches are always
identical.
• Grounding switches on the line feeder end, for example, rapid grounding switches, are normally
interlocked only with reference to the conditions in the bay where they are located, not with reference
to switches on the other side of the line. So a line voltage indication may be included into line
interlocking modules. If there is no line voltage supervision within the bay, then the appropriate inputs
must be set to no voltage, and the operator must consider this when operating.
• Grounding switches can only be operated on isolated sections for example, without load/voltage.
Circuit breaker contacts cannot be used to isolate a section, that is, the status of the circuit breaker is
irrelevant as far as the grounding switch operation is concerned.
• Disconnectors cannot break power current or connect different voltage systems. Disconnectors in
series with a circuit breaker can only be operated if the circuit breaker is open, or if the disconnectors
operate in parallel with other closed connections. Other disconnectors can be operated if one side is
completely isolated, or if the disconnectors operate in parallel to other closed connections, or if they
are grounding on both sides.
• Circuit breaker closing is only interlocked against running disconnectors in its bay or additionally in a
transformer bay against the disconnectors and grounding switch on the other side of the transformer, if
there is no disconnector between CB and transformer.
• Circuit breaker opening is only interlocked in a bus-coupler bay, if a bus bar transfer is in progress.
To make the implementation of the interlocking function easier, a number of standardized and tested
software interlocking modules containing logic for the interlocking conditions are available:
The interlocking conditions can be altered, to meet the customer specific requirements, by adding
configurable logic by means of the graphical configuration tool PCM600. The inputs Qx_EXy on the
interlocking modules are used to add these specific conditions.
The input signals EXDU_xx shall be set to true if there is no transmission error at the transfer of
information from other bays. Required signals with designations ending in TR are intended for transfer to
other bays.
16.3.3.1 Identification
GUID-3EC5D7F1-FDA0-4F0E-9391-08D357689E0C v3
The Logical node for interlocking SCILO(3) function is used to enable a switching operation if the
interlocking conditions permit. SCILO (3) function itself does not provide any interlocking functionality.
The interlocking conditions are generated in separate function blocks containing the interlocking logic.
SCILO (3)
POSOPEN EN_OPEN
POSCLOSE EN_CLOSE
OPEN_EN
CLOSE_EN
ANSI05000359-1-en.vsd
ANSI05000359 V1 EN-US
16.3.3.4 Signals
PID-3487-INPUTSIGNALS v7
PID-3487-OUTPUTSIGNALS v7
The function contains logic to enable the open and close commands respectively if the interlocking
conditions are fulfilled. That means also, if the switch has a defined end position for example, open,
then the appropriate enable signal (in this case EN_OPEN) is false. The enable signals EN_OPEN
and EN_CLOSE can be true at the same time only in the intermediate and bad position state and if
they are enabled by the interlocking function. The position inputs come from the logical nodes Circuit
breaker/Circuit switch (SXCBR/SXSWI) and the enable signals come from the interlocking logic. The
outputs are connected to the logical node Switch controller (SCSWI). One instance per switching device
is needed.
POSOPEN SCILO
POSCLOSE XOR NOT
AND EN_OPEN
OR
AND
OPEN_EN
CLOSE_EN AND EN_CLOSE
OR
AND
en04000525_ansi.vsd
ANSI04000525 V1 EN-US
16.3.4.1 Identification
GUID-F3CBAFDC-3723-429F-9183-45229A6F0A12 v3
The interlocking for busbar grounding switch (BB_ES, 3) function is used for one busbar grounding
switch on any busbar parts according to figure 456.
89G
en04000504.vsd
ANSI04000504 V1 EN-US
BB_ES (3)
89G_OP 89GREL
89G_CL 89GITL
BB_DC_OP BBGSOPTR
VP_BB_DC BBGSCLTR
EXDU_BB
ANSI05000347-2-en.vsd
ANSI05000347 V2 EN-US
BB_ES
VP_BB_DC 89GREL
BB_DC_OP AND 89GITL
EXDU_BB NOT
89G_OP BBGSOPTR
89G_CL BBGSCLTR
en04000546_ansi.vsd
ANSI04000546 V1 EN-US
16.3.4.5 Signals
PID-3494-INPUTSIGNALS v10
16.3.5.1 Identification
GUID-29EF1F25-E10A-4C82-A6B7-FA246D9C6CD2 v3
The interlocking for bus-section breaker (A1A2_BS ,3) function is used for one bus-section circuit
breaker between section 1 and 2 according to figure 458. The function can be used for different busbars,
which includes a bus-section circuit breaker.
152
389G 489G
A1A2_BS
en04000516_ansi.vsd
ANSI04000516 V1 EN-US
A1A2_BS (3)
152_OP 152OPREL
152_CL 152OPITL
189_OP 152CLREL
189_CL 152CLITL
289_OP 189REL
289_CL 189ITL
389G_OP 289REL
389G_CL 289ITL
489G_OP 389GREL
489G_CL 389GITL
S189G_OP 489GREL
S189G_CL 489GITL
S289G_OP S1S2OPTR
S289G_CL S1S2CLTR
BBTR_OP 189OPTR
VP_BBTR 189CLTR
EXDU_12 289OPTR
EXDU_89G 289CLTR
152O_EX1 VPS1S2TR
152O_EX2 VP189TR
152O_EX3 VP289TR
189_EX1
189_EX2
289_EX1
289_EX2
ANSI05000348-2-en.vsd
ANSI05000348 V2 EN-US
A1A2_BS
152_OP
152_CL XOR VP152
189_OP
189_CL XOR VP189
289_OP
289_CL XOR VP289
389G_OP
389G_CL XOR VP389G
489G_OP
489G_CL XOR VP489G
S1189G_OP
S1189G_CL XOR VPS1189G
S2289G_OP
S2289G_CL XOR VPS2289G
VP189
189_OP AND OR 152OPREL
152O_EX1 152OPITL
NOT
VP289
289_OP AND
152O_EX2
VP_BBTR
BBTR_OP AND
EXDU_12
152O_EX3
VP189 152CLREL
VP289 AND 152CLITL
NOT
VP152
VP389G AND OR 189REL
VP489G 189ITL
NOT
VPS1189G
152_OP
389G_OP
489G_OP
S1189G_OP
EXDU_89G
189_EX1
VP389G
VPS1189G AND
389G_CL
S1189G_CL
EXDU_89G
189_EX2
en04000542_ansi.vsd
ANSI04000542 V1 EN-US
VP152
VP389G AND OR 289REL
VP489G 289ITL
NOT
VPS2289G
152_OP
389G_OP
489G_OP
S2289G_OP
EXDU_89G
289_EX1
VP489G
VPS2289G AND
489G_CL
S2289G_CL
EXDU_89G
289_EX2
VP189 389GREL
VP289 AND 389GITL
189_OP NOT
489GREL
289_OP
489GITL
NOT
189_OP 189OPTR
189_CL 189CLTR
VP189 VP189TR
289_OP 289OPTR
289_CL 289CLTR
VP289 VP289TR
189_OP S1S2OPTR
289_OP OR S1S2CLTR
152_OP NOT
VP189 VPS1S2TR
VP289 AND
VP152
en04000543_ansi.vsd
ANSI04000543 V1 EN-US
16.3.5.5 Signals
PID-3498-INPUTSIGNALS v9
16.3.6.1 Identification
GUID-0A0229EB-5ECD-405C-B706-6A54CBBDB49D v3
The interlocking for bus-section disconnector (A1A2_DC, 3) function is used for one bus-section
disconnector between section 1 and 2 according to figure 460. A1A2_DC (3) function can be used
for different busbars, which includes a bus-section disconnector.
52
189G 289G
A1A2_DC en04000492_ansi.vsd
ANSI04000492 V1 EN-US
A1A2_DC (3)
089_OP 089OPREL
089_CL 089OPITL
S189G_OP 089CLREL
S189G_CL 089CLITL
S289G_OP DCOPTR
S289G_CL DCCLTR
S1DC_OP VPDCTR
S2DC_OP
VPS1_DC
VPS2_DC
EXDU_89G
EXDU_BB
089C_EX1
089C_EX2
089O_EX1
089O_EX2
089O_EX3
ANSI05000349-2-en.vsd
ANSI05000349 V2 EN-US
A1A2_DC
89_OP
VPQB VPDCTR
89_CL XOR
DCOPTR
DCCLTR
S1189G_OP
VPS1189G
S1189G_CL XOR
S2289G_OP
VPS2289G
S2289G_CL XOR
VPS1189G
VPS2289G AND OR
VPS1_DC 89OPREL
S1189G_OP NOT
89OPITL
S2289G_OP
S1DC_OP
EXDU_89G
EXDU_BB
QBOP_EX1
VPS1189
VPS2289G AND
VPS2_DC
S1189G_OP
S2289G_OP
S2DC_OP
EXDU_89G
EXDU_BB
QBOP_EX2
VPS1189G
VPS2289G AND
S1189G_CL
S2289G_CL
EXDU_89G
QBOP_EX3
en04000544_ansi.vsd
ANSI04000544 V1 EN-US
IEC04000545 V1 EN-US
16.3.6.5 Signals
PID-3499-INPUTSIGNALS v10
16.3.7.1 Identification
GUID-8149EE0A-E2A4-431C-9D07-D1A0BD296743 v3
The interlocking for bus-coupler bay (ABC_BC, 3) function is used for a bus-coupler bay connected to a
double busbar arrangement according to figure 462. The function can also be used for a single busbar
arrangement with transfer busbar or double busbar arrangement without transfer busbar.
WA1 (A)
WA2 (B)
WA7 (C)
152
289G
en04000514_ansi.vsd
ANSI04000514 V1 EN-US
ABC_BC (3)
152_OP 152OPREL
152_CL 152OPITL
189_OP 152CLREL
189_CL 152CLITL
289_OP 189REL
289_CL 189ITL
789_OP 289REL
789_CL 289ITL
2089_OP 789REL
2089_CL 789ITL
189G_OP 2089REL
189G_CL 2089ITL
289G_OP 189GREL
289G_CL 189GITL
1189G_OP 289GREL
1189G_CL 289GITL
2189G_OP 189OPTR
2189G_CL 189CLTR
7189G_OP 22089OTR
7189G_CL 22089CTR
BBTR_OP 789OPTR
BC_12_CL 789CLTR
VP_BBTR 1289OPTR
VP_BC_12 1289CLTR
EXDU_89G BC12OPTR
EXDU_12 BC12CLTR
EXDU_BC BC17OPTR
152O_EX1 BC17CLTR
152O_EX2 BC27OPTR
152O_EX3 BC27CLTR
189_EX1 VP189TR
189_EX2 V22089TR
189_EX3 VP789TR
289_EX1 VP1289TR
289_EX2 VPBC12TR
289_EX3 VPBC17TR
2089_EX1 VPBC27TR
2089_EX2
789_EX1
789_EX2
ANSI05000350-2-en.vsd
ANSI05000350 V2 EN-US
ABC_BC
152_OP
152_CL XOR VP152
189_OP
189_CL XOR VP189
2089_OP
2089_CL XOR VP2089
789_OP
789_CL XOR VP789
289_OP
289_CL XOR VP289
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
1189G_OP
1189G_CL XOR VP1189G
2189G_OP
2189G_CL XOR VP2189G
7189G_OP
7189G_CL XOR VP7189G
VP189
189_OP AND
152OPREL
OR
152O_EX1 152OPITL
NOT
VP2089
2089_OP AND
152O_EX2
VP_BBTR
BBTR_OP AND
EXDU_12
152O_EX3
VP189 152CLREL
VP289 AND 152CLITL
VP789 NOT
VP2089
en04000533_ansi.vsd
ANSI04000533 V1 EN-US
VP152
VP289 AND OR 189REL
VP189G 189ITL
VP289G NOT
VP1189G
152_OP
289_OP
189G_OP
289G_OP
1189G_OP
EXDU_89G
189_EX1
VP289
VP_BC_12 AND
289_CL
BC_12_CL
EXDU_BC
189_EX2
VP189G
VP1189G AND
189G_CL
1189G_CL
EXDU_89G
189_EX3
en04000534_ansi.vsd
ANSI04000534 V1 EN-US
VP152
VP189 AND OR 289REL
VP189G 289ITL
VP289G NOT
VP2189G
152_OP
189_OP
189G_OP
289G_OP
2189G_OP
EXDU_89G
289_EX1
VP189
VP_BC_12 AND
189_CL
BC_12_CL
EXDU_BC
289_EX2
VP189G
VP2189G AND
189G_CL
2189G_CL
EXDU_89G
289_EX3
en04000535_ansi.vsd
ANSI04000535 V1 EN-US
VP152
VP2089 AND OR 789REL
VP189G 789ITL
VP289G NOT
VP7189G
152_OP
2089_OP
189G_OP
289G_OP
7189G_OP
EXDU_89G
789_EX1
VP289G
VP7189G AND
289G_CL
7189G_CL
EXDU_89G
789_EX2
VP152
VP789 AND OR
2089REL
VP189G 2089ITL
VP289G NOT
VP2189G
152_OP
789_OP
189G_OP
289G_OP
2189G_OP
EXDU_89G
2089_EX1
VP289G
VP2189G AND
289G_CL
2189G_CL
EXDU_89G
2089_EX2
en04000536_ansi.vsd
ANSI04000536 V1 EN-US
VP189 189GREL
VP2089 AND 189GITL
VP789 NOT
289GREL
VP289
189_OP NOT
289GITL
2089_OP
789_OP
289_OP
189_OP 189OPTR
189_CL 189CLTR
VP189 VP189TR
2089_OP 22089OTR
289_OP AND 22089CTR
VP2089 NOT
V22089TR
VP289 AND
789_OP 789OPTR
789_CL 789CLTR
VP789 VP789TR
189_OP 1289OPTR
289_OP OR 1289CLTR
VP189 NOT
VP1289TR
VP289 AND
152_OP BC12OPTR
189_OP OR BC12CLTR
2089_OP NOT
VP152
VPBC12TR
VP189 AND
VP2089
152_OP BC17OPTR
189_OP OR BC17CLTR
789_OP NOT
VP152
VPBC17TR
VP189 AND
VP789
152_OP BC27OPTR
289_OP OR BC27CLTR
789_OP NOT
VP152
VPBC27TR
VP289 AND
VP789
en04000537_ansi.vsd
ANSI04000537 V1 EN-US
16.3.7.5 Signals
PID-3500-INPUTSIGNALS v9
16.3.8.1 Identification
GUID-03F1A3BB-4A1E-49E8-88C6-10B3876F64DA v4
WA1 (A)
WA2 (B)
189 289
189G 189G
152 152
289G 289G
689 689
389G 389G
BH_LINE_A BH_LINE_B
6189 6289
152
989 989
189G 289G
989G 989G
BH_CONN
en04000513_ansi.vsd
ANSI04000513 V1 EN-US
M13574-3 v6
BH_LINE_A (3)
152_OP 152CLREL
152_CL 152CLITL
689_OP 689REL
689_CL 689ITL
189_OP 189REL
189_CL 189ITL
189G_OP 189GREL
189G_CL 189GITL
289G_OP 289GREL
289G_CL 289GITL
389G_OP 389GREL
389G_CL 389GITL
989_OP 989REL
989_CL 989ITL
989G_OP 989GREL
989G_CL 989GITL
C152_OP 189OPTR
C152_CL 189CLTR
C6189_OP VP189TR
C6189_CL
C189G_OP
C189G_CL
C289G_OP
C289G_CL
1189G_OP
1189G_CL
VOLT_OFF
VOLT_ON
EXDU_89G
689_EX1
689_EX2
189_EX1
189_EX2
989_EX1
989_EX2
989_EX3
989_EX4
989_EX5
989_EX6
989_EX7
ANSI05000352-2-en.vsd
ANSI05000352 V2 EN-US
M13578-3 v6
BH_LINE_B (3)
152_OP 152CLREL
152_CL 152CLITL
689_OP 689REL
689_CL 689ITL
289_OP 289REL
289_CL 289ITL
189G_OP 189GREL
189G_CL 189GITL
289G_OP 289GREL
289G_CL 289GITL
389G_OP 389GREL
389G_CL 389GITL
989_OP 989REL
989_CL 989ITL
989G_OP 989GREL
989G_CL 989GITL
C152_OP 289OPTR
C152_CL 289CLTR
C6289_OP VP289TR
C6289_CL
C189G_OP
C189G_CL
C289G_OP
C289G_CL
2189G_OP
2189G_CL
VOLT_OFF
VOLT_ON
EXDU_89G
689_EX1
689_EX2
289_EX1
289_EX2
989_EX1
989_EX2
989_EX3
989_EX4
989_EX5
989_EX6
989_EX7
ANSI05000353-2-en.vsd
ANSI05000353 V2 EN-US
BH_CONN (3)
152_OP 152CLREL
152_CL 152CLITL
6189_OP 6189REL
6189_CL 6189ITL
6289_OP 6289REL
6289_CL 6289ITL
189G_OP 189GREL
189G_CL 189GITL
289G_OP 289GREL
289G_CL 289GITL
1389G_OP
1389G_CL
2389G_OP
2389G_CL
6189_EX1
6189_EX2
6289_EX1
6289_EX2
ANSI05000351-2-en.vsd
ANSI05000351 V2 EN-US
M13577-1 v5
BH_CONN
152_OP
152_CL XOR VP152
6189_OP
6189_CL XOR VP6189
6289_OP
6289_CL XOR VP6289
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
1389G_OP
1389G_CL XOR VP1389G
2389G_OP
2389G_CL XOR VP2389G
VP6189 152CLREL
VP6289 AND 152CLITL
NOT
VP152
VP189G AND OR 6189REL
VP289G 61891ITL
NOT
VP1389G
152_OP
189G_OP
289G_OP
1389G_OP
6189_EX1
VP189G
VP1389G AND
189G_CL
1389G_CL
6189_EX2
VP152
VP189G AND OR 6289REL
VP289G 6289ITL
NOT
VP2389G
152_OP
189G_OP
289G_OP
2389G_OP
6289_EX1
VP289G
VP2389G AND
289G_CL
2389G_CL
6289_EX2
VP6189 189GREL
VP6289 AND NOT 189GITL
6189_OP 289GREL
6289_OP NOT
289GITL
en04000560_ansi.vsd
ANSI04000560 V1 EN-US
BH_LINE_A
152_OP
152_CL XOR VP152
189_OP
189_CL XOR VP189
689_OP
689_CL XOR VP689
989G_OP
989G_CL XOR VP989G
989_OP
989_CL XOR VP989
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
389G_OP
389G_CL XOR VP389G
C152_OP
C152_CL XOR VPC152
C189G_OP
C189G_CL XOR VPC189G
C289G_OP
C289G_CL XOR VPC289G
C6189_OP
C6189_CL XOR VPC6189
1189G_OP
1189G_CL XOR VP1189G
VOLT_OFF
VOLT_ON XOR VPVOLT
VP189 152CLREL
VP689 152CLITL
AND NOT
VP989
VP152
VP189G 689REL
AND OR
VP289G 689ITL
NOT
VP389G
152_OP
189G_OP
289G_OP
389G_OP
689_EX1
VP289G
VP389G
AND
289G_CL
389G_CL
689_EX2
en04000554_ansi.vsd
ANSI04000554 V1 EN-US
VP152
VP189G AND OR 189REL
VP289G 189ITL
NOT
VP1189G
152_OP
189G_OP
289G_OP
1189G_OP
EXDU_89G
189_EX1
VP189G
VP1189G AND
189G_CL
1189G_CL
EXDU_89G
189_EX2
VP189 189GREL
VP689 AND 189GITL
NOT
189_OP 289GREL
689_OP 289GITL
VP689 NOT
VP989 AND 389GREL
VPC6189 389GITL
NOT
689_OP
989_OP
C6189_OP
VP152 989REL
VP689 AND OR 989ITL
NOT
VP989G
VP189G
VP289G
VP389G
VPC152
VPC6189
VPC189G
VPC289G
989_EX1
689_OP
989_EX2 OR
152_OP
189G_OP AND
289G_OP
989_EX3
en04000555_ansi.vsd
ANSI04000555 V1 EN-US
C6189_OP
989_EX4
OR AND OR
C152_OP
C189G_OP AND
C289G_OP
989_EX5
989G_OP
389G_OP
989_EX6
VP989G
VP389G AND
989G_CL
389G_CL
989_EX7
VP989 989GREL
VPVOLT AND 989GITL
NOT
989_OP
VOLT_OFF
189_OP 189OPTR
189_CL 189CLTR
VP189 VP189TR
en04000556_ansi.vsd
ANSI04000556 V1 EN-US
BH_LINE_B
152_OP
152_CL XOR VP152
289_OP
289_CL XOR VP289
689_OP
689_CL XOR VP689
989G_OP
989G_CL XOR VP989G
989_OP
989_CL XOR VP989
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
389G_OP
389G_CL XOR VP389G
C152_OP
C152_CL XOR VPC152
C189G_OP
C189G_CL XOR VPC189G
C289G_OP
C289G_CL XOR VPC289G
C6289_OP
C6289_CL XOR VPC6289
2189G_OP
2189G_CL XOR VP2189G
VOLT_OFF
VOLT_ON XOR VPVOLT
VP289 152CLREL
VP689 AND 152CLITL
NOT
VP989
VP152
VP189G AND OR 689REL
VP289G 689ITL
VP389G NOT
152_OP
189G_OP
289G_OP
389G_OP
689_EX1
VP289G
VP389G AND
289G_CL
389G_CL
689_EX2
en04000557_ansi.vsd
ANSI04000557 V1 EN-US
VP152
VP189G 289REL
VP289G AND OR
NOT 289ITL
VP2189G
152_OP
189G_OP
289G_OP
2189G_OP
EXDU_89G
289_EX1
VP189G
VP2189G AND
189G_CL
2189G_CL
EXDU_89G
289_EX2
VP289 189GREL
VP689 189GITL
AND NOT
289_OP 289GREL
689_OP 289GITL
VP689 NOT
VP989 389GREL
VPC6289 AND
NOT 389GITL
689_OP
989_OP
C6289_OP
VP152 989REL
VP689
AND OR 989ITL
VP989G NOT
VP189G
VP289G
VP389G
VPC152
VPC6289
VPC189G
VPC289G
989_EX1
689_OP
989_EX2
OR
152_OP
189G_OP
AND
289G_OP
989_EX3
en04000558_ansi.vsd
ANSI04000558 V1 EN-US
C6289_OP
989_EX4
OR AND OR
C152_OP
C189G_OP
AND
C289G_OP
989_EX5
989G_OP
389G_OP
989_EX6
VP989G
VP389G AND
989G_CL
389G_CL
989_EX7
VP989 989GREL
VPVOLT AND NOT 989GITL
989_OP
VOLT_OFF
289_OP 289OPTR
289_CL 289CLTR
VP289 VP289TR
en04000559_ansi.vsd
ANSI04000559 V1 EN-US
16.3.8.5 Signals
PID-3593-INPUTSIGNALS v9
16.3.9.1 Identification
GUID-D6D10255-2818-44E4-A44E-DF623161C486 v3
The interlocking for a double busbar double circuit breaker bay including DB_BUS_A (3), DB_BUS_B (3)
and DB_LINE (3) functions are used for a line connected to a double busbar arrangement according to
figure 468.
WA1 (A)
WA2 (B)
189 289
189G 489G
289G 589G
6189 6289
389G
DB_LINE
989
989G
en04000518_ansi.vsd
ANSI04000518 V1 EN-US
Three types of interlocking modules per double circuit breaker bay are defined. DB_BUS_A (3) handles
the circuit breaker QA1 that is connected to busbar WA1 and the disconnectors and grounding switches
of this section. DB_BUS_B (3) handles the circuit breaker QA2 that is connected to busbar WA2 and the
disconnectors and grounding switches of this section.
M15105-1 v4
DB_BUS_A
152_OP
152_CL XOR VP152
6189_OP
6189_CL XOR VP6189
189_OP
189_CL XOR VP189
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
389G_OP
389G_CL XOR VP389G
1189G_OP
1189G_CL XOR VP1189G
VP6189 152CLREL
VP189 AND 152CLITL
NOT
VP152
VP189G AND OR 6189REL
VP289G 6189ITL
NOT
VP389G
152_OP
189G_OP
289G_OP
389G_OP
6189_EX1
VP289G
VP389G AND
289G_CL
389G_CL
6189_EX2
VP152
VP189G AND OR 189REL
VP289G 189ITL
NOT
VP1189G
152_OP
189G_OP
289G_OP
1189G_OP
EXDU_89G
189_EX1
VP189G
VP1189G AND
189G_CL
1189G_CL
EXDU_89G
189_EX2
en04000547_ansi.vsd
ANSI04000547 V1 EN-US
VP6189 189GREL
VP189 AND NOT 189GITL
6189_OP 289GREL
189_OP NOT
289GITL
189_OP 189OPTR
189_CL 189CLTR
VP189 VP189TR
en04000548_ansi.vsd
ANSI04000548 V1 EN-US
DB_BUS_B
252_OP
252_CL XOR VP252
6289_OP
6289_CL XOR VP6289
289_OP
289_CL XOR VP289
489G_OP
489G_CL XOR VP489G
589G_OP
589G_CL XOR VP589G
389G_OP
389G_CL XOR VP389G
2189G_OP
2189G_CL XOR VP2189G
VP6289 252CLREL
VP289 AND 252CLITL
NOT
VP252
VP489G AND OR 6289REL
VP589G 6289ITL
NOT
VP389G
252_OP
489G_OP
589G_OP
389G_OP
6289_EX1
VP589G
VP389G AND
589G_CL
389G_CL
6289_EX2
VP252
VP489G AND OR 289REL
VP589G 289ITL
NOT
VP2189G
252_OP
489G_OP
589G_OP
2189G_OP
EXDU_89G
289_EX1
VP489G
VP2189G AND
489G_CL
2189G_CL
EXDU_89G
289_EX2
en04000552_ansi.vsd
ANSI04000552 V1 EN-US
VP6289 489GREL
VP289 AND NOT 489GITL
6289_OP 589GREL
289_OP 589GITL
NOT
289_OP 289OPTR
289_CL 289CLTR
VP289 VP289TR
en04000553_ansi.vsd
ANSI04000553 V1 EN-US
DB_LINE
152_OP
152_CL XOR VP152
252_OP
252_CL XOR VP252
6189_OP
6189_CL XOR VP6189
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
6289_OP
6289_CL XOR VP6289
489G_OP
489G_CL XOR VP489G
589G_OP
589G_CL XOR VP589G
989_OP
989_CL XOR VP989
389G_OP
389G_CL XOR VP389G
989G_OP
989G_CL XOR VP989G
VOLT_OFF
VOLT_ON XOR VPVOLT
VP152
VP252 AND OR 989REL
VP189G 989ITL
NOT
VP289G
VP389G
VP489G
VP589G
VP989G
152_OP
252_OP
189G_OP
289G_OP
389G_OP
489G_OP
589G_OP
989G_OP
989_EX1
AND
en04000549_ansi.vsd
ANSI04000549 V1 EN-US
VP152
VP189G AND OR
VP289G
VP389G
VP989G
VP6289
152_OP
189G_OP
289G_OP
389G_OP
989G_OP
6289_OP
989_EX2
VP252
VP6189 AND
VP389G
VP489G
VP589G
VP989G
252_OP
6189_OP
389G_OP
489G_OP
589G_OP
989G_OP
989_EX3
VP389G
VP989G AND
VP6189
VP6289
389G_OP
989G_OP
6189_OP
6289_OP
989_EX4
VP389G
VP989G AND
389G_CL
989G_CL
989_EX5
en04000550_ansi.vsd
ANSI04000550 V1 EN-US
VP6189
VP6289 AND 389GREL
VP989 389GITL
NOT
6189_OP
6289_OP
989_OP
VP989
VPVOLT AND 989GREL
989_OP 989GITL
NOT
VOLT_OFF
en04000551_ansi.vsd
ANSI04000551 V1 EN-US
M13591-3 v6
DB_BUS_A (3)
152_OP 152CLREL
152_CL 152CLITL
189_OP 6189REL
189_CL 6189ITL
6189_OP 189REL
6189_CL 189ITL
189G_OP 189GREL
189G_CL 189GITL
289G_OP 289GREL
289G_CL 289GITL
389G_OP 189OPTR
389G_CL 189CLTR
1189G_OP VP189TR
1189G_CL
EXDU_89G
6189_EX1
6189_EX2
189_EX1
189_EX2
ANSI05000354-2-en.vsd
ANSI05000354 V2 EN-US
DB_LINE (3)
152_OP 989REL
152_CL 989ITL
252_OP 389GREL
252_CL 389GITL
6189_OP 989GREL
6189_CL 989GITL
189G_OP
189G_CL
289G_OP
289G_CL
6289_OP
6289_CL
489G_OP
489G_CL
589G_OP
589G_CL
989_OP
989_CL
389G_OP
389G_CL
989G_OP
989G_CL
VOLT_OFF
VOLT_ON
989_EX1
989_EX2
989_EX3
989_EX4
989_EX5
ANSI05000356-2-en.vsd
ANSI05000356 V2 EN-US
M13596-3 v6
DB_BUS_B (3)
252_OP 252CLREL
252_CL 252CLITL
289_OP 6289REL
289_CL 6289ITL
6289_OP 289REL
6289_CL 289ITL
489G_OP 489GREL
489G_CL 489GITL
589G_OP 589GREL
589G_CL 589GITL
389G_OP 289OPTR
389G_CL 289CLTR
2189G_OP VP289TR
2189G_CL
EXDU_89G
6289_EX1
6289_EX2
289_EX1
289_EX2
ANSI05000355-2-en.vsd
ANSI05000355 V2 EN-US
16.3.9.5 Signals
PID-3598-INPUTSIGNALS v9
PID-3508-INPUTSIGNALS v10
16.3.10.1 Identification
GUID-BEA26EA4-F402-4385-9238-1361E862D987 v3
The interlocking for line bay (ABC_LINE, 3) function is used for a line connected to a double busbar
arrangement with a transfer busbar according to figure 472. The function can also be used for a
double busbar arrangement without transfer busbar or a single busbar arrangement with/without transfer
busbar.
WA1 (A)
WA2 (B)
WA7 (C)
152
289G
989
989G
en04000478_ansi.vsd
ANSI04000478 V1 EN-US
ABC_LINE (3)
152_OP 152CLREL
152_CL 152CLITL
989_OP 989REL
989_CL 989ITL
189_OP 189REL
189_CL 189ITL
289_OP 289REL
289_CL 289ITL
789_OP 789REL
789_CL 789ITL
189G_OP 189GREL
189G_CL 189GITL
289G_OP 289GREL
289G_CL 289GITL
989G_OP 989GREL
989G_CL 989GITL
1189G_OP 189OPTR
1189G_CL 189CLTR
2189G_OP 289OPTR
2189G_CL 289CLTR
7189G_OP 789OPTR
7189G_CL 789CLTR
BB7_D_OP 1289OPTR
BC_12_CL 1289CLTR
BC_17_OP VP189TR
BC_17_CL VP289TR
BC_27_OP VP789TR
BC_27_CL VP1289TR
VOLT_OFF
VOLT_ON
VP_BB7_D
VP_BC_12
VP_BC_17
VP_BC_27
EXDU_89G
EXDU_BPB
EXDU_BC
989_EX1
989_EX2
189_EX1
189_EX2
189_EX3
289_EX1
289_EX2
289_EX3
789_EX1
789_EX2
789_EX3
789_EX4
ANSI05000357-2-en.vsd
ANSI05000357 V2 EN-US
ABC_LINE
152_OP
152_CL XOR VP152
989_OP
989_CL XOR VP989
189_OP 152CLREL
189_CL XOR VP189 AND NOT
152CLITL
289_OP
289_CL XOR VP289
789_OP
789_CL XOR VP789
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
989G_OP
989G_CL XOR VP989G
1189G_OP
1189G_CL XOR VP1189G
2189G_OP
2189G_CL XOR VP2189G
7189G_OP
7189G_CL XOR VP7189G
VOLT_OFF
VOLT_ON XOR VPVOLT
VP152
VP189G AND OR 989REL
VP289G 989ITL
NOT
VP989G
152_OP
189G_OP
289G_OP
989G_OP
989_EX1
VP289G
VP989G AND
289G_CL
989G_CL
989_EX2
en04000527_ansi.vsd
ANSI04000527 V1 EN-US
VP152 189REL
AND OR
VP289
VP189G 189ITL
NOT
VP289G
VP1189G
152_OP
289_OP
189G_OP
289G_OP
1189G_OP
EXDU_89G
189_EX1
VP289 AND
VP_BC_12
289_CL
BC_12_CL
EXDU_BC
189_EX2
VP189G
AND
VP1189G
189G_CL
1189G_CL
EXDU_89G
189EX3
en04000528_ansi.vsd
ANSI04000528 V1 EN-US
VP152 289REL
AND OR
VP189
VP189G 289ITL
NOT
VP289G
VP2189G
152_OP
189_OP
189G_OP
289G_OP
2189G_OP
EXDU_89G
289_EX1
VP189 AND
VP_BC_12
QB1_CL
BC_12_CL
EXDU_BC
289_EX2
VP189G
AND
VP2189G
189G_CL
2189G_CL
EXDU_89G
289_EX3
en04000529_ansi.vsd
ANSI04000529 V1 EN-US
VP989G 789REL
AND OR
VP7189G
VP_BB7_D 789ITL
NOT
VP_BC_17
VP_BC_27
989G_OP
7189G_OP
EXDU_89G
BB7_D_OP
EXDU_BPB
BC_17_OP
BC_27_OP
EXDU_BC
789_EX1
VP152
VP189 AND
VP989G
VP989
VP7189G
VP_BB7_D
VP_BC_17
152_CL
189_CL
989G_OP
989_CL
7189G_OP
EXDU_89G
BB7_D_OP
EXDU_BPB
BC_17_CL
EXDU_BC
789_EX2
en04000530_ansi.vsd
ANSI04000530 V1 EN-US
VP152
VP289
AND OR
VP989G
VP989
VP7189G
VP_BB7_D
VP_BC_27
152_CL
289_CL
989G_OP
989_CL
7189G_OP
EXDU_89G
BB7_D_OP
EXDU_BPB
BC_27_CL
EXDU_BC
789_EX3
VP989G
VP7189G AND
989G_CL
7189G_CL
EXDU_89G
789_EX4
VP189 189GREL
VP289 189GITL
AND NOT
VP989
289GREL
189_OP
289_OP 289GITL
NOT
989_OP
VP789
VP989 989GREL
AND
VPVOLT 989GITL
789_OP NOT
989_OP
VOLT_OFF
en04000531_ansi.vsd
ANSI04000531 V1 EN-US
189_OP 189OPTR
189_CL 189CLTR
VP189 VP189TR
289_OP 289OPTR
289_CL 289CLTR
VP289 VP289TR
789_OP 789OPTR
789_CL 789CLTR
VP789 VP789TR
189_OP 1289OPTR
289_OP OR 1289CLTR
VP189 NOT
VP1289TR
VP289 AND
en04000532_ansi.vsd
ANSI04000532 V1 EN-US
16.3.10.5 Signals
PID-3509-INPUTSIGNALS v10
16.3.11.1 Identification
GUID-AD839CAA-531B-43BC-B508-39AED3D0A97D v3
The interlocking for transformer bay (AB_TRAFO, 3) function is used for a transformer bay connected
to a double busbar arrangement according to figure 474. The function is used when there is
no disconnector between circuit breaker and transformer. Otherwise, the interlocking for line bay
(ABC_LINE, 3) function can be used. This function can also be used in single busbar arrangements.
WA1 (A)
WA2 (B)
189 289
189G
152 AB_TRAFO
289G
389G
389 489
en04000515_ansi.vsd
ANSI04000515 V1 EN-US
AB_TRAFO (3)
152_OP 152CLREL
152_CL 152CLITL
189_OP 189REL
189_CL 189ITL
289_OP 289REL
289_CL 289ITL
189G_OP 189GREL
189G_CL 189GITL
289G_OP 289GREL
289G_CL 289GITL
389_OP 189OPTR
389_CL 189CLTR
489_OP 289OPTR
489_CL 289CLTR
389G_OP 1289OPTR
389G_CL 1289CLTR
1189G_OP VP189TR
1189G_CL VP289TR
2189G_OP VP1289TR
2189G_CL
BC_12_CL
VP_BC_12
EXDU_89G
EXDU_BC
152_EX1
152_EX2
152_EX3
189_EX1
189_EX2
189_EX3
289_EX1
289_EX2
289_EX3
ANSI05000358-2-en.vsd
ANSI05000358 V2 EN-US
AB_TRAFO
152_OP
152_CL XOR VP152
189_OP
189_CL XOR VP189
289_OP
289_CL XOR VP289
189G_OP
189G_CL XOR VP189G
289G_OP
289G_CL XOR VP289G
389_OP
389_CL XOR VP389
489_OP
489_CL XOR VP489
389G_OP
389G_CL XOR VP389G
1189G_OP
1189G_CL XOR VP1189G
2189G_OP
2189G_CL XOR VP2189G
VP189 152CLREL
VP289 AND 152CLITL
VP189G NOT
VP289G
VP389
VP489
VP389G
152_EX2
389G_OP
152_EX3 OR
189G_CL
289G_CL AND
389G_CL
152_EX1
en04000538_ansi.vsd
ANSI04000538 V1 EN-US
VP152
VP289 AND OR 189REL
VP189G
189ITL
VP289G NOT
VP389G
VP1189G
152_OP
289_OP
189G_OP
289G_OP
389G_OP
1189G_OP
EXDU_89G
189_EX1
VP289
VP389G AND
VP_BC_12
289_CL
389G_OP
BC_12_CL
EXDU_BC
189_EX2
VP189G
VP289G AND
VP389G
VP1189G
189G_CL
289G_CL
389G_CL
1189G_CL
EXDU_89G
189_EX3
en04000539_ansi.vsd
ANSI04000539 V1 EN-US
VP152
VP189 252REL
AND OR
VP189G 252ITL
VP289G NOT
VP389G
VP2189G
152_OP
189_OP
189G_OP
289G_OP
389G_OP
2189G_OP
EXDU_89G
289_EX1
VP189
VP389G
AND
VP_BC_12
189_CL
389G_OP
BC_12_CL
EXDU_BC
289_EX2
VP189G
VP289G
AND
VP389G
VP2189G
189G_CL
289G_CL
389G_CL
2189G_CL
EXDU_89G
289_EX3
en04000540_ansi.vsd
ANSI04000540 V1 EN-US
VP189 189GREL
VP289 AND 189GITL
NOT
VP389 289GREL
VP489
189_OP 289GITL
NOT
289_OP
389_OP
489_OP
189_OP 189OPTR
189_CL 189CLTR
VP189 VP189TR
289_OP 289OPTR
289_CL 289CLTR
VP289 VP289TR
189_OP 1289OPTR
289_OP OR 1289CLTR
NOT
VP189 VP1289TR
VP289 AND
en04000541_ansi.vsd
ANSI04000541 V1 EN-US
16.3.11.5 Signals
PID-3510-INPUTSIGNALS v10
16.3.12.1 Identification
GUID-3C4B9379-C861-406C-9295-0309014D548E v3
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Position evaluation POS_EVAL - -
Position evaluation (POS_EVAL) function converts the input position data signal POSITION, consisting
of value, time and signal status, to binary signals OPENPOS or CLOSEPOS.
The output signals are used by other functions in the interlocking scheme.
POS_EVAL
POSITION OPENPOS
CLOSEPOS
IEC09000079_1_en.vsd
IEC09000079 V1 EN-US
POS_EVAL
Position including quality POSITION OPENPOS
Open/close position of
CLOSEPOS switch device
IEC08000469-1-en.vsd
IEC08000469-1-EN V1 EN-US
Only the value, open/close, and status is used in this function. Time information is not used.
16.3.12.5 Signals
PID-3555-INPUTSIGNALS v6
The apparatus control functions are used for control and supervision of circuit breakers, disconnectors
and grounding switches within a bay. Permission to trip is given after evaluation of conditions from other
functions such as interlocking, synchronism check, operator place selection and external or internal
blockings.
Normal security means that only the command is evaluated and the resulting position is not supervised.
Enhanced security means that the command is evaluated with an additional supervision of the status
value of the control object. The command sequence with enhanced security is always terminated by a
CommandTermination service primitive and an AddCause telling if the command was successful or if
something went wrong.
Control operation can be performed from the local HMI with authority control if so defined.
A bay can handle, for example a power line, a transformer, a reactor, or a capacitor bank. The different
primary apparatuses within the bay can be controlled via the apparatus control functions directly by the
operator or indirectly by automatic sequences.
Because a primary apparatus can be allocated to many functions within a Substation Automation
system, the object-oriented approach with a function block that handles the interaction and status
of each process object ensures consistency in the process information used by higher-level control
functions.
Primary apparatuses such as breakers and disconnectors are controlled and supervised by one function
block (SCSWI) each. Because the number and type of signals used for the control of a breaker or a
disconnector are almost the same, the same function block type is used to handle these two types of
apparatuses.
The SCSWI function block is connected either to an SXCBR function block (for circuit breakers) or
to an SXSWI function block (for disconnectors and grounding switches). The physical process in the
switchyard is connected to these two function blocks via binary inputs and outputs.
Four types of function blocks are available to cover most of the control and supervision within the
bay. These function blocks are interconnected to form a control function reflecting the switchyard
configuration. The total number used depends on the switchyard configuration. These types are:
The functions Local Remote (LOCREM) and Local Remote Control (LOCREMCTRL), to handle the
local/remote switch. The functions Bay reserve (QCRSV) and Reservation input (RESIN), for the
reservation function, also belong to the apparatus control function.
The principles of operation, function blocks, input and output signals and setting parameters for all these
functions are described below.
Depending on the error that occurs during the command sequence the error signal will be set with a
value. Table 518 describes the cause values given on local HMI. The translation to AddCause values
specified in IEC 61850-8-1 is shown in Table 519. For IEC 61850-8-1 edition 2 only addcauses defined
in the standard are used, for edition 1 also a number of vendor specific causes are used. The values
are available in the command response to commands from IE C61850-8-1 clients. An output L_CAUSE
on the function block for Switch controller (SCSWI), Circuit breaker (SXCBR) and Circuit switch (SXSWI)
indicates the value of the cause during the latest command if the function specific command evaluation
has been started. The causes that are not always reflected on the output L_CAUSE, with description of
the typical reason are listed in table 520.
Table 519: Translation of cause values for IEC 61850 edition 2 and edition 1
The Bay control (QCBAY) function is used together with Local remote and local remote control functions
to handle the selection of the operator place per bay. QCBAY also provides blocking functions that can
be distributed to different apparatuses within the bay.
QCBAY
LR_OFF PSTO
LR_LOC UPD_BLKD
LR_REM CMD_BLKD
LR_VALID LOC
BL_UPD STA
BL_CMD REM
IEC10000048 V4 EN-US
16.4.5.3 Signals
PID-4086-INPUTSIGNALS v9
PID-4086-OUTPUTSIGNALS v9
16.4.5.4 Settings
PID-4086-SETTINGS v9
The local panel switch is a switch that defines the operator place selection. The switch connected to
this function can have three positions (remote/local/off). The positions are here defined so that remote
means that operation is allowed from station and/or remote level and local means that operation is
allowed from the IED level. The local/remote switch is also on the control/protection IED itself, which
means that the position of the switch and its validity information are connected internally, not via I/O
boards. When the switch is mounted separately from the IED the signals are connected to the function
via I/O boards.
When the local panel switch (or LHMI selection, depending on the set source to select this) is in Off
position, all commands from remote and local level will be ignored. If the position for the local/remote
switch is not valid the PSTO output will always be set to faulty state (3), which means no possibility to
operate.
To adapt the signals from the local HMI or from an external local/remote switch, the function blocks
LOCREM and LOCREMCTRL are needed and connected to QCBAY.
The actual state of the operator place is presented by the value of the Permitted Source To Operate,
PSTO signal. The PSTO value is evaluated from the local/remote switch position according to Table 524.
In addition, there are two settings and one command that affect the value of the PSTO signal.
When the external switch is in Off position, or invalid position, the output always shows the actual state
of the switch (0 for Off and 3 for Invalid). In these cases, it is not possible to control anything, and the
setting AllPSTOValid has no effect on the PSTO output.
If the setting AllPSTOValid is set to No Priority and the LR-switch position is in Local or Remote state,
the PSTO output is set to 5 (all), that is, it is permitted to operate from local, station and remote level
without any priority.
If the setting RemoteIncStation is set to Yes and the LR-switch position is in Remote state, the PSTO
output is set to 2 (Station or Remote), that is, it is permitted to operate from both station and remote level
without any priority.
If the LR-switch position is in Remote state, and AllPSTOValid is set to Priority and RemoteIncStation is
set to No, the switching between station and remote level control is done through the command LocSta.
The command is accessible only through the IEC 61850 Edition 2 protocol.
Table 524: PSTO values for different Local panel switch positions
Local panel switch AllPSTOV RemoteIn LocSta.Ct PSTO LED indications on Possible locations
positions alid cStation lVal value LHMI that shall be able to
(setting) (setting) (comman operate
d)
0 = Off - - - 0 Remote and Local Off Not possible to
operate
1 = Local Priority - - 1 Remote Off, Local Panel
Local On
1 = Local No priority - - 5 Remote and Local On Local, Station or
Remote level without
any priority
2 = Remote Priority No TRUE 6 Remote On, Station level
Local Off
2 = Remote Priority No FALSE 7 Remote On, Remote level
Local Off
2 = Remote Priority Yes - 2 Remote On, Station or Remote
Local Off level
2 = Remote No priority - - 5 Remote and Local On Local, Station or
Remote level without
any priority
3 = Faulty - - - 3 Remote and Local Not possible to
Flashing operate
Blockings M13446-50 v6
The blocking states for position indications and commands are intended to provide the possibility for the
user to make common blockings for the functions configured within a complete bay.
The blocking facilities provided by the bay control function are the following:
• Blocking of position indications, BL_UPD. This input will block all inputs related to apparatus positions
for all configured functions within the bay.
• Blocking of commands, BL_CMD. This input will block all commands for all configured functions within
the bay.
The switching of the Local/Remote switch requires at least system operator level. The password will be
requested at an attempt to operate if authority levels have been defined in the IED, otherwise the default
authority level can handle the control without LogOn. The users and passwords are defined with the IED
Users tool in PCM600.
M17086-3 v12
The signals from the local HMI or from an external local/remote switch are connected via the function
blocks local remote (LOCREM) and local remote control (LOCREMCTRL) to the Bay control (QCBAY)
function block. The parameter ControlMode in function block LOCREM is set to choose if the switch
signals are coming from the local HMI or from an external hardware switch connected via binary inputs.
LOCREM
CTRLOFF OFF
LOCCTRL LOCAL
REMCTRL REMOTE
LHMICTRL VALID
IEC05000360 V4 EN-US
LOCREMCTRL
^PSTO1 HMICTR1
^PSTO2 HMICTR2
^PSTO3 HMICTR3
^PSTO4 HMICTR4
^PSTO5 HMICTR5
^PSTO6 HMICTR6
^PSTO7 HMICTR7
^PSTO8 HMICTR8
^PSTO9 HMICTR9
^PSTO10 HMICTR10
^PSTO11 HMICTR11
^PSTO12 HMICTR12
IEC05000361 V4 EN-US
16.4.6.2 Signals
PID-3944-INPUTSIGNALS v8
PID-3943-INPUTSIGNALS v6
16.4.6.3 Settings
PID-3944-SETTINGS v8
The function block Local remote (LOCREM) handles the signals coming from the local/remote switch.
The connections are seen in Figure 480, where the inputs on function block LOCREM are connected
to binary inputs if an external switch is used. When the local HMI is used, the inputs are not used.
The switching between external and local HMI source is done through the parameter ControlMode. The
outputs from the LOCREM function block control the output PSTO (Permitted Source To Operate) on
Bay control (QCBAY).
LOCREM QCBAY
CTRLOFF OFF LR_ OFF PSTO
LOCCTRL LOCAL LR_ LOC UPD_ BLKD
REMCTRL REMOTE LR_ REM CMD_ BLKD
LHMICTRL VALID LR_ VALID LOC
BL_ UPD STA
BL_ CMD REM
LOCREM QCBAY
CTRLOFF OFF LR_ OFF PSTO
LOCCTRL LOCAL LR_ LOC UPD_ BLKD
REMCTRL REMOTE LR_ REM CMD_ BLKD
LHMICTRL VALID LR_ VALID LOC
BL_ UPD STA
BL_ CMD REM
LOCREMCTRL
PSTO1 HMICTR1
PSTO2 HMICTR2
PSTO3 HMICTR3
PSTO4 HMICTR4
PSTO5 HMICTR5
PSTO6 HMICTR6
PSTO7 HMICTR7
PSTO8 HMICTR8
PSTO9 HMICTR9
PSTO 10 HMICTR 10
PSTO 11 HMICTR 11
PSTO 12 HMICTR 12
IEC10000052 V4 EN-US
Figure 480: Configuration for the local/remote handling for a local HMI with two bays and two screen pages
If the IED contains control functions for several bays, the local/remote position can be different for the
included bays. When the local HMI is used the position of the local/remote switch can be different
depending on which single line diagram screen page that is presented on the local HMI. The function
block Local remote control (LOCREMCTRL) controls the presentation of the LEDs for the local/remote
position to applicable bay and screen page.
The switching of the local/remote switch requires at least system operator level. The password will be
requested at an attempt to operate if authority levels have been defined in the IED. Otherwise the default
authority level, SuperUser, can handle the control without LogOn. The users and passwords are defined
with the IED Users tool in PCM600.
The Switch controller (SCSWI) initializes and supervises all functions to properly select and operate
switching primary apparatuses. The Switch controller may handle and operate on one multi-phase
device or up to three one-phase devices.
SCSWI
BLOCK EXE_OP
PSTO EXE_CL
L_SEL SEL_OP
L_OPEN SEL_CL
L_CLOSE SELECTED
AU_OPEN RES_RQ
AU_CLOSE RES_RQ_OP
BL_CMD RES_RQ_CL
RES_GRT START_SY
RES_EXT CANC_SY
SY_INPRO POSITION
SYNC_OK OPENPOS
EN_OPEN CLOSEPOS
EN_CLOSE POLEDISC
XPOSL1* POS_INTR
XPOSL2* CMD_BLK
XPOSL3* L_CAUSE
XEXINF
IEC05000337 V7 EN-US
16.4.7.3 Signals
PID-8269-INPUTSIGNALS v1
AU_OPEN and AU_CLOSE are used to issue automated commands. They work without
regard to how the operator place selector, PSTO, is set. In order to have effect on the outputs
EXE_OP and EXE_CL, the corresponding enable input, EN_OPEN respectively EN_CLOSE
must be set, and that no interlocking is active.
L_SEL, L_OPEN and L_CLOSE are used for local command sequence connected to binary
inputs. In order to have effect, the operator place selector, PSTO, must be set to local or to
remote with no priority. Also, the corresponding enable input must be set, and no interlocking
is active. The L_SEL input must always be set before L_OPEN or L_CLOSE, regardless of
the control model. This is to ensure no accidental operations occur.
If one multi-phase XCBR/XSWI or two single-phase XCBR/XSWI are used for a two-
or three-phase system, two or more of the inputs XPOSL1, XPOSL2 and XPOSL3 are
connected to the same source.
16.4.7.4 Settings
PID-8269-SETTINGS v1
.
Two types of control models can be used. The two control models are "direct with normal security" and
"SBO (Select-Before-Operate) with enhanced security". The parameter CtlModel defines which one of
the two control models is used. The control model "direct with normal security" does not require a select
whereas, the "SBO with enhanced security" command model requires a select before execution. The
command sequence for a command with control mode SBO with enhanced security is shown in figure
482, with control mode direct with normal security is shown in figure 483.
Reservation SXCBR /
Client SCSWI
logic SXSWI
select
SEL_CL = TRUE
tReservation RES_RQ = TRUE
Response
tSelect
RES_GRT = TRUE
SELECTED = TRUE
selectAck/AddCause = 0
requestedPosition = 10
opRcvd = TRUE
EXE_CL
RES_RQ = FALSE
RES_GRT = FALSE
IEC15000416-2-EN.vsdx
IEC15000416 V2 EN-US
Figure 482: Example of command sequence for a successful close command when the control model SBO with enhanced
security is used
requestedPosition = 10
opRcvd = TRUE
RES_RQ
tReservation
Response
RES_GRT = TRUE
EXE_CL
operateAck/AddCause = 0 operateAck/AddCause = 0
RES_RQ = FALSE
RES_GRT = FALSE
IEC15000417-1-en.vsdx
IEC15000417 V1 EN-US
Figure 483: Example of command sequence for a successful close command when the control model direct with normal
security is used
Normal security means that only the command is evaluated and the resulting position is not supervised.
Enhanced security means that the command sequence is supervised in three steps, the selection,
command evaluation and the supervision of position. Each step ends up with a pulsed signal to indicate
that the respective step in the command sequence is finished. If an error occurs in one of the steps in
the command sequence, the sequence is terminated. The last error (L_CAUSE) can be read from the
function block and used for example at commissioning.
Before an execution command, an evaluation of the position is done. If the parameter PosDependent is
set to Not perm 00/11 or Not perm cPos/00/11, and the position is in intermediate state or in bad state,
the command is rejected with the cause Invalid-position. If the parameter is set to Not perm cPos or
Not perm cPos/00/11 and the command is to move to the current position, the command is rejected with
the cause Position-reached. If the parameter is set to Always permitted the execution command is sent
independent of the position value.
The position output from the switches (SXCBR or SXSWI) is connected to the switch controller SCSWI.
The XPOSL1, XPOSL2 and XPOSL3 input signals receive the position, time stamps and quality
attributes of the position which is used for further evaluation.
In the case when there are two or more one-phase switches connected to the switch control function, the
switch control will "merge" the position of the switches to the resulting multi-phase position. In the case
when the position differ between the one-phase switches, following principles will be applied:
The time stamp of the output multi-phase position from switch control will have the time stamp of the last
changed phase when it reaches the end position. When it goes to intermediate position or bad state, it
will get the time stamp of the first changed phase.
In addition, there is also the possibility that one of the one-phase switches will change position at any
time due to a trip. Such situation is here called pole discrepancy and is supervised by this function. In
case of a pole discrepancy situation, that is, the positions of the one-phase switches are not equal for a
time longer than the setting tPoleDiscord, an error signal POLEDISC will be set.
In the supervision phase, the switch controller function evaluates the "cause" values from the switch
modules circuit breaker (SXCBR)/circuit switch (SXSWI). At error the "cause" value with highest priority
is shown.
The blocking signals are normally coming from the bay control function (QCBAY) or via the IEC 61850
communication from the operator place.
The different block conditions will only affect the operation of this function, that is, no blocking
signals will be "forwarded" to other functions. The above blocking outputs are stored in a
non-volatile memory.
For the commands from a communication protocol, such as IEC 61850-8-1, and through the inputs
L_SEL, L_OPEN and L_CLOSE, the operator place is evaluated, and only the commands from actual
operator place are accepted, see Table 524. Commands through the inputs L_SEL, L_OPEN and
L_CLOSE are always from the local operator place. For commands through the inputs AU_OPEN and
AU_CLOSE, the operator place is only evaluated so that it is not set to Off or is invalid.
The Switch controller (SCSWI) works in conjunction with the synchronism-check and the synchronizing
function (SESRSYN, 25). It is assumed that the synchronism-check function is continuously in operation
and gives the result to SCSWI. The result from the synchronism-check function is evaluated during the
close execution. If the operator performs an override of the synchronism-check, the evaluation of the
synchronism-check state is omitted. When there is a positive confirmation from the synchronism-check
function, SCSWI will send the close signal EXE_CL to the switch function Circuit breaker (SXCBR).
When there is no positive confirmation from the synchronism-check function, SCSWI will send a start
signal START_SY to the synchronizing function, which will send the closing command to SXCBR when
the synchronizing conditions are fulfilled, see Figure 484. If no synchronizing function is included, the
timer for supervision of the "synchronizing in progress signal" is set to 0, which means no start of the
synchronizing function. SCSWI will then set the attribute "blocked-by-synchronism-check" in the "cause"
signal. See also the time diagram in Figure 488.
SCSWI SXCBR
EXE_CL
OR CLOSE
SYNC_OK
START_SY
SY_INPRO
SESRSYN
CLOSECMD
Synchro Synchronizing
check function
ANSI09000209-1-en.vsd
ANSI09000209 V1 EN-US
Figure 484: Example of interaction between SCSWI, SESRSYN (25) (synchronism check and synchronizing function) and
SXCBR function
The Switch controller (SCSWI) function has timers for evaluating different time supervision conditions.
These timers are explained here.
The timer tSelect is used for supervising the time between the select and the execute command signal,
that is, the time the operator has to perform the command execution after the selection of the object to
operate.
select
execute command
tSelect
timer t1 t1>tSelect, then long-
operation-time in 'cause'
is set
en05000092.vsd
IEC05000092 V1 EN-US
The Long-operation-time cause (-30) is only given on the output L_CAUSE. It is not sent
on protocols since the selection has already received a positive response, and no operation
has been issued. If an operation is issued after the time out, the negative response is
Object-not-selected.
The parameter tResResponse is used to set the maximum allowed time to make the reservation, that is,
the time between reservation request and the feedback reservation granted from all bays involved in the
reservation function.
select
The timer tExecutionFB supervises the time between the execute command and the command
termination, see Figure 487.
execute command
phase A open
close
phase B open
close
phase C open
close
command termination
phase A
command termination
phase B
command termination
phase C
command termination *
close
The parameter tSynchrocheck is used to define the maximum allowed time between the execute
command and the input SYNC_OK to become true. If SYNC_OK=true at the time the execute command
signal is received, the timer "tSynchrocheck" will not start. The start signal for the synchronizing is
obtained if the synchronism-check conditions are not fulfilled.
The parameter tSynchronizing is used to define the maximum allowed time between the start signal for
synchronizing and the confirmation that synchronizing is in progress.
execute command
SYNC_OK
tSynchrocheck
t1
START_SY
SY_INPRO
tSynchronizing
t2>tSynchronizing, then
t2 blocked-by-synchronism
check in 'cause' is set
en05000095_ansi.vsd
ANSI05000095 V1 EN-US
The purpose of Circuit breaker (SXCBR) is to provide the actual status of positions and to perform the
control operations, that is, pass all the commands to primary apparatuses in the form of circuit breakers
via binary output boards and to supervise the switching operation and position.
SXCBR
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE SUBSTED
BL_OPEN OP_BLKD
BL_CLOSE CL_BLKD
BL_UPD UPD_BLKD
POSOP EN POSITION
POSCLOSE OPENP OS
CBOPCAP CLOSEPOS
TR_OPEN TR_POS
TR_CLOSE CNT_VAL
RS_CNT L_CAUSE
EEH_WARN EEHEALTH
EEH_ALM CBOPCAP
XIN
IEC05000338-6-en.vsdx
IEC05000338 V6 EN-US
16.4.8.3 Signals
PID-6799-INPUTSIGNALS v3
PID-6799-OUTPUTSIGNALS v3
16.4.8.4 Settings
PID-6799-SETTINGS v3
SXCBR has an operation counter for closing and opening commands. The counter value can be read
remotely from the operator place. The value is reset from local HMI, a binary input or remotely from
the operator place by configuring a signal from the Single Point Generic Control 8 signals (SPC8GAPC)
for example. The health of the external equipment, the switch, can be monitored according to IEC
61850-8-1. The operation counter functionality and the external equipment health supervision are
independent sub-functions of the circuit breaker function.
One binary input signal LR_SWI is included in SXCBR to indicate the local/remote switch position from
switchyard provided via the I/O board. If this signal is set to TRUE it means that change of position is
allowed only from switchyard level. If the signal is set to FALSE it means that command from IED or
higher level is permitted. When the signal is set to TRUE all commands (for change of position) are
rejected, even trip commands from protection functions are rejected. The functionality of the local/remote
switch is described in Figure 490.
Local= Operation at
UE switch yard level
TR
en05000096.vsd
IEC05000096 V1 EN-US
SXCBR includes several blocking principles. The basic principle for all blocking signals is that they
will affect commands from all other clients for example, switch controller, protection functions and
autoreclosure.
• Block/deblock for open command. It is used to block operation for the open command.
• Block/deblock for close command. It is used to block operation for the close command.
• Update block/deblock of positions. It is used to block the updating of position values. Other signals
related to the position will be reset.
• Blocking of function, BLOCK. If BLOCK signal is set, it means that the function is active, but no
outputs are generated, no reporting, control commands are rejected and functional and configuration
data is visible.
Substitution M13487-22 v5
The substitution part in SXCBR is used for manual set of the position and quality of the switch. The
typical use of substitution is that an operator enters a manual value because that the real process value
is erroneous for some reason. SXCBR will then use the manually entered value instead of the value for
positions determined by the process.
It is always possible to make a substitution, independently of the position indication and the
status information of the I/O board. When substitution is enabled, the other signals related to
the position follow the substituted position. The substituted values are stored in a non-volatile
memory. If the function is blocked or blocked for update when the substitution is released, the
position value is kept the same as the last substitution value, but the quality is changed to
"questionable, old data", indicating that the value is old and not reliable.
When the position of the SXCBR is substituted, its IEC 61850-8-1 data object is marked as
“substituted", in addition to the substituted quality, but the position quality of the connected
SCSWI is not dependent on the substitution indication in the quality, so it does not show that
it is derived from a substituted value.
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStartMove
supervises that the primary device starts moving after the execute output pulse is sent. tIntermediate
defines the maximum allowed time for intermediate position. Figure 491 explains these two timers during
the execute phase.
OPENPOS
CLOSEPOS
en05000097.vsd
IEC05000097 V1 EN-US
The timers tOpenPulse and tClosePulse are the minimum length of the execute output pulses to be
sent to the primary equipment. Note that the output pulses for open and close command can have
different pulse lengths. The pulses can also be set to be adaptive with the configuration parameter
AdaptivePulse. Figure 492 shows the principle of the execute output pulse. The AdaptivePulse
parameter will have effect on both execute output pulses. However, as long as the OPEN or CLOSE
inputs are active, the corresponding execute output will remain active if the operation is allowed, thus
overriding AdaptivePulse parameter.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
en05000098.vsd
IEC05000098 V1 EN-US
If the pulse is set to be adaptive and the activating input is not still active, it is not possible for the pulse
to exceed tOpenPulse or tClosePulse.
The execute output pulses are reset when the activating input is reset and either of the following
happens:
• the new expected final position is reached and the configuration parameter AdaptivePulse is set to
true
• the timer tOpenPulse or tClosePulse has elapsed
• an error occurs due to the switch not start moving, that is tStartMove has elapsed for normal
commands, or tIntermediate has elapsed starting from intermediate position, and the position
indications are valid.
If either of the position inputs are invalid or unconnected, the combined position is considered as invalid.
Then the execute output pulse resets at earliest when time tOpenPulse or tClosePulse has elapsed.
If the breaker reaches the final position before the execution pulse time has elapsed, and
AdaptivePulse is not true, then the function waits for the end of the execution pulse before
indicating the activating function that the command is complete.
If the activating input remains active when the breaker has reached its final position and the
execution pulse time has elapsed, then the function waits for the reset of the activating input
before indicating that the command is complete.
There is one exception to the first item above: if the primary device is in open position and an open
command is executed or if the primary device is in closed position and a close command is executed.
In these cases, with the additional condition that the configuration parameter AdaptivePulse is true, the
execute output pulse is always activated and resets when tStartMove has elapsed. If the configuration
parameter AdaptivePulse is set to false, the execution output remains active until the pulse duration
timer has elapsed.
If the start position indicates bad state (OPENPOS=1 and CLOSEPOS=1) when a command
is executed, the execute output pulse resets at earliest when timer tOpenPulse or
tClosePulse has elapsed.
An example of when a primary device is open and an open command is executed is shown in
Figure 493 .
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
en05000099.vsd
IEC05000099 V1 EN-US
The purpose of Circuit switch (SXSWI) function is to provide the actual status of positions and to
perform the control operations, that is, pass all the commands to primary apparatuses in the form of
disconnectors or grounding switches via binary output boards and to supervise the switching operation
and position.
SXSWI
BLOCK XPOS
LR_SWI EXE_OP
OPEN EXE_CL
CLOSE SUBSTED
BL_OPEN OP_BLKD
BL_CLOSE CL_BLKD
BL_UPD UPD_BLKD
POSOP EN POSITION
POSCLOSE OPENP OS
SWOPCAP CLOSEPOS
RS_CNT CNT_VAL
EEH_WARN L_CAUSE
EEH_ALM EEHEALTH
XIN SWOPCAP
IEC05000339-5-en.vsdx
IEC05000339 V5 EN-US
16.4.9.3 Signals
PID-6800-INPUTSIGNALS v4
16.4.9.4 Settings
PID-6800-SETTINGS v4
SXSWI has an operation counter for closing and opening commands. The counter value can be read
remotely from the operator place. The value is reset from a binary input or remotely from the operator
place by configuring a signal from the Single Point Generic Control 8 signals (SPC8GAPC), for example.
Also, the health of the external equipment, the switch, can be monitored according to IEC 61850-8-1.
One binary input signal LR_SWI is included in SXSWI to indicate the local/remote switch position from
switchyard provided via the I/O board. If this signal is set to TRUE it means that change of position is
allowed only from switchyard level. If the signal is set to FALSE it means that command from IED or
higher level is permitted. When the signal is set to TRUE all commands (for change of position) from
internal IED clients are rejected. The functionality of the local/remote switch is described in Figure 495.
Local= Operation at
UE switch yard level
TR
en05000096.vsd
IEC05000096 V1 EN-US
SXSWI includes several blocking principles. The basic principle for all blocking signals is that they
will affect commands from all other clients for example, switch controller, protection functions and
autorecloser.
• Block/deblock for open command. It is used to block operation for open command.
• Block/deblock for close command. It is used to block operation for close command.
• Update block/deblock of positions. It is used to block the updating of position values. Other signals
related to the position will be reset.
• Blocking of function, BLOCK. If BLOCK signal is set, it means that the function is active, but no
outputs are generated, no reporting, control commands are rejected and functional and configuration
data is visible.
Substitution M16494-21 v7
The substitution part in SXSWI is used for manual set of the position and quality of the switch. The
typical use of substitution is that an operator enters a manual value because the real process value is
erroneous of some reason. SXSWI will then use the manually entered value instead of the value for
positions determined by the process.
It is always possible to make a substitution, independently of the position indication and the
status information of the I/O board. When substitution is enabled, the other signals related to
the position follow the substituted position. The substituted values are stored in a non-volatile
memory. If the function is blocked or blocked for update when the substitution is released, the
position value is kept the same as the last substitution value, but the quality is changed to
"questionable, old data", indicating that the value is old and not reliable.
When the position of the SXSWI is substituted, its IEC 61850-8-1 data object is marked as
“substituted", in addition to the substituted quality, but the position quality of the connected
SCSWI is not dependent on the substitution indication in the quality, so it does not show that
it is derived from a substituted value.
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStartMove
supervises that the primary device starts moving after the execute output pulse is sent. tIntermediate
defines the maximum allowed time for intermediate position. Figure 496 explains these two timers during
the execute phase.
OPENPOS
CLOSEPOS
en05000097.vsd
IEC05000097 V1 EN-US
The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to the
primary equipment. Note that the output pulses for open and close command can have different pulse
lengths. The pulses can also be set to be adaptive with the configuration parameter AdaptivePulse.
Figure 497 shows the principle of the execute output pulse. The AdaptivePulse parameter will have
effect on both execute output pulses.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
EXE_CL
tClosePulse
AdaptivePulse=TRUE
EXE_CL
tClosePulse
en05000098.vsd
IEC05000098 V1 EN-US
If the pulse is set to be adaptive and the activating input is not still active, it is not possible for the pulse
to exceed tOpenPulse or tClosePulse.
For the SXSWI the activating inputs should be pulsed, however, the functionality of following them is the
same as for SXCBR.
The execute output pulses are reset when the activating input is reset and either of the following
happens:
• the new expected final position is reached and the configuration parameter AdaptivePulse is set to
true
• the timer tOpenPulse or tClosePulse has elapsed
• an error occurs due to the switch not start moving, that is tStartMove has elapsed for normal
commands, or tIntermediate has elapsed starting from intermediate position, and the position
indications are valid.
If either of the position inputs are invalid or unconnected, the combined position is considered as invalid.
Then the execute output pulse resets at earliest when time tOpenPulse or tClosePulse has elapsed.
If the controlled primary device reaches the final position before the execution pulse time has
elapsed, and AdaptivePulse is not true, the function waits for the end of the execution pulse
before indicating the activating function that the command is completed.
If the activating input remains active when the switch has reached its final position and the
execution pulse time has elapsed, the function waits for the reset of the activating input
before indicating that the command is completed.
There is one exception from the first item above. If the primary device is in open position and an open
command is executed or if the primary device is in close position and a close command is executed.
In these cases, with the additional condition that the configuration parameter AdaptivePulse is true, the
execute output pulse is always activated and resets when tStartMove has elapsed. If the configuration
parameter AdaptivePulse is set to false the execution output remains active until the pulse duration timer
has elapsed.
If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command
is executed the execute output pulse resets only when timer tOpenPulse or tClosePulse has
elapsed.
An example when a primary device is open and an open command is executed is shown in Figure 498.
OPENPOS
CLOSEPOS
EXE_OP AdaptivePulse=FALSE
tOpenPulse
EXE_OP AdaptivePulse=TRUE
tOpenPulse
tStartMove timer
en05000099.vsd
IEC05000099 V1 EN-US
16.4.10 Proxy for signals from switching device via GOOSE XLNPROXY
The proxy for signals from switching device via GOOSE (XLNPROXY) gives an internal representation
of the position status and control response for a switch modelled in a breaker IED. This representation is
identical to that of an SXCBR or SXSWI function.
XLNPROXY
BEH* XPOS
BEH_VALID* SELECTED
LOC* OP_BLKD
LOC_VALID* CL_BLKD
BLKOPN* OPENPOS
BLKOPN_V* CLOSEPOS
BLKCLS* CNT_VAL
BLKCLS_V* L_CAUSE
POSVAL* EEHEALTH
POSVAL_V* OPCAP
OPCNT*
OP_CNT_V*
BLK
BLK_VAL
STSELD
STSELD_V
OPRCVD
OPRCVD_V
OPOK
OPOK_VAL
EEHEALTH
EEH_VAL
OPCAP
OPCAP_V
COMMVALID
XIN
IEC16000043-1-en.vsdx
IEC16000043 V1 EN-US
16.4.10.3 Signals
PID-6712-INPUTSIGNALS v3
16.4.10.4 Settings
PID-6712-SETTINGS v3
The default values of the inputs BEH, OPCNT, EEHEALTH and OPCAP are set to -1 to
denote that they are not connected.
The proxy for signals from switching device via GOOSE (XLNPROXY) is intended to be used when
the switch (XCBR/XSWI) is modelled and controlled in a breaker IED or similar unit on the process
bus. XLNPROXY packages the signals from the GOOSE receive function, normally GOOSEXLNRCV,
into the same format as used from SXCBR and SXSWI to SCSWI. It makes a similar evaluation of the
command response as SXCBR and SXSWI when a command is issued from the connected SCSWI.
XLNPROXY has two outputs for position indication: OPENPOS and CLOSEPOS. Position is a double
point indication and the OPENPOS and CLOSEPOS are binary outputs intended to be used for
condition logics to protection and control functions
Normally, the position outputs, OPENPOS and CLOSEPOS, follow the value of the input POSVAL.
However, if the POSVAL_V input is FALSE, the communication is lost (COMMVALID = FALSE), or the
quality of the position received is bad, the OPENPOS and CLOSEPOS are both set to FALSE.
The command evaluation is triggered through the group input XIN that is connected to the SCSWI
function controlling the switch.
If an operation is initiated by the SCSWI, the XLNPROXY function checks if the switch is blocked for
the operation direction and that the position moves to the desired position within the two time limits
tStartMove and tIntermediate. The default values for tStartMove and tIntermediate are for a breaker. The
typical values for a disconnector are:
• tStartMove = 3s
• tIntermediate = 15s
In most cases, tStartMove and tIntermediate can be set to the same values as in the
source XCBR or XSWI function. However, if the time limits are set very close to the actual
movement times of the apparatus, compensation may be needed for the communication
delays and differences in cycle time of the XLNPROXY function and the source function. The
compensation should be in the range of 0 - 5ms.
When the switch has started moving, it issues a response to the SCSWI function that the operation has
started. If it does not start moving within tStartMove, the command is deemed as failed, and a cause
is raised on the L_CAUSE output and sent to the SCSWI. The different causes it can identify are listed
in order of priority in table 1. The detection of the different ways of blocking is done while waiting for
movement of the switch, but the cause is not given until the tStartMove has elapsed.
The L_CAUSE output keeps its output value until a new command sequence has been started.
If the quality of the position or the communication becomes bad, the command evaluation replaces the
uncertain position value with intermediate position. Thus, as long as the quality is bad, all commands will
result in the cause Persistant-intermediate-state, -32.
If the switch in the merging unit has the behaviour set to Test or Test blocked, when the IED has the
behaviour On or Blocked, all data from the switch is regarded as invalid. Thus, any command will fail
with the cause PersistantiIntermediate-state, -32, and if selection is used for the switch, all attempts to
select the connected SCSWI will fail with the cause Select-failed, 3, from the SCSWI.
It is possible to speed up the command response for when the command has been started by the switch
in the breaker IED by connecting the inputs OPOK and OPOK_VAL. Then the blocking check is only
done until OPOK is activated and confirmation of that the command has been started is given to the
SCSWI function.
If the inputs STSELD and STSELD_V are connected, the switch in the breaker IED is assumed to use
selection. Then the SCSWI will wait for a selected indication, STSELD input of XLNPROXY, before
accepting selection, this information is transferred to the SCSWI function from the XLNPROXY through
the group connection XPOS. If STSELD is not activated within tSelect of the SCSWI function, the
selection is deemed failed and it gives a negative selection acknowledgement to the command issuer
with the cause Select-failed. Further, if the communication is lost, or the data received is deemed invalid,
the selection will also fail with cause Select-failed from the SCSWI.
The purpose of the reservation (QCRSV) function is primarily to transfer interlocking information
between IEDs in a safe way and to prevent double operation in a bay, switchyard part, or complete
substation.
QCRSV
EXCH_IN RES_GRT1
RES_RQ1 RES_GRT2
RES_RQ2 RES_GRT3
RES_RQ3 RES_GRT4
RES_RQ4 RES_GRT5
RES_RQ5 RES_GRT6
RES_RQ6 RES_GRT7
RES_RQ7 RES_GRT8
RES_RQ8 RES_BAYS
BLOCK ACK_TO_B
OVERRIDE RESERVED
RES_DATA EXCH_OUT
IEC05000340-3-en.vsdx
IEC05000340 V3 EN-US
16.4.11.3 Signals
PID-3561-INPUTSIGNALS v7
16.4.11.4 Settings
PID-3561-SETTINGS v7
The parameters ParamRequestx (x=1-8) are chosen at reservation of the own bay only (TRUE) or other
bays (FALSE). To reserve the own bay only means that no reservation request RES_BAYS is created.
If the reservation request comes from the own bay, the function QCRSV has to know which apparatus
the request comes from. This information is available with the input signal RES_RQx and parameter
ParamRequestx (where x=1-8 is the number of the requesting apparatus). In order to decide if a
reservation request of the current bay can be permitted QCRSV has to know whether the own
bay already is reserved by itself or another bay. This information is available in the output signal
RESERVED.
If the RESERVED output is not set, the selection is made with the output RES_GRTx (where x=1-8
is the number of the requesting apparatus), which is connected to switch controller SCSWI. If the
bay already is reserved the command sequence will be reset and the SCSWI will set the attribute
"1-of-n-control" in the "cause" signal.
When the function QCRSV receives a request from an apparatus in the own bay that requires other bays
to be reserved as well, it checks if it already is reserved. If not, it will send a request to the other bays
that are predefined (to be reserved) and wait for their response (acknowledge). The request of reserving
other bays is done by activating the output RES_BAYS.
When it receives acknowledge from the bays via the input RES_DATA, it sets the output RES_GRTx
(where x=1-8 is the number of the requesting apparatus). If not acknowledgement from all bays is
received within a certain time defined in SCSWI (tResResponse), the SCSWI will reset the reservation
and set the attribute "1-of-n-control" in the "cause" signal.
When another bay requests for reservation, the input BAY_RES in corresponding function block RESIN
is activated. The signal for reservation request is grouped into the output signal EXCH_OUT in RESIN,
which is connected to input RES_DATA in QCRSV. If the bay is not reserved, the bay will be reserved
and the acknowledgment from output ACK_T_B is sent back to the requested bay. If the bay already is
reserved the reservation is kept and no acknowledgment is sent.
If QCRSV function is blocked (input BLOCK is set to true) the reservation is blocked. That is, no
reservation can be made from the own bay or any other bay. This can be set, for example, via a binary
input from an external device to prevent operations from another operator place at the same time.
The reservation function can also be overridden in the own bay with the OVERRIDE input signal, that is,
reserving the own bay without waiting for the external acknowledge.
If only one instance of QCRSV is used for a bay that is, use of up to eight apparatuses, the input
EXCH_IN must be set to zero.
If there are more than eight apparatuses in the bay, there has to be one additional QCRSV. The two
QCRSV functions have to communicate and this is done through the input EXCH_IN and EXCH_OUT
according to Figure 501. If more than one QCRSV are used, the execution order is very important. The
execution order must be in the way that the first QCRSV has a lower number than the next one.
QCRSV
EXCH_IN RES_ GRT1
RES_RQ1 RES_ GRT2
RES_RQ2 RES_ GRT3
RES_RQ3 RES_ GRT4
RES_RQ4 RES_ GRT5
RES_RQ5 RES_ GRT6
RES_RQ6 RES_ GRT7
RES_RQ7 RES_ GRT8
RES_RQ8 RES_ BAYS
BLK_ RES ACK_TO_B
OVERRIDE RESERVED
RES_ DATA EXCH_ OUT
QCRSV
EXCH_IN RES_ GRT1
RES_RQ1 RES_ GRT2
RES_RQ2 RES_ GRT3 RES_ BAYS
OR
RES_RQ3 RES_ GRT4
RES_RQ4 RES_ GRT5
RES_RQ5 RES_ GRT6 ACK_TO_B
RES_RQ6 RES_ GRT7 OR
RES_RQ7 RES_ GRT8
RES_RQ8 RES_ BAYS
BLK_ RES ACK_TO_B RESERVED
OR
OVERRIDE RESERVED
RES_ DATA EXCH_ OUT
ANSI05000088_2_en.vsd
ANSI05000088 V2 EN-US
The Reservation input (RESIN) function receives the reservation information from other bays. The
number of instances is the same as the number of involved bays (up to 60 instances are available).
RESIN1
BAY_ACK ACK_F_B
BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
IEC05000341-2-en.vsd
IEC05000341 V2 EN-US
RESIN2
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
IEC09000807_1_en.vsd
IEC09000807 V1 EN-US
16.4.12.3 Signals
PID-3629-INPUTSIGNALS v7
16.4.12.4 Settings
PID-3629-SETTINGS v7
The reservation input (RESIN) function is based purely on Boolean logic conditions. The logic diagram in
Figure 504 shows how the output signals are created. The inputs of the function block are connected to
a receive function block representing signals transferred over the station bus from another bay.
EXCH_IN INT
BIN
ACK_F_B
AND
FutureUse
OR
ANY_ACK
BAY_ACK OR
VALID_TX
AND
BAY_VAL OR
RE_RQ_B
OR
BAY_RES AND
V _RE_RQ
OR
BIN
EXCH_OUT
INT
INT……..Integer
BIN……..Binary en05000089_ansi.vsd
ANSI05000089 V1 EN-US
Figure 505 describes the principle of the data exchange between all RESIN modules in the current
bay. There is one RESIN function block per "other bay" used in the reservation mechanism. The output
signal EXCH_OUT in the last RESIN functions are connected to the module bay reserve (QCRSV) that
handles the reservation function in the own bay.
RESIN
BAY_ACK ACK_F_B
Bay 1 BAY_VAL ANY_ACK
BAY_RES VALID_TX
RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay 2 BAY_VAL VALID_TX
BAY_RES RE_RQ_B
V_RE_RQ
EXCH_OUT
RESIN
EXCH_IN ACK_F_B
BAY_ACK ANY_ACK
Bay n BAY_VAL VALID_TX
BAY_RES RE_RQ_B QCRSV
V_RE_RQ
EXCH_OUT RES_DATA
en05000090.vsd
IEC05000090 V2 EN-US
16.5.1 Identification
SEMOD167845-2 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Logic rotating switch for SLGAPC - -
function selection and
WebUI presentation
The logic rotating switch for function selection and LHMI presentation (SLGAPC) (or the selector switch
function block) is used to get an enhanced selector switch functionality compared to the one provided
by a hardware selector switch. Hardware selector switches are used extensively by utilities, in order
to have different functions operating on pre-set values. Hardware switches are however sources for
maintenance issues, lower system reliability and an extended purchase portfolio. The selector switch
function eliminates all these problems.
SLGAPC
BLOCK ^P01
PSTO ^P02
UP ^P03
DOWN ^P04
^P05
^P06
^P07
^P08
^P09
^P10
^P11
^P12
^P13
^P14
^P15
^P16
^P17
^P18
^P19
^P20
^P21
^P22
^P23
^P24
^P25
^P26
^P27
^P28
^P29
^P30
^P31
^P32
SWPOSN
IEC14000005 V2 EN-US
16.5.4 Signals
PID-6641-INPUTSIGNALS v4
16.5.5 Settings
PID-6641-SETTINGS v4
descending order (for example if the present activated output is P03 and one activates the DOWN input
then the output P02 will be activated). Depending on the output settings the output signals can be steady
or pulsed. In case of steady signals, the output will be active till the time it receives next operation of
UP/DOWN inputs. Also, depending on the settings one can have a time delay between activation of the
UP or DOWN input signals and the output activation.
Besides the inputs visible in the application configuration in the Application Configuration Tool, there
are other possibilities that will allow an user to set the desired position directly (without activating the
intermediate positions), either locally or remotely, using a “select before execute” dialog. One can block
the function operation, by activating the BLOCK input. In this case, the present position will be kept
and further operation will be blocked. The operator place (local or remote) is specified through the
PSTO input. If any operation is allowed the signal INTONE from the Fixed signal function block can be
connected. SLGAPC function block has also an integer value output, that generates the actual position
number. The positions and the block names are fully settable by the user. These names will appear in
the menu, so the user can see the position names instead of a number.
• if it is used just for the monitoring, the switches will be listed with their actual position names, as
defined by the user (max. 13 characters).
• if it is used for control, the switches will be listed with their actual positions, but only the first three
letters of the name will be used.
In both cases, the switch full name will be shown, but the user has to redefine it when building
the Graphical Display Editor, under the "Caption". If used for the control, the following sequence of
commands will ensure:
Control
Control Single Line Diagram
Measurements Commands
Events
Disturbance records
Settings
Diagnostics
Test
Change to the "Switches" page Reset
of the SLD by left-right arrows. Authorization
Select switch by up-down Language
arrows
../Control/SLD/Switch
SMBRREC control
WFM
Pilot setup
OFF
Damage control
DFW
ANSI06000421-2-en.vsd
ANSI06000421 V2 EN-US
Figure 507: Example 2 on handling the switch from the local HMI.
From the single line diagram on local HMI.
16.6.1 Identification
SEMOD167850-2 v4
The Selector mini switch (VSGAPC) function block is a multipurpose function used for a variety of
applications, as a general purpose switch.
VSGAPC can be controlled from a symbol on the single line diagram (SLD) on the local HMI or from
binary inputs.
VSGAPC
BLOCK BLOCKED
PSTO POSITION
IPOS1 POS1
IPOS2 POS2
CMDPOS12
CMDPOS21
IEC14000066 V2 EN-US
16.6.4 Signals
PID-7478-INPUTSIGNALS v1
16.6.5 Settings
PID-7478-SETTINGS v1
Selector mini switch (VSGAPC) function can be used for double purpose, in the same way as switch
controller (SCSWI) functions are used:
• for indication on the single line diagram (SLD). Position is received through the IPOS1 and IPOS2
inputs and distributed in the configuration through the POS1 and POS2 outputs, or to IEC 61850
through reporting, or GOOSE.
• for commands that are received via the local HMI or IEC 61850 and distributed in the configuration
through outputs CMDPOS12 and CMDPOS21.
The output CMDPOS12 is set when the function receives a CLOSE command from the local HMI
when the SLD is displayed and the object is chosen.
The output CMDPOS21 is set when the function receives an OPEN command from the local HMI
when the SLD is displayed and the object is chosen.
It is important for indication in the SLD that a symbol is associated with a controllable object,
otherwise the symbol won't be displayed on the screen. A symbol is created and configured
in GDE tool in PCM600.
The PSTO input is connected to the Local remote switch to have a selection of operators place,
operation from local HMI (Local) or through IEC 61850 (Remote). An INTONE connection from Fixed
signal function block (FXDSIGN) will allow operation from local HMI.
As it can be seen, both indications and commands are done in double-bit representation, where a
combination of signals on both inputs/outputs generate the desired result.
The following table shows the relationship between IPOS1/IPOS2 inputs and the name of the string that
is shown on the SLD. The value of the strings are set in PST.
16.7.1 Identification
GUID-E16EA78F-6DF9-4B37-A92D-5C09827E2297 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Generic communication DPGAPC - -
function for double point
indication
Generic communication function for double point indication (DPGAPC) function block is used to send
double point position indications to other systems, equipment or functions in the substation through IEC
61850-8-1 or other communication protocols. It is especially intended to be used in the interlocking
station-wide logics.
DPGAPC
OPEN POSITION
CLOSE
VALID
IEC13000081 V2 EN-US
PID-4139-INPUTSIGNALS v12
The function does not have any parameters available in the local HMI or PCM600.
When receiving the input signals, DPGAPC sends the signals over IEC 61850-8-1 to the systems,
equipment or functions that requests and thus subscribes on these signals. To be able to get the signals
into other systems, equipment or functions, one must use other tools, described in the Engineering
manual, and define which function block in which systems, equipment or functions should receive this
information.
More specifically, DPGAPC function reports a combined double point position indication output
POSITION, by evaluating the value and the timestamp attributes of the inputs OPEN and CLOSE,
together with the logical input signal VALID.
When the input signal VALID is active, the values of the OPEN and CLOSE inputs determine the two-bit
integer value of the output POSITION. The timestamp of the output POSITION will have the latest
updated timestamp of the inputs OPEN and CLOSE.
When the input signal VALID is inactive, DPGAPC function forces the position to intermediated state.
When the value of the input signal VALID changes, the timestamp of the output POSITION will be
updated as the time when DPGAPC function detects the change.
Refer to Table 561 for the description of the input-output relationship in terms of the value and the quality
attributes.
POSITION
VALID OPEN CLOSE
Value Description
0 - - 0 Intermediate
1 0 0 0 Intermediate
1 1 0 1 Open
1 0 1 2 Closed
1 1 1 3 Bad State
16.8.2 Identification
SEMOD176456-2 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Single point generic control 8 SPC8GAPC - -
signals
The Single point generic control 8 signals (SPC8GAPC) function block is a collection of 8 single
point commands that can be used for direct commands for example reset of LEDs or putting IED in
"ChangeLock" state from remote. In this way, simple commands can be sent directly to the IED outputs,
without confirmation. Confirmation (status) of the result of the commands is supposed to be achieved
by other means, such as binary inputs and SPGAPC function blocks. The commands can be pulsed or
steady with a settable pulse time.
SPC8GAPC
BLOCK ^OUT1
PSTO ^OUT2
^OUT3
^OUT4
^OUT5
^OUT6
^OUT7
^OUT8
ANSI07000143-3-en.vsd
ANSI07000143 V1 EN-US
16.8.5 Signals
PID-3575-INPUTSIGNALS v8
PID-3575-OUTPUTSIGNALS v8
16.8.6 Settings
PID-3575-SETTINGS v8
The PSTO input selects the operator place (LOCAL, REMOTE or ALL). One of the eight outputs is
activated based on the command sent from the operator place selected. The settings Latchedx and
tPulsex (where x is the respective output) will determine if the signal will be pulsed (and how long the
pulse is) or latched (steady). BLOCK will block the operation of the function – in case a command is
sent, no output will be activated.
PSTO is the universal operator place selector for all control functions. Although, PSTO can
be configured to use LOCAL or ALL operator places, only REMOTE operator place is used in
SPC8GAPC function.
16.9.1 Identification
GUID-C3BB63F5-F0E7-4B00-AF0F-917ECF87B016 v4
Automation bits function for DNP3 (AUTOBITS) is used within PCM600 to get into the configuration
of the commands coming through the DNP3 protocol. The AUTOBITS function plays the same role as
functions GOOSEBINRCV (for IEC 61850) and MULTICMDRCV (for LON).
AUTOBITS
BLOCK ^CMDBIT1
PSTO ^CMDBIT2
^CMDBIT3
^CMDBIT4
^CMDBIT5
^CMDBIT6
^CMDBIT7
^CMDBIT8
^CMDBIT9
^CMDBIT10
^CMDBIT11
^CMDBIT12
^CMDBIT13
^CMDBIT14
^CMDBIT15
^CMDBIT16
^CMDBIT17
^CMDBIT18
^CMDBIT19
^CMDBIT20
^CMDBIT21
^CMDBIT22
^CMDBIT23
^CMDBIT24
^CMDBIT25
^CMDBIT26
^CMDBIT27
^CMDBIT28
^CMDBIT29
^CMDBIT30
^CMDBIT31
^CMDBIT32
IEC09000925-1-en.vsd
IEC09000925 V1 EN-US
16.9.4 Signals
PID-3776-INPUTSIGNALS v6
16.9.5 Settings
PID-3776-SETTINGS v6
AutomationBits function (AUTOBITS) has 32 individual outputs which each can be mapped as a Binary
Output point in DNP3. The output is operated by a "Object 12" in DNP3. This object contains parameters
for control-code, count, on-time and off-time. To operate an AUTOBITS output point, send a control-code
of latch-On, latch-Off, pulse-On, pulse-Off, Trip or Close. The remaining parameters will be regarded
were appropriate. ex: pulse-On, on-time=100, off-time=300, count=5 would give 5 positive 100 ms
pulses, 300 ms apart.
There is a BLOCK input signal, which will disable the operation of the function, in the same way the
setting Operation: Enabled/Disabled does. That means that, upon activation of the BLOCK input, all 32
CMDBITxx outputs will be set to 0. The BLOCK acts like an overriding, the function still receives data
from the DNP3 master. Upon deactivation of BLOCK, all the 32 CMDBITxx outputs will be set by the
DNP3 master again, momentarily. For AUTOBITS , the PSTO input determines the operator place. The
command can be written to the block while in “Remote”. If PSTO is in “Local” then no change is applied
to the outputs.
16.10.1 Identification
GUID-2217CCC2-5581-407F-A4BC-266CD6808984 v2
The IEDs can receive commands either from a substation automation system or from the local HMI. The
command function block has outputs that can be used, for example, to control high voltage apparatuses
or for other user defined functionality.
SINGLECMD
BLOCK ^OUT1
^OUT2
^OUT3
^OUT4
^OUT5
^OUT6
^OUT7
^OUT8
^OUT9
^OUT10
^OUT11
^OUT12
^OUT13
^OUT14
^OUT15
^OUT16
IEC05000698-2-en.vsd
IEC05000698 V3 EN-US
16.10.4 Signals
PID-6189-INPUTSIGNALS v7
16.10.5 Settings
PID-6189-SETTINGS v7
Single command, 16 inputs (SINGLECMD) function has 16 binary output signals. The outputs can be
individually controlled from a substation automation system or from the local HMI. Each output signal
can be given a name with a maximum of 13 characters in PCM600.
The output signals can be of the types Disabled, Steady, or Pulse. This configuration setting is done via
the local HMI or PCM600 and is common for the whole function block. The length of the output pulses
are 100 ms. In steady mode, SINGLECMD function has a memory to remember the output values at
power interruption of the IED. Also a BLOCK input is available used to block the updating of the outputs.
The output signals, OUT1 to OUT16, are available for configuration to built-in functions or via the
configuration logic circuits to the binary outputs of the IED.
17.1.2 Identification
M14854-1 v4
To achieve instantaneous fault clearance for all line faults, scheme communication logic is provided.
All types of communication schemes for permissive underreaching, permissive overreaching, blocking,
delta based blocking, unblocking and intertrip are available.
The built-in communication module (LDCM) can be used for scheme communication signaling when
included.
ZCPSCH
I3P* TRIP
V3P* CS
BLOCK CHSTOP
BLKTR CRL
BLKCS LCG
CS_STOP
PLTR_CRD
CSOR
CSUR
CR
CR_GUARD
CBOPEN
ANSI09000004.vsd
ANSI09000004 V4 EN-US
17.1.5 Signals
PID-3766-INPUTSIGNALS v7
17.1.6 Settings
PID-3766-SETTINGS v7
A permissive scheme is inherently faster and has better security against false tripping than a blocking
scheme. On the other hand, a permissive scheme depends on a received signal for a fast trip, so its
dependability is lower than that of a blocking scheme.
The principle of operation for a blocking scheme is that an overreaching zone is allowed to trip
instantaneously after the settable co-ordination time tCoord has elapsed, when no signal is received
from the remote IED.
The received signal, which shall be connected to CR, is used to block the zone to be accelerated to
clear the fault instantaneously (after time tCoord). The forward overreaching zone to be accelerated is
connected to the input PLTR_CRD, see figure 514.
In case of external faults, the blocking signal (CR) must be received before the settable timer tCoord
elapses to prevent a false trip, see figure 514.
The function can be totally blocked by activating the input BLOCK. Tripping can be blocked by activating
the input BLKTR. Signal send can be blocked by activating the input BLKCS.
PLTR-CRD
0-tCoord TRIP
CR AND 0
en05000512_ansi.vsd
ANSI05000512 V1 EN-US
In order to avoid delays due to carrier coordination times, the initiation of sending of blocking signal to
remote end is done by a fault inception detection element based on delta quantities of currents and
voltages. The delta based fault detection is very fast and if the channel is fast there is no need for
delaying the operation of the remote distance element. The received blocking signal arrives well before
the distance element has picked up. If the fault is in forward direction the sending is immediately stopped
by a forward directed distance, directional current or directional ground fault element.
The fault inception detection element detects instantaneous changes in any phase currents or zero
sequence current in combination with a change in the corresponding phase voltage or zero sequence
voltage. The criterion for the fault inception detection is if the change of any phase voltage and current
exceeds the settings DeltaV and DeltaI respectively, or if the change of zero sequence voltage and zero
sequence current exceeds the settings Delta3V0,Delta3I0 respectively. The schemeType is selected as
DeltaBlocking.
If the fault inception function has detected a system fault, a block signal CS will be issued and sent to
remote end in order to block the overreaching zones. Different criteria has to be fulfilled for sending the
CS signal:
1. The breaker has to be in closed condition, that is, the input signal CBOPEN is deactivated.
2. A fault inception should have been detected while the carrier send signal is not blocked, that is, the
input signal BLKCS is not activated.
If it is later detected that it was an internal fault that made the function issue the CS signal, the function
will issue a CHSTOP signal to unblock the remote end.
The received signal, which is connected to the CR input, is not used to accelerate the release of
the overreaching zone to clear the fault instantaneously. The overreaching zone to be accelerated is
connected to the input PLTR_CRD, see Figure 515.
In case of external faults, the blocking signal (CR) must be received before the settable timer tCoord
elapses, to prevent a false trip, see Figure 515.
The function can be totally blocked by activating the input BLOCK, block of trip by activating the input
BLKTR, block of carrier send by activating the input BLKCS.
PLTR-CRD
0-tCoord TRIP
CR AND 0
en05000512_ansi.vsd
ANSI05000512 V1 EN-US
Figure 515: Basic logic for trip signal in delta blocking scheme
The logic for trip signal in permissive scheme is shown in figure 516.
PLTR-CRD
0-tCoord TRIP
CR AND 0
en05000513_ansi.vsd
ANSI05000513 V1 EN-US
The function can be totally blocked by activating the input BLOCK. Tripping can be blocked by activating
the input BLKTR. Signal send can be blocked by activating the input BLKCS.
The logic for trip signal in permissive scheme is shown in figure 516.
PLTR-CRD
0-tCoord TRIP
CR AND 0
en05000513_ansi.vsd
ANSI05000513 V1 EN-US
The function can be totally blocked by activating the input BLOCK. Tripping can be blocked by activating
the input BLKTR. Signal send can be blocked by activating the input BLKCS.e.
In unblocking scheme, the lower dependability of a permissive scheme is overcome by using the loss
of guard signal from the communication equipment to locally create a receive signal. It is common or
suitable to use the function when older, less reliable power-line carrier (PLC) communication is used.
The received signal created by the unblocking function is reset 150 ms after the security timer has
elapsed. When that occurs an output signal LCG is activated for signalling purpose. The unblocking
function is reset 200 ms after that the guard signal is present again.
CR
CRL
0-tSecurity OR
0
CRG_GUARD
200 ms 150 ms AND
0 AND OR
0
LCG
ANSI05000746-2-en.vsd
ANSI05000746 V2 EN-US
Figure 518: Guard signal logic with unblocking scheme and with setting Unblock = Restart
CR
CRL
OR
CR_GUARD 0-tSecurity
0
ANSI11000253-2-en.vsd
ANSI11000253 V2 EN-US
Figure 519: Guard signal logic with unblocking scheme and with setting Unblock = NoRestart
The unblocking function can be set in three operation modes (setting Unblock):
In the direct intertrip scheme, the send signal CS is sent from an underreaching zone that is tripping the
line.
The received signal CR is directly transferred to a trip for tripping without local criteria. The signal is
further processed in the tripping logic.
The simplified logic diagram for the complete logic is shown in figure 520.
Unblock = Off
CR
Unblock =
NoRestart OR CRL
AND
Unblock =
Restart
LCG
AND
200ms AND 150ms
OR
0 0
SchemeType =
Intertrip
CSUR
tSendMin AND
OR
BLOCK AND
CS_STOP
CRL
Schemetype =
Permissive UR AND CS
OR
AND TRIP
OR 0-tCoord 0
PLTR_CRD 25ms
0
Schemetype =
Permissive OR
CSOR OR AND
AND
tSendMin
OR
AND
SchemeType =
Blocking
BLKCS
AND
En05000515_ansi.vsd
ANSI05000515 V2 EN-US
Figure 520: Scheme communication logic for distance or overcurrent protection, simplified logic diagram
17.2.2 Identification
SEMOD141699-2 v3
Communication between line ends is used to achieve fault clearance for all faults on a power
line. All possible types of communication schemes for example, permissive underreach, permissive
overreach and blocking schemes are available. To manage problems with simultaneous faults on
parallel power lines phase segregated communication is needed. This will then replace the standard
Scheme communication logic for distance or Overcurrent protection (ZCPSCH, 85) on important lines
where three communication channels (in each subsystem) are available for the distance protection
communication.
The main purpose of the Phase segregated scheme communication logic for distance protection
(ZPCPSCH, 85) function is to supplement the distance protection function such that:
• fast clearance of faults is also achieved at the line end for which the faults are on the part of the line
not covered by its underreaching zone.
• correct phase selection can be maintained to support single-pole tripping for faults occurring anywhere
on the entire length of a double circuit line.
To accomplish this, three separate communication channels, that is, one per phase, each capable of
transmitting a signal in each direction is required.
ZPCPSCH (85) can be completed with the current reversal and WEI logic for phase segregated
communication, when found necessary in Blocking and Permissive overreaching schemes.
ZPCPSCH (85)
BLOCK TRIP
BLKTR TR_A
BLKTRL1 TR_B
BLKTRL2 TR_C
BLKTRL3 CS_A
CACCL1 CS_B
CACCL2 CS_C
CACCL3 CSMPH
CSUR_A CRL_A
CSUR_B CRL_B
CSUR_C CRL_C
CSOR_A
CSOR_B
CSOR_C
CSSTOP_A
CSSTOP_B
CSSTOP_C
BLKCS_A
BLKCS_B
BLKCS_C
CR_A
CR_B
CR_C
CRMPH
ANSI06000427 V3 EN-US
17.2.5 Signals
PID-7669-INPUTSIGNALS v1
17.2.6 Settings
PID-7669-SETTINGS v1
A permissive scheme is inherently faster and has better security against false tripping than a blocking
scheme. On the other hand, a permissive scheme depends on a received signal for a fast trip, so its
dependability is lower than that of a blocking scheme.
The Phase segregated scheme communication logic for distance protection (ZPCPSCH ,85) function is
a logical function built-up from logical elements. It is a supplementary function to the distance protection,
requiring for its operation inputs from the distance protection and the communication equipment.
The type of communication-aided scheme to be used can be selected by way of the settings.
The ability to select which distance protection zone is assigned to which input of ZPCPSCH (85) makes
this logic able to support practically any scheme communication requirements regardless of their basic
operating principle. The outputs to initiate tripping and sending of the teleprotection signal are given in
accordance with the type of communication-aided scheme selected and the zone(s) and phase(s) of the
distance protection which have operated.
When power line carrier communication channels are used for permissive schemes communication,
unblocking logic which uses the loss of guard signal as a receive criteria is provided. This logic
compensates for the lack of dependability due to the transmission of the command signal over the
faulted line.
The principle of operation for a blocking scheme is that an overreaching zone is allowed to trip
instantaneously after the settable co-ordination time tCoord has elapsed, when no signal is received
from the remote IED. The received signal (sent by a reverse looking element in the remote IED),
which shall be connected to CRLx, is used to not release the zone to be accelerated to clear the fault
instantaneously (after time tCoord). The overreaching zone to be accelerated is connected to the input
CACCLx, see figure 522. In case of external faults, the blocking signal (CRLx) must be received before
the settable timer tCoord elapses, to prevent an unneccesary trip, see figure 522.
ZPCPSCH (85) can be totally blocked by activating the input BLOCK, block of trip is achieved by
activating the input BLKTRLx, Block of carrier send is done by activating the input BLKCSLx.
CACCLx
0 - tCoord 0 TRLx
CRLx AND
0 25 ms
ANSI06000310_2_en.vsd
ANSI06000310 V2 EN-US
Figure 522: Basic logic for trip carrier in one phase of a blocking scheme
In a permissive underreach scheme, a forward directed underreach measuring element (normally zone1)
sends a permissive signal CSLx to the remote end if a fault is detected in forward direction. The received
signal CRLx is used to allow an overreaching zone (connected to CACCLx) to trip after the tCoord timer
has elapsed. The tCoord is in permissive underreach schemes normally set to zero. The logic for trip
carrier in permissive scheme is shown in figure 523. Three channels for communication in each direction
must be available.
CACCLx
0-tCoord 0 TRLx
CRLx AND
0 25 ms
ANSI07000088_2_en.vsd
ANSI07000088 V2 EN-US
Figure 523: Basic logic for trip carrier in one phase of a permissive underreach scheme
In a permissive overreach scheme, a forward directed overreach measuring element (normally zone2)
sends a permissive signal CSLx to the remote end if a fault is detected in forward direction. The received
signal CRLx is used to allow an overreaching zone to trip after the settable tCoord timer has elapsed.
The tCoord is in permissive overreach schemes normally set to zero. The logic for trip carrier is the
same as for permissive underreach, see figure 522.
The permissive overreach scheme has the same blocking possibilities as mentioned for blocking
scheme above. The blocking inputs are activated from the current reversal logic when this function
is included.
In an unblocking scheme, the lower dependability in permissive scheme is overcome by using the loss
of guard signal from the communication equipment to locally create a carrier receive signal. It is common
or suitable to use the function when older, less reliable, power-line carrier (PLC) communication is
used. As phase segregated communication schemes uses phases individually and the PLC is typically
connected single-phase or phase-to-phase it is not possible to evaluate which of the phases to release
and the unblocking scheme has thus not been supported.
In the direct intertrip scheme, the carrier send signal CS is sent from an underreaching zone that is
tripping the line.
The received signal per phase is directly transferred to the trip function block for tripping without local
criteria. The signal is not further processed in the phase segregated communication logic. In case of
single-pole tripping the phase selection and logic for tripping the three phases is performed in the trip
function block.
The simplified logic diagram for one phase is shown in figure 524.
SchemeType =
Intertrip
CSURLx
tSendMin AND
OR
BLOCK
AND
CSBLKLx OR
CRLx
Scheme Type =
Permissive UR AND CSLx
OR
AND
OR
0-tCoord TRLx
CACCLx 25
Scheme Type =
Permissive OR
CSORLx OR AND
AND
tSendMin
OR
AND
Scheme Type =
Blocking
BLKCSx
AND
CSL1
CSL2 AND
CSL2
OR CSMPH
CSL3 AND
CSL3
CSL1 AND
CSL1
CSL2 GENERAL
OR
CSL3
ANSI06000311_2_en.vsd
ANSI06000311 V2 EN-US
17.3.2 Identification
M15073-1 v5
The ZCRWPSCH function provides the current reversal and weak end infeed logic functions that
supplement the standard scheme communication logic. It is not suitable for standalone use as it requires
inputs from the distance protection functions and the scheme communications function included within
the terminal.
On detection of a current reversal, the current reversal logic provides an output to block the sending of
the teleprotection signal to the remote end, and to block the permissive tripping at the local end. This
blocking condition is maintained long enough to ensure that no unwanted operation will occur as a result
of the current reversal.
On verification of a weak end infeed condition, the weak end infeed logic provides an output for sending
the received teleprotection signal back to the remote sending end and other output(s) for local tripping.
For terminals equipped for single- and two-pole tripping, outputs for the faulted phase(s) are provided.
Undervoltage detectors are used to detect the faulted phase(s).
ZCRWPSCH (85)
V3P* IRVL
BLOCK TRWEI
IFWD TRWEI_A
IREV TRWEI_B
WEIBLK1 TRWEI_C
WEIBLK2 ECHO
LOVBZ
CBOPEN
CRL
ANSI06000287-2-en.vsd
ANSI06000287 V2 EN-US
17.3.5 Signals
PID-3521-INPUTSIGNALS v8
17.3.6 Settings
PID-3521-SETTINGS v8
The current reversal logic can be enabled by setting the parameter CurrRev = On. The current reversal
logic uses a reverse zone connected to the input IRV to recognize the fault on the parallel line in any of
the phases.When the reverse zone has been activated (even if only for a short time), it prevents sending
of a communication signal and tripping through the scheme communication logic after a settable time
tPickUpRev. The prevention will last for tPickUpRev + 10 ms + tDelayRev after the IREV reset. This
makes it possible for the receive signal to reset before the carrier-aided trip signal is activated due to
the current reversal by the forward directed zone. The logic diagram for current reversal is shown in
Figure 526.
IREV 0 0 0-tPickUpRev
0-tPickUpRev 10ms 0
IRVL
IFWD AND 0
0-tDelayRev
ANSI05000122-2-en.vsd
ANSI05000122 V2 EN-US
By connecting the output signal IRVL to input BLKCS in the ZCPSCH (85) function, the sending of the
signal CS from the overreaching zone connected to CSOR in ZCPSCH will be blocked. By connecting
IRVL to input BLKTR in the ZCPSCH function, the TRIP output from the ZCPSCH (85) function will be
blocked.
The function has an internal 10 ms drop-off timer which will secure that the current reversal logic will be
activated for short input signals even if the pick-up timer is set to zero.
The weak-end infeed logic (WEI) function sends back (echoes) the received signal under the condition
that no fault has been detected on the weak-end by different fault detection elements (distance
protection in forward or reverse direction).
The WEI function returns the received signal, shown in Figure 527, when:
• The setting parameter WEI is set to either Echo or Echo & Trip.
• No active signal is present on the input BLOCK.
• The functional input CRL is active for a time longer than the tPickUpWei setting. This input is usually
connected to the CRL output on the scheme communication logic ZCPSCH (85).
• The WEI function is not blocked by the active signal connected to the WEIBLK1 functional input or
to theLOVBZ functional input. The later is usually configured to the VTSZ functional output of the
fuse-failure function.
• No active signal has been present for at least 200 ms on the WEIBLK2 functional input. An OR
combination of all fault detection functions (not undervoltage) as present within the IED is usually used
for this purpose.
• The weak-end infeed logic also echoes the received permissive signal when local breaker opens.
BLOCK
WTSZ
WEIBLK1 OR
ECHO - cont.
CRL 0-tWEI 0 200ms
AND
0 50 ms 0 ECHO
AND
WEIBLKn 0
200ms
en06000324_ansi.vsd
ANSI06000324 V1 EN-US
Figure 527: Simplified logic diagram for weak-end infeed logic — Echo
When an echo function is used in both IEDs (should generally be avoided), a spurious signal can be
looped round by the echo logics. To avoid a continuous lock-up of the system, the duration of the echoed
signal is limited to 200 ms.
An undervoltage criteria is used as an additional tripping criteria, when the tripping of the local breaker is
selected, setting WEI = Echo&Trip. With this setting the Echo and Trip are working in parallel as in logic
shown in Figure 528.
BLOCK
VTSZ
WEIBLK1 OR
tPickUpWEI
CRL AND 50 ms 200 ms
t AND ECHO
OR t t AND
200 ms
WEIBLK2
t
AND
1500 ms
OR
CBOPEN
t
AND
V3P*
VA<VPN<
VB < VPN<
VC < VPN<
VPN< 100 ms
OR
AND t
TRWEI
OR
15 ms
TRWEI_A
V3P*
AND t
VAB <VPP< OR
VBC < VPP<
VCA < VPP<
15 ms
VPP< TRWEI_B
AND t
OR
15 ms
OR TRWEI_C
AND t
ANSI00000551-1-en.vsd
ANSI00000551-TIFF V1 EN-US
Figure 528: Simplified logic diagram for weak-end infeed logic — Echo&Trip
17.4.2 Identification
SEMOD156467-2 v3
Current reversal and weak-end infeed logic for phase segregated communication (ZPCWPSCH, 85)
function is used to prevent unwanted operations due to current reversal when using permissive
overreach protection schemes in application with parallel lines where the overreach from the two ends
overlaps on the parallel line.
The weak-end infeed logic is used in cases where the apparent power behind the protection can be
too low to activate the distance protection function. When activated, received carrier signal together
with local undervoltage criteria and no reverse zone operation gives an instantaneous trip. The received
signal is also echoed back to accelerate the sending end.
ZPCWPSCH (85)
V3P* TRPWEI
BLOCK TRPWEI_A
BLKZ TRPWEI_B
CBOPEN TRPWEI_C
CR IRVOP
CR_A IRVOP_A
CR_B IRVOP_B
CR_C IRVOP_C
IRV_A ECHO
IRV_B ECHO_A
IRV_C ECHO_B
IRVBLK_A ECHO_C
IRVBLK_B
IRVBLK_C
WEIBLK
WEIBLK_A
WEIBLK_B
WEIBLK_C
WEIBLKOP
WEIBLKO1
WEIBLKO2
WEIBLKO3
ANSI06000477 V3 EN-US
17.4.5 Signals
PID-7876-INPUTSIGNALS v1
PID-7876-OUTPUTSIGNALS v1
17.4.6 Settings
PID-7876-SETTINGS v1
The current reversal logic can be enabled by setting the parameter OperCurrRev = On. The current
reversal logic uses a reverse zone connected to the input IRVLx to recognize the fault on the parallel
line in any of the phases. When the reverse zone has been activated (even if only for a short time), it
prevents sending of a communication signal and tripping through the scheme communication logic after
a settable time tPickUpRev. The prevention will last for tPickUpRev + 10 ms + tDelayRev after the IRVLx
reset. This makes it possible for the receive signal to reset before the trip signal is activated due to the
current reversal by the forward directed zone. The logic diagram for current reversal is shown in Figure
530.
BLOCK
IRVBLKLx
tDelayRev
tPickUpRev 10 ms tPickUpRev IRVOPLx
IRVLx & t
t t t
operCurrRev=On
IEC06000474-3-en.vsd
IEC06000474 V3 EN-US
By connecting the IRVOPLx signal to input BLKCSLx in the ZPCPSCH (85) function, the sending carrier
send signal CSLx in ZPCPSCH is blocked. By connecting the IRVOPLx signal to input BLKTRLx in
ZPCPSCH, the TRIPLx output in ZPCPSCH is blocked.
The Current reversal and weak-end infeed logic for phase segregated communication (ZPCWPSCH ,85)
function has an internal 10 ms drop-off timer which secure that the current reversal logic will be activated
for short input signals even if the pickup timer is set to zero.
The WEI function sends back (echoes) the received carrier signal under the condition that no fault has
been detected at the weak end by different fault detection elements (distance protection in forward and
reverse direction).
VTSZ
BLOCK OR
ECHOLn - cont.
CRLLn 0-tWEI 0 200ms
AND
0 50ms 0 ECHOLn
AND
WEIBLK1 0
200ms
WEIBLK2 0
200ms
en07000085_ansi.vsd
ANSI07000085 V1 EN-US
The WEI function returns the received carrier signal, shown in Figure 531, when:
When an echo function is used in both the IEDs on the protected line (should generally be avoided), a
spurious signal can be looped round by the echo logics. To avoid a continuous lock-up of the system, the
duration of the echoed signal is limited to 200 ms.
An undervoltage criteria is used as an additional tripping criteria when the tripping of the local breaker
is selected. Setting OperationWEI = Echo &Trip together with the WEI function and ECHOLx, trip signal
TRPWEIx has been issued by the echo and trip logic which is described in Figure 532.
WEI = Echo&Trip
ECHOLn - cont.
CBOPEN
STUL1N
OR TRWEI
STUL2N AND 100ms OR
0
STUL3N TRWEIL1
AND 0
15ms
TRWEIL2
AND 0
15ms
TRWEIL3
AND 0
15ms
en00000551_ansi.vsd
ANSI00000551 V1 EN-US
Figure 532: Simplified logic diagram for weak-end infeed logic – Echo & Trip
It is strongly recommended to not connect any start signals from impedance protection
or directional overcurrent protection functions to WEIBLK and WEIBLKOP inputs in
ZPCWPSCH function to block the echo signal, if local protection functions operate for faults
at the weak end.
Start signals can be connected to WEIBLKLx and WEIBLKOx via OR gate to achieve the blocking of
echo signal in case if the faults are detected by local protection functions and thereby, avoiding the
operation from the remote end. By this, 3-pole operation can be accomplished in addition to 1-pole
and 2-pole operations by ZPCWPSCH function. Also, if a 3-pole operation needs to be achieved by a
separate protection function, current reversal and weak-end infeed logic for distance protection 3-phase
ZCRWPSCH function can be used. Figure 533 and Figure 534 shows the connection of start signals
from ZMFCPDIS function to WEIBLKLx and WEIBLKOx in ACT configuration to block echo signal.
ZMFCPDIS(21;Z<)
I3P I3P TRIP
U3P U3P TRZ1
INP TRL1Z1
BLOCK TRL2Z1
VTSZ TRL3Z1
BLKZ1 TRZ2
BLKZ2 TRL1Z2
BLKZ3 TRL2Z2
BLKZ4 TRL3Z2
BLKZ5 TRZ3
BLKZRV TRZ4
BLKZBU TRZ5 ZPCWPSCH(85)
BLKTRZ1 TRZRV
BLKTRZ2 TRZBU U3P U3P TRPWEI
BLKTRZ3 START ZMFCPDIS_START BLOCK TRPWEIL1
BLKTRZ4 STZ1 OR BLKZ TRPWEIL2
BLKTRZ5 STNDZ1 CBOPEN TRPWEIL3
BLKTRZRV STZ2 ZMFCPDIS_START INPUT1 OUT CR IRVOP
BLKTRZBU STL1Z2 ZMFCPDIS_STFWL1 INPUT2 NOUT CRL1 IRVOPL1
BLKTD STL2Z2 O:2403|T:3|I:26 CRL2 IRVOPL2
EXTNST STL3Z2 CRL3 IRVOPL3
ORCND STNDZ2 IRVL1 ECHO ZPCWPSCH_ECHO
RELCNDZ1 STZ3 IRVL2 ECHOL1 ZPCWPSCH_ECHOL1
RELCNDZ2 STNDZ3 IRVL3 ECHOL2 ZPCWPSCH_ECHOL2
RELCNDZ3 STZ4 IRVBLKL1 ECHOL3 ZPCWPSCH_ECHOL3
RELCNDZ4 STNDZ4 IRVBLKL2
RELCNDZ5 STZ5 IRVBLKL3
RELCNDZRV STNDZ5 OR WEIBLK
RELCNDZBU STZRV WEIBLKL1
STL1ZRV ZMFCPDIS_START INPUT1 OUT WEIBLKL2
STL2ZRV ZMFCPDIS_STFWL2 INPUT2 NOUT WEIBLKL3
STL3ZRV O:2400|T:3|I:25 WEIBLKOP
STNDZRV WEIBLKO1
STZBU WEIBLKO2
STNDZBU WEIBLKO3
STND O:3815|T:3|I:1
STNDL1
STNDL2
STNDL3 OR
STNDPE
STFWL1 ZMFCPDIS_STFWL1 ZMFCPDIS_START INPUT1 OUT
STFWL2 ZMFCPDIS_STFWL2 ZMFCPDIS_STFWL3 INPUT2 NOUT
STFWL3 ZMFCPDIS_STFWL3 O:2406|T:3|I:27
STFWPE
STRVL1
STRVL2
STRVL3
STRVPE
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
STTDFWL1
STTDFWL2
STTDFWL3
STTDRVL1
STTDRVL2
STTDRVL3
O:2095|T:3|I:1
IEC18000012 V2 EN-US
ZMFCPDIS(21;Z<)
I3P I3P TRIP
U3P U3P TRZ1
INP TRL1Z1
BLOCK TRL2Z1
VTSZ TRL3Z1
BLKZ1 TRZ2
BLKZ2 TRL1Z2
BLKZ3 TRL2Z2
BLKZ4 TRL3Z2
BLKZ5 TRZ3
BLKZRV TRZ4 ZPCWPSCH(85)
BLKZBU TRZ5
BLKTRZ1 TRZRV U3P U3P TRPWEI
BLKTRZ2 TRZBU BLOCK TRPWEIL1
BLKTRZ3 START ZMFCPDIS_START BLKZ TRPWEIL2
BLKTRZ4 STZ1 CBOPEN TRPWEIL3
BLKTRZ5 STNDZ1 CR IRVOP
BLKTRZRV STZ2 CRL1 IRVOPL1
BLKTRZBU STL1Z2 CRL2 IRVOPL2
BLKTD STL2Z2 OR CRL3 IRVOPL3
EXTNST STL3Z2 IRVL1 ECHO ZPCWPSCH_ECHO
ORCND STNDZ2 ZMFCPDIS_START INPUT1 OUT IRVL2 ECHOL1 ZPCWPSCH_ECHOL1
RELCNDZ1 STZ3 ZMFCPDIS_STFWL1 INPUT2 NOUT IRVL3 ECHOL2 ZPCWPSCH_ECHOL2
RELCNDZ2 STNDZ3 O:3000|T:3|I:29 IRVBLKL1 ECHOL3 ZPCWPSCH_ECHOL3
RELCNDZ3 STZ4 IRVBLKL2
RELCNDZ4 STNDZ4 IRVBLKL3
RELCNDZ5 STZ5 WEIBLK
RELCNDZRV STNDZ5 WEIBLKL1
RELCNDZBU STZRV WEIBLKL2
STL1ZRV WEIBLKL3
STL2ZRV OR WEIBLKOP
STL3ZRV WEIBLKO1
STNDZRV ZMFCPDIS_START INPUT1 OUT WEIBLKO2
STZBU ZMFCPDIS_STFWL2 INPUT2 NOUT WEIBLKO3
STNDZBU O:3003|T:3|I:30 O:3816|T:3|I:2
STND
STNDL1
STNDL2
STNDL3
STNDPE
STFWL1 ZMFCPDIS_STFWL1
STFWL2 ZMFCPDIS_STFWL2 OR
STFWL3 ZMFCPDIS_STFWL3
STFWPE ZMFCPDIS_START INPUT1 OUT
STRVL1 ZMFCPDIS_STFWL3 INPUT2 NOUT
STRVL2 O:3006|T:3|I:31
STRVL3
STRVPE
STFW1PH
STFW2PH
STFW3PH
STPE
STPP
STTDFWL1
STTDFWL2
STTDFWL3
STTDRVL1
STTDRVL2
STTDRVL3
O:2095|T:3|I:1
IEC18000013 V2 EN-US
17.5.1 Identification
M14860-1 v4
To achieve fast clearing of faults on the whole line, when no communication channel is available, local
acceleration logic (ZCLCPSCH) can be used. This logic enables fast fault clearing and re-closing during
certain conditions, but naturally, it can not fully replace a communication channel.
The logic can be controlled either by the autorecloser (zone extension) or by the loss-of-load current
(loss-of-load acceleration).
ZCLCPSCH
I3P* TRZE
BLOCK TRLL
ARREADY
NDST
EXACC
BC
LLACC
IEC13000307-1-en.vsd
IEC13000307 V1 EN-US
17.5.4 Signals
PID-3511-INPUTSIGNALS v6
17.5.5 Settings
PID-3511-SETTINGS v7
When the auto-recloser controls the function, a signal auto-recloser ready (ZCLCARREADY) allows an
overreaching zone (ZCLC-EXACC) to trip instantaneously, see figure 536.
The ZCLC-ARREADY functional input should be configured to READY output of auto-reclosing function.
IEC05000157 V1 EN-US
The function provides instantaneous trip (TRZE) if the ARREADY and EXACC inputs are set. After that,
the autorecloser initiates the close command and remains in the reclaim state and therefore ARREADY
signal will be low. This will block the TRZE output. If a non-direction start is picked up after reclosing, the
TRZE is blocked and therefore the fault clearance is as per the step-time distance protection.
In case of a fault on the adjacent line within the overreaching zone range, an unwanted autoreclosing
cycle will occur due to the zone extension functionality.
On the other hand, if the fault is a persistent line fault on the line section and not covered by
instantaneous zone (normally zone 1), then a trip after reclosing will be with the step-time distance
function (which is time delayed) and only the first trip (before reclosing) will be "instantaneous" .
The function will be blocked if the input BLOCK is activated (common with loss-of-load acceleration).
The local acceleration logic uses the loss-of-load condition to accelerate the trip for faults that were not
detected in an instantaneous zone (normally zone 1). If there is a fault in the range of over reaching
zone but still in the same line section, then the distance protection in the remote operates in the
instantaneous zone and the remote breaker opens in all three phases. Due to this, the load current
in the healthy phases will be discontinued, however, the current continues to flow in the fault phases.
Hence, this scenario is used to detect that the fault is inside the line section and then LLACC is released
for TRLL.
When the "acceleration" is controlled by a loss-of-load, the overreaching zone used for "acceleration"
connected to input LLACC is not allowed to trip "instantaneously" during normal non-fault system
conditions. When all three-phase currents have been above the set value MinCurr for more than setting
tLowCurr, an overreaching zone will be allowed to trip "instantaneously" during a fault condition when
one or two of the phase currents will become low due to a three-phase trip at the opposite IED, see
figure 537. The current measurement is performed internally and the internal STILL signal becomes
logical one under the described conditions. The load current in a healthy phase is in this way used to
indicate the tripping at the opposite IED. Note that this function will not trip in case of three-phase faults,
because none of the phase currents will be low when the opposite IED is tripped.
BLOCK
BC OR
I_PHA
a overPhase1
a>b
LoadCurr b
tLoadOn tLoadOff
a
a > b overPhase2 AND t t
b
a
a>b
b overPhase3
tLoadOn
AND TRLL
AND t
OR
a
a < b underPhase1
MinCurr b
tLowCurr
I_PHB
a AND t
a < b underPhase2 OR
b
I_PHC
a
a<b
b underPhase3
LLACC
ANSI05000158-2-en.vsdx
ANSI05000158 V2 EN-US
Breaker closing signals can if decided be connected to block the function during normal closing.
M13819-14 v2
17.6.2 Identification
M14882-1 v2
To achieve fast fault clearance of ground faults on the part of the line not covered by the instantaneous
step of the residual overcurrent protection, the directional residual overcurrent protection can be
supported with a logic that uses communication channels.
In the directional scheme, information of the fault current direction must be transmitted to the other line
end. With directional comparison, a short trip time of the protection including a channel transmission
time, can be achieved. This short trip time enables rapid autoreclosing function after the fault clearance.
The communication logic module for directional residual current protection enables blocking as well as
permissive under/overreaching, and unblocking schemes. The logic can also be supported by additional
logic for weak-end infeed and current reversal, included in Current reversal and weak-end infeed logic
for residual overcurrent protection (ECRWPSCH (85)) function.
ECPSCH (85)
BLOCK TRIP
BLKTR CS
BLKCS CRL
CS_STOP LCG
PLTR_CRD
CSOR
CSUR
CR
CR_GUARD
ANSI06000288-1-en.vsd
ANSI06000288 V1 EN-US
17.6.5 Signals
PID-3581-INPUTSIGNALS v7
PID-3581-OUTPUTSIGNALS v6
17.6.6 Settings
PID-3581-SETTINGS v6
• Input signal PLTR_CRD is used for tripping of the communication scheme, normally the pickup signal
of a forward overreaching step of STFW.
• Input signal CS_STOP is used for sending block signal in the blocking communication scheme,
normally thepickup signal of a reverse overreaching step of STRV.
• Input signal CSUR is used for sending permissive signal in the underreaching permissive
communication scheme, normally the pickup signal of a forward underreaching step of STINn, where n
corresponds to the underreaching step.
• Input signal CSOR is used for sending permissive signal in the overreaching permissive
communication scheme, normally the pickup signal of a forward overreaching step of STINn, where n
corresponds to the overreaching step.
In addition to this a signal from the autoreclosing function should be configured to the BLKCS input for
blocking of the function at a single phase reclosing cycle.
In the blocking scheme a signal is sent to the other line end if the directional element detects a ground
fault in the reverse direction. When the forward directional element operates, it trips after a short time
delay if no blocking signal is received from the opposite line end. The time delay, normally 30 – 40 ms,
depends on the communication transmission time and a chosen safety margin.
One advantage of the blocking scheme is that only one channel (carrier frequency) is needed if the
ratio of source impedances at both end is approximately equal for zero and positive sequence source
impedances, the channel can be shared with the impedance measuring system, if that system also
works in the blocking mode. The communication signal is transmitted on a healthy line and no signal
attenuation will occur due to the fault.
Blocking schemes are particular favorable for three-terminal applications if there is no zero-sequence
outfeed from the tapping. The blocking scheme is immune to current reversals because the received
signal is maintained long enough to avoid unwanted operation due to current reversal. There is never
any need for weak-end infeed logic, because the strong end trips for an internal fault when no blocking
signal is received from the weak end. The fault clearing time is however generally longer for a blocking
scheme than for a permissive scheme.
If the fault is on the line, the forward direction measuring element operates. If no blocking signal comes
from the other line end via the CR binary input (received signal) the TRIP output is activated after the
tCoord set time delay.
AND
CS
CS_STOP
BLOCK
TRIP
AND 0-tCoord 0
0 25ms
PLTR_CRD
CR 0
50ms
CRL
AND
ANSI05000448-1-en.vsd
ANSI05000448 V1 EN-US
In the permissive scheme the forward directed ground-fault measuring element sends a permissive
signal to the other end, if a ground fault is detected in the forward direction. The directional element at
the other line end must wait for a permissive signal before activating a trip signal. Independent channels
must be available for the communication in each direction.
An impedance measuring IED, which works in the same type of permissive mode, with one channel
in each direction, can share the channels with the communication scheme for residual overcurrent
protection. If the impedance measuring IED works in the permissive overreaching mode, common
channels can be used in single line applications. In case of double lines connected to a common bus
at both ends, use common channels only if the ratio Z1S/Z0S (positive through zero-sequence source
impedance) is about equal at both ends. If the ratio is different, the impedance measuring and the
directional ground-fault current system of the healthy line may detect a fault in different directions, which
could result in unwanted tripping.
Common channels cannot be used when the weak-end infeed function is used in the distance or
ground-fault protection.
In case of an internal ground-fault, the forward directed measuring element operates and sends a
permissive signal to the remote end via the CS output (sent signal). Local tripping is permitted when
the forward direction measuring element operates and a permissive signal is received via the CR binary
input (received signal).
The permissive scheme can be of either underreaching or overreaching type. In the underreaching
alternative, an underreaching directional residual overcurrent measurement element will be used as
sending criterion of the permissive input signal CSUR.
BLOCK
CRL
CR AND
0 TRIP
0-tCoord 25ms
PLTR_CRD AND AND
0
0
50ms
AND
BLKCS OR CS
AND
Overreach
CSOR AND
OR 25ms
CSUR
0
ANSI05000280
ANSI05000280 V2 EN-US
In unblocking scheme, the lower dependability in permissive scheme is overcome by using the loss
of guard signal from the communication equipment to locally create a receive signal. It is common or
suitable to use the function when older, less reliable, power line carrier (PLC) communication is used.
The unblocking function uses a guard signal CR_GUARD, which must always be present, even when no
CR signal is received. The absence of the CR_GUARD signal for a time longer than the setting tSecurity
time is used as a CR signal, see figure 540. This also enables a permissive scheme to trip when the line
fault blocks the signal transmission.
The received signal created by the unblocking function is reset 150 ms after the security timer has
elapsed. When that occurs an output signal LCG is activated for signaling purpose. The unblocking
function is reset 200 ms after that the guard signal is present again.
CR
CRL
0-tSecurity OR
0
CRG_GUARD
200 ms 150 ms AND
0 AND OR
0
LCG
ANSI05000746-2-en.vsd
ANSI05000746 V2 EN-US
The unblocking function can be set in three operation modes (setting Unblock):
17.7.1 Identification
M14883-1 v2
17.7.2 Functionality
M13928-3 v8
The Current reversal and weak-end infeed logic for residual overcurrent protection (ECRWPSCH (85)) is
a supplement to Scheme communication logic for residual overcurrent protection ECPSCH (85).
To achieve fast fault clearing for all ground faults on the line, the directional ground fault protection
function can be supported with logic that uses tele-protection channels.
This is why the IEDs have available additions to the scheme communication logic.
M13928-6 v2
If parallel lines are connected to common busbars at both terminals, overreaching permissive
communication schemes can trip unselectively due to fault current reversal. This unwanted tripping
affects the healthy line when a fault is cleared on the other line. This lack of security can result in a total
loss of interconnection between the two buses. To avoid this type of disturbance, a fault current reversal
logic (transient blocking logic) can be used.
M13928-8 v5
Permissive communication schemes for residual overcurrent protection can basically trip only when
the protection in the remote IED can detect the fault. The detection requires a sufficient minimum
residual fault current, out from this IED. The fault current can be too low due to an opened breaker or
high-positive and/or zero-sequence source impedance behind this IED. To overcome these conditions,
weak-end infeed (WEI) echo logic is used. The weak-end infeed echo is limited to 200 ms to avoid
channel lockup.
ECRWPSCH (85)
V3P* IRVL
BLOCK TRWEI
IFWD ECHO
IREV
WEIBLK1
WEIBLK2
LOVBZ
CBOPEN
CRL
ANSI06000289-3-en.vsdx
ANSI06000289 V3 EN-US
17.7.4 Signals
PID-3522-INPUTSIGNALS v9
PID-3522-OUTPUTSIGNALS v8
17.7.5 Settings
PID-3522-SETTINGS v9
The directional comparison function contains logic for blocking overreaching and permissive
overreaching schemes.
The circuits for the permissive overreaching scheme contain logic for current reversal and weak-end
infeed functions. These functions are not required for the blocking overreaching scheme.
Use the independent or inverse time functions in the directional ground fault protection module to
get backup tripping in case the communication equipment malfunctions and prevents operation of the
directional comparison logic.
Connect the necessary signal from the autorecloser for blocking of the directional comparison scheme,
during a single-phase autoreclosing cycle, to the BLOCK input of the directional comparison module.
The fault current reversal logic uses a reverse directed element, connected to the input signal IREV,
which recognizes that the fault is in reverse direction. When the reverse direction element is activated
the output signal IRVL is activated which is shown in Figure 542. The logic is now ready to handle a
current reversal without tripping. The output signal IRVL will be connected to the block input on the
permissive overreaching scheme.
When the fault current is reversed on the healthy line, IRV is deactivated and IRVBLK is activated.
The tDelayRev timer delays the reset of the output signal. The signal blocks operation of the overreach
permissive scheme for residual current and thus prevents unwanted operation caused by fault current
reversal.
BLOCK
IREV 0 0 tPickUpRev 0 IRVL
tPickUpRev 10ms 0 AND tDelayRev
IRWD
CurrRev = On
ANSI09000031-2-en.vsd
ANSI09000031 V2 EN-US
The weak-end infeed function can be set to send only an echo signal (WEI=Echo) or an echo signal and
a trip signal (WEI=Echo & Trip). The corresponding logic diagrams are depicted in Figure 543 and Figure
544.
The weak-end infeed logic uses normally a reverse and a forward direction element, connected to
WEIBLK2 via an OR-gate. If neither the forward nor the reverse directional measuring element is
activated during the last 200 ms, the weak-end infeed logic echoes back the received permissive signal
as shown in Figure 543 and Figure 544. The weak-end infeed logic also echoes the received permissive
signal when CBOPEN is high (local breaker opens) prior to faults appeared at the end of line.
If the forward or the reverse directional measuring element is activated during the last 200 ms, the fault
current is sufficient for the IED to detect the fault with the ground fault function that is in operation.
BLOCK
ANSI09000032-2-en.vsd
ANSI09000032 V2 EN-US
Figure 543: Simplified logic diagram for weak-end infeed logic - Echo
With the WEI= Echo & Trip setting, the logic sends an echo according to the diagram above. Further,
it activates the TRWEI signal to trip the breaker if the echo conditions are fulfilled and the neutral point
voltage is above the set trip value for 3V0PU .
The voltage signal that is used to calculate the zero sequence voltage is set in the ground fault function
which is in operation.
BLOCK
WEIBLK1 0 AND
ECHO
200 ms AND 0 200 ms
CRL 50 ms 0
TRWEI
WEI = Echo&Trip AND
100 ms
3V0PU
AND
CBOPEN
ANSI09000020-2-en.vsd
ANSI09000020 V2 EN-US
Figure 544: Simplified logic diagram for weak-end infeed logic - Echo & Trip
The weak-end infeed echo sent to the strong line end has a maximum duration of 200 ms. When this
time period has elapsed, the conditions that enable the echo signal to be sent are set to zero for a time
period of 50 ms. This avoids ringing action if the weak-end echo is selected for both line ends.
Direct transfer trip (DTT) logic is used together with Line distance protection function or other type
of line protection. One typical example for use of transfer trip is given below. When Line distance
protection function is extended to cover power lines feeding the transformer directly and there is a fault
in transformer differential area, the transformer differential protection operates faster than line protection.
A trip command is sent to the remote end of the line. On remote end, before sending a trip command to
the circuit breaker, the certainty of a fault condition is ensured by checking local criterion in DTT logic.
CR CS TRIP
TRIP
DTT IDIFF>
Xsource VT1
~ CT1
Line
CT2 CT3
Source Power Load
Transformer
en03000120.vsd
IEC03000120 V1 EN-US
On receiving the CR signal from remote end, Direct transfer trip logic needs to check additional local
criterion, before sending the trip signal to circuit breaker.
A composite scheme of these functions must be configured in PCM600 configuration tool, to make a
complete DTT scheme as shown in Figure 546. The different individual local criteria functions can also
be used as direct tripping protections, normally with a time delay.
CR!
CR2
Impedance protection
Low impedance protection
CarrierReceiveLogic
LCCRPTRC (94)
Three phase undercurrent
V3P
CR!
CB Trip output
CR2
Zero sequence overcurrent
protection
LocalCheck
Analog input
ANSI09000773-1-en.vsd
ANSI09000773 V1 EN-US
17.8.2.1 Identification
GUID-6F3FADD8-8974-4874-8A43-642C1D540D3E v1
Low active power and power factor protection (LAPPGAPC, 37_55) function measures power flow. It can
be used for protection and monitoring of:
LAPPGAPC (37_55)
I3P* TRLAP
V3P* TRLPF
BLOCK TRTPFA
BLKTR TRLPFB
TRLPFC
PU_LAP
PU_LPF
PU_LAP_A
PU_LAP_B
PU_LAP_C
PU_LPF_A
PU_LPF_B
PU_LPF_C
ANSI09000763-1-en.vsd
ANSI09000763 V1 EN-US
17.8.2.4 Signals
PID-3520-INPUTSIGNALS v6
17.8.2.5 Settings
PID-3520-SETTINGS v6
Low active power and low power factor protection (LAPPGAPC, 37_55) calculates power and power
factor from voltage and current values. Trip signal must be set independently for low active power and
low power factor condition after definite time delay.
LAPPGAPC (37_55) calculates single phase complex power of A, B and C loop by following equations.
From this complex apparent power, the real and imaginary parts can be respective active and reactive
power values of respective phases. All the apparent power values given out of the function are absolute
values. The active power is the real part of the calculated apparent power.
S A = VA ·I A
S = V ·I
B B B
SC = VC · IC
EQUATION2245-ANSI V1 EN-US (Equation 182)
Power factor is a ratio of active power to apparent power. The function calculates power factor from the
calculated values of active power and apparent power of A, B and C loop by following equation:
PA
pfA =
SA
EQUATION2246-ANSI V1 EN-US (Equation 183)
PB
pfB =
SB
EQUATION2247-ANSI V1 EN-US (Equation 184)
PC
pfC =
SC
EQUATION2248-ANSI V1 EN-US (Equation 185)
The low active power functionality has a trip mode setting. According to this setting, trip is activated if the
low active power is detected in one out of three phases or two out of three phases respectively. These
two modes are user settable through setting OpModeSel.
The function will do zero clamping to disable the calculation if the current and voltage values of a
particular phase are less than 30% of VBase for voltage and 3% of IBase for current value.
Calculation
The active power setting value used for detection of under power must be given as a three-phase value.
The design starts to calculate internally the per phase value from this setting and detect phase wise
under power condition individually. The power factor pickup value is common for all the three phases.
Phase wise analog values apparent power, active power, reactive power and power factor are available
as service values.
PU_LAP_x
P < LAP<
I3P TRLAP
t
Calculation P and
pf
V3P
PU_LPF_x
pf < pf<
TRLPFx
t
ANSI10000011-1-en.vsd
ANSI10000011 V1 EN-US
Figure 548: Logic diagram of Low active power and low power factor protection (LAPPGAPC, 37_55)
17.8.3.1 Identification
GUID-F5F76C4D-DD25-4695-9FF1-6B45C696CC5E v1
Compensated over and undervoltage protection (COUVGAPC, 59_27) function calculates the remote
end voltage of the transmission line utilizing local measured voltage, current and with the help of
transmission line parameters, that is, line resistance, reactance, capacitance and local shunt reactor. For
protection of long transmission line for in zone faults, COUVGAPC, (59_27) can be incorporated with
local criteria within direct transfer trip logic to ensure tripping of the line only under abnormal conditions.
COUVGAPC (59_27)
I3P* 27 Trip
V3P* 59 Trip
BLOCK 27_Trip_A
BLKTR 27_Trip_B
SWIPOS 27_Trip_C
59_Trip_A
59_Trip_B
59_Trip_C
27 PU
59 PU
27_PU_A
27_PU_B
27_PU_C
59_PU_A
59_PU_B
59_PU_C
ANSI09000764-1-en.vsd
ANSI09000764 V1 EN-US
17.8.3.4 Signals
PID-3480-INPUTSIGNALS v8
17.8.3.5 Settings
PID-3480-SETTINGS v8
Compensated over and undervoltage protection (COUVGAPC, 59_27) function is phase segregated
and mainly used for local criteria check in Direct transfer trip. The principle is to utilize local measured
voltage and current to calculate the voltage at the remote end of the line.
The main measured inputs to COUVGAPC (59_27) are three-phase voltage and current signals.
COUVGAPC (59_27)uses line resistance, reactance and line charging capacitance to calculate the
remote end voltage. It also takes the input for local shunt reactor, connected at the line side of the line
breaker, reactance value. The calculated voltage is referred to as compensated voltage.
59 PU
59 Trip
Over voltage
V3P 59_PU_x
comparator
I3P 59_Trip_x
t
Compensated
SWIPOS voltage calculation 27_PU_x
EnShuntReactor AND
27_Trip_x
Under voltage t
27 Trip
comparator
27 PU
ANSI09000782-1-en.vsd
ANSI09000782 V1 EN-US
Figure 550: Logic diagram of Compensated over and undervoltage protection (COUVGAPC, 59_27)
Where:
Vremote calculated voltage at the opposite side of line
Vlocal measured local voltage
Ilocal measured local current
Xsr reactance of local line connected shunt reactor, if applicable
Xcp half of equivalent reactance of line distributed capacitor
Above calculated compensated voltage is compared to preset over and under voltage levels set as
percentage of base voltage VBase. If the calculated voltage exceeds setting in any phase, COUVGAPC
(59_27) generates pickup and trip signals for that phase and common pickup and trip signals.
Independent enabling for overvoltage and undervoltage are available with definite time delay. If shunt
reactor is not present in the system, COUVGAPC (59_27) does not include any effect of shunt reactor
while calculating the compensated voltage. This shunt reactor calculation is enabled when both input
SWIPOS is and setting parameter EnShuntReactor is Enabled. Run time change in EnShuntReactor
setting parameter restarts the IED and SWIPOS input signal is used to enable/disable the shunt reactor
calculations.
Calculations
• All resistance and reactance considered in compensated voltage calculation are primary side values.
• Calculation of shunt reactor reactance in ohms from given MVAr rating:
2
VN
X sr =
QN
EQUATION2249-ANSI V1 EN-US (Equation 186)
Where:
VN line to line voltage
QN is total three phase MVAr of shunt reactor
• If total line capacitance (Ctotal) is known then half line capacitive reactance:
2
X cp =
wCtotal
EQUATION2250 V1 EN-US (Equation 187)
X cp = 2 X cTotal
EQUATION2251 V1 EN-US (Equation 188)
17.8.4.1 Identification
GUID-3B6E6472-8153-4D8F-874B-DF68891296C8 v1
Sudden change in current variation (SCCVPTOC, 51) function is a fast way of finding any abnormality
in line currents. When there is a fault in the system, the current changes faster than the voltage.
SCCVPTOC (51) finds abnormal condition based on phase-to-phase current variation. The main
application is as a local criterion to increase security when transfer trips are used.
SCCVPTOC (51)
I3P* TRIP
BLOCK RI
BLKTR
ANSI09000765-1-en.vsd
ANSI09000765 V1 EN-US
17.8.4.4 Signals
PID-3585-INPUTSIGNALS v5
17.8.4.5 Settings
PID-3585-SETTINGS v6
Sudden change in current variation (SCCVPTOC, 51) function calculates the variation in phase-to-phase
current and gives the RI output when this variation crosses the sum of start level and float threshold for a
time of tDelay. The variation is calculated for all the three phase-to-phase currents.
Di = i ( t ) - 2 × i ( t - T ) + i ( t - 2T )
EQUATION2252 V1 EN-US
Where:
i(t) Amplitude of the current at the present instant
i(t-T) Amplitude of the current at the instant exactly one cycle time before
i(t-2T) Amplitude of the current at the instant exactly two cycle time before
Criteria:
1 2T -1
DIT = å Di ( t - n )
T n =T
EQUATION2254 V1 EN-US (Equation 190)
If the above criteria becomes true for a time of tDelay, then respective RI output is activated provided
the BLOCK input is false, and the respective TRIP outputs is activated for the time of tHold provided the
BLKTR and BLOCK input is false.
17.8.5.1 Identification
GUID-D420E532-37DC-442F-B847-8F73EE8527A7 v1
In Direct transfer trip (DTT) scheme, the received CR signal gives the trip to the circuit breaker
after checking certain local criteria functions in order to increase the security of the overall tripping
functionality. Carrier receive logic (LCCRPTRC, 94) function gives final trip output of the DTT scheme.
Features:
LCCRPTRC (94)
BLOCK TRIP
LOCTR TR_A
LOCTR_A TR_B
LOCTR_B TR_C
LOCTR_C
CHERR1
CHERR2
CR!
CR2
ANSI09000766-1-en.vsd
ANSI09000766 V1 EN-US
17.8.5.4 Signals
PID-3481-INPUTSIGNALS v6
PID-3481-OUTPUTSIGNALS v6
17.8.5.5 Settings
PID-3481-SETTINGS v5
The functionality of the Carrier receive logic (LCCRPTRC, 94) is to release the TRIP signal for DTT
scheme based on the LOCTR_A, LOCTRL_B, LOCTR_C, and LOCTR signals coming from local
criterion, and the Carrier receive signals CR! and CR2. There are two modes of operation 1 out of
2 and 2 out of 2. In the case of the 1 out of 2 mode if any one of the carrier signal is received then the
trip signals will be released, and in 2 out of 2 mode both the CRs should be high to release trip signal. If
any one of the channel error signals is high in 2 out of 2 mode, then logic automatically switches to 1 out
of 2 mode after a time delay of 200 ms. After switching to 1/2 mode under channel error condition and if
channel error gets cleared the mode will switch back only after a time delay of 200 ms.
If the input channel error signal is high then the respective carrier receive signal will be blocked.
The complete function can be blocked by setting the BLOCK input high.
17.8.6.1 Identification
GUID-C0F8D64B-FBCD-4115-9A5A-23B252CB7E45 v1
Negative sequence components are present in all types of fault condition. Negative sequence voltage
and current get high values during unsymmetrical faults.
LCNSPTOV (47)
V3P* TRIP
BLOCK RI
BLKTR
ANSI09000767-1-en.vsd
ANSI09000767 V1 EN-US
17.8.6.4 Signals
PID-7429-INPUTSIGNALS v1
17.8.6.5 Settings
PID-7429-SETTINGS v1
Negative sequence over voltage protection (LCNSPTOV, 47) is a definite time stage comparator
function. The negative sequence input voltage from the SMAI block is connected as input to the function
through a group connection V3P in PCM600. This voltage is compared against the preset value and
a pickup signal will be set high if the input negative sequence voltage is greater than the preset value
Pickup2. Trip signal will be set high after a time delay setting oftV2. There is a BLOCK input which will
block the complete function. BLKTR will block the trip output. The negative sequence voltage is also
available as service value output U2.
17.8.7.1 Identification
GUID-0D2A007F-167A-4534-A41B-22C107FEAC46 v1
Zero sequence components are present in all abnormal conditions involving ground. They can reach
considerably high values during ground faults.
LCZSPTOV (59N)
V3P* TRIP
BLOCK RI
BLKTR
ANSI09000768-1-en.vsd
ANSI09000768 V1 EN-US
17.8.7.4 Signals
PID-3631-INPUTSIGNALS v6
17.8.7.5 Settings
PID-3631-SETTINGS v6
Zero sequence over voltage protection (LCZSPTOV, 59N) is a definite time stage comparator function.
The zero sequence input voltage from the SMAI block is connected as input to the function through
a group connection V3P in PCM600. This voltage is compared against the preset value and a pickup
signal will be set high if the input zero sequence voltage is greater than the preset value 3V0PU. Trip
signal will be set high after a time delay setting of t3V0. BLOCK input will block the complete function.
BLKTR will block the trip output. The zero sequence voltage will be available as service value output as
3V0.
17.8.8.1 Identification
GUID-EDC20AC7-540D-43DE-8ABF-7A463E115950 v1
Negative sequence components are present in all types of fault condition. They can reach considerably
high values during abnormal operation.
LCNSPTOC (46)
I3P* TRIP
BLOCK RI
BLKTR
ANSI09000769-1-en.vsd
ANSI09000769 V1 EN-US
17.8.8.4 Signals
PID-3617-INPUTSIGNALS v5
17.8.8.5 Settings
PID-3617-SETTINGS v6
Negative sequence overcurrent protection (LCNSPTOC, 46) is a definite time stage comparator function.
The negative sequence input current from the SMAI block is connected as input to the function through
a group connection I3P in PCM600. This current is compared against the preset value and a pickup
signal will be set high if the input negative sequence current is greater than the preset value Pickup2 .
Trip signal will be set high after a time delay setting of tI2. BLOCK input will block the complete function.
BLKTR will block the trip output. The negative sequence current is available as service value output I2.
17.8.9.1 Identification
GUID-581BA9F0-7886-4E46-84B6-37E8B6962934 v1
Zero sequence components are present in all abnormal conditions involving ground. They have a
considerably high value during ground faults.
LCZSPTOC (51N)
I3P* TRIP
BLOCK RI
BLKTR
ANSI09000770-1-en.vsd
ANSI09000770 V1 EN-US
17.8.9.4 Signals
PID-3632-INPUTSIGNALS v5
17.8.9.5 Settings
PID-3632-SETTINGS v6
Zero sequence overcurrent protection (LCZSPTOC, 51N) is a definite time stage comparator function.
The zero sequence input current from the SMAI block is connected as input to the function through a
group connection I3P in PCM600. This current is compared against the preset value and a pickup signal
will be set high if the input zero sequence current is greater than the preset value 3I0 PU. Trip signal will
be set high after a time delay setting of t3I0. BLOCK input will block the complete function. BLKTR will
block the trip output. The zero sequence current is available as service value output 3I0.
17.8.10.1 Identification
GUID-5FBC4309-C8FB-4CDF-A4D6-84E3A89C81B7 v1
Features:
LCP3PTOC (51)
I3P* TRIP
BLOCK TR_A
BLKTR TR_B
TR_C
RI
PU_A
PU_B
BFI_C
ANSI09000771-1-en.vsd
ANSI09000771 V1 EN-US
17.8.10.4 Signals
PID-3672-INPUTSIGNALS v5
17.8.10.5 Settings
PID-3672-SETTINGS v6
Three phase overcurrent (LCP3PTOC, 51) is used for detecting over current conditions. LCP3PTOC
(51) pickups when the current exceeds the set limit PU 51. It operates with definite time (DT)
characteristics, that is, the function operates after a predefined time tOC and resets when the fault
current disappears. The function contains a blocking functionality. It is possible to block the function
output, timer or the function itself, if desired.
17.8.11.1 Identification
GUID-51A4DEE2-C549-483B-9BDD-8F79AD4CFE23 v1
Three phase undercurrent function (LCP3PTUC, 37) is designed for detecting loss of load conditions.
Features:
LCP3PTUC (37)
I3P* TRIP
BLOCK TR_A
BLKTR TR_B
TR_C
RI
BFI_A
PU_B
BFI_C
ANSI09000772-1-en.vsd
ANSI09000772 V1 EN-US
17.8.11.4 Signals
PID-3673-INPUTSIGNALS v5
17.8.11.5 Settings
PID-3673-SETTINGS v6
Three phase undercurrent (LCP3PTUC, 37) is used for detecting sudden load loss which is considered
as fault condition. LCP3PTUC (37) starts when the current is less than the set limit PU_37. It operates
with definite time (DT) characteristics, that is, the function operates after a predefined time tUC and
resets when the load current restores. The function contains a blocking functionality. It is possible to
block the function output, timer or the function itself, if desired.
Section 18 Logic
18.1 Tripping logic SMPPTRC (94) IP14576-1 v5
18.1.2 Identification
SEMOD56226-2 v8
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Tripping logic SMPPTRC 1 -> 0
94
IEC15000314 V1 EN-US
A function block for protection tripping and general start indication is always provided as a basic function
for each circuit breaker. It provides a settable pulse prolongation time to ensure a trip pulse of sufficient
length, as well as all functionality necessary for correct co-operation with autoreclosing functions.
The trip function block includes a settable latch function for the trip signal and circuit breaker lockout.
The trip function can collect start and directional signals from different application functions. The
aggregated start and directional signals are mapped to the IEC 61850 logical node data model.
SMPPTRC (94)
I3P TRIP
V3P TR_A
BLOCK TR_B
BLKLKOUT TR_C
TRINALL TRN
TRINP_A TR1P
TRINP_B TR2P
TRINP_C TR3P
TRINN CLLKOUT
PS_A BFI_3P
PS_B PU_A
PS_C PU_B
1PTRZ PU_C
1PTRGF PU_N
P3PTR FW
SETLKOUT REV
RSTLKOUT FLTIAMAG
CND FLTIAANG
RSTFLTUI FLTIBMAG
FLTIBANG
FLTICMAG
FLTICANG
FLTINMAG
FLTINANG
FLTVAMAG
FLTVAANG
FLTVBMAG
FLTVBANG
FLTVCMAG
FLTVCANG
FLTVNMAG
FLTVNANG
GUID-1D93B12C-884C-4725-998C-1D3E8B4F19DB V1 EN-US
18.1.5 Signals
PID-8233-INPUTSIGNALS v1
PID-8233-OUTPUTSIGNALS v1
18.1.6 Settings
PID-8233-SETTINGS v1
There is a single input (TRINP_3P) through which all trip output signals from the protection functions
within the IED or from external protection functions via one or more of the IEDs' binary inputs are routed.
It has a three-phase trip output (TRIP) to connect to one or more of the IEDs' binary outputs, as well as
to other functions within the IED requiring this signal.
SETLKOUT
RSTLKOUT
P3PTR
SETLKOUT
RSTLKOUT
P3PTR
SETLKOUT
RSTLKOUT
ANSI10000266=2=en=Original.vsd
ANSI10000266 V2 EN-US
The input TRINN can be activated from functions which provide data for trip in the neutral.
SMPPTRC (94) function has separate inputs (TRINP_A, TRINP_B, and TRINP_C) which are used for
single-pole and two-pole tripping from the functions which offer phase segregated trip outputs.
The inputs 1PTRZ and 1PTRGF enable single-pole and two-pole tripping for those functions which do
not have their own pole selection capability (that is, which have just a single trip output). An example of
such a protection function is the residual overcurrent protection. The SMPPTRC (94) function has two
inputs for these functions, one for impedance tripping (1PTRZ used for carrier-aided tripping commands
from the scheme communication logic), and one for ground fault tripping (1PTRGF used for tripping from
a residual overcurrent protection). External pole selection for these two trip signals shall be provided via
inputs PS_A, PS_B, and PS_C.
A timer tWaitForPHS, secures a three-phase trip command for these two trip signals in the absence of
the external phase selection signals.
The SMPPTRC (94) function has three trip outputs TR_A, TR_B, TR_C (besides the three-phase trip
output TRIP), one per phase, to connect to one or more of the IEDs’ binary outputs, as well as to other
functions within the IED requiring these signals. These three output signals shall be used as trip signals
for individual circuit breaker poles. These signals are important for cooperation with the autorecloser
SMBRREC (79) function.
The outputs TRN and TRIP are activated when the input TRINN is activated.
The SMPPTRC (94) function is equipped with logic which secures correct operation for evolving faults
as well as for reclosing on to persistent faults. A binary input P3PTR is provided which will force all
tripping to be three-pole. This input is required in order to cooperate with the SMBRREC function.
In multi-breaker arrangements, one SMPPTRC (94) function block is used for each circuit breaker.
If external conditions are required to initiate a circuit breaker lockout, it can be achieved by activating
input SETLKOUT. The settingAutoLock = Disabled means that the internal three-phase trip will not
activate lockout so only initiation of the input SETLKOUT will result in lockout. This is normally the case
for overhead line protection where most faults are transient. Unsuccessful autoreclosing and back-up
zone tripping can in such cases be connected to initiate lockout by activating the input SETLKOUT.
If CLLKOUT is set by an external trip signal from another protection function, that is by activating
SETLKOUT input, or internally by a three-phase trip, that is with the setting AutoLock = Enabled and the
setting TripLockout = Enabled, then also all trip outputs are set latched.
The lockout can manually be reset after checking the primary fault by activating the reset lockout input
RSTLKOUT.
The BLKLKOUT input blocks the circuit breaker lockout output CLLKOUT.
The following three sequences in the following table shows the interaction between the inputs BLOCK,
BLKLKOUT, SETLKOUT, RSTLKOUT and the output CLLKOUT.
Inputs Output
BLOCK BLKLKOUT SETLKOUT RSTLKOUT CLLKOUT
Active - - - False
Active - Active - False
- - - - False
Table continues on next page
Inputs Output
BLOCK BLKLKOUT SETLKOUT RSTLKOUT CLLKOUT
- - Active - True
Active - - - True
Active - - Activated True
- - - - True
- Active - - False
- Active Active - False
- - - - True
- - - Activated False
Directional data
Merged directional data from application functions can be provided to the trip function (SMPPTRC) via
the start matrix function (SMAGAPC) connected to the CND input.
The directional input signal CND is a coded integer signal which contains 15 individual Boolean signals;
see Figure 566:
CNDX=[b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14]
b0= BFI_3P (general pickup)
b1= FW (forward)
b2= REV (reverse)
b3= BFI_A (pickup A)
b4= FW_A (forward A)
b5= REV_A (reverse A)
b6= BFI_B (pickup B)
b7= FW_B (forward B)
b8= REV_B (reverse B)
b9= BFI_C (pickup C)
b10= FW_C (forward C)
b11= REV_C (reverse C)
b12= BFI_N (pickup N)
b13= FW_N (forward N)
b14= REV_N (reverse N)
The indications for common start BFI_3P, and phase-wise starts BFI_A, BFI_B and BFI_C and neutral
STN and common directional forward FW and reverse REV are all available as outputs on the trip
function.
All start and directional outputs are mapped to the IEC 61850 logical node data model of the trip
function. The time stamping is updated each time a trip or pickup signal is changed:
dirGeneral
0 unknown
1 forward
2 backward (reverse)
3 both
• The phase wise directional outputs (DIR_A, DIR_B, DIR_C, and DIR_N) are mapped as:
TRIP
Instantaneous samples
FLTIL1MAG
IL1
FLTIL2MAG
IL2
FLTIL3MAG
IL3
GUID-8178BD9C-69CB-4C1C-905E-59626FD6B5ED V1 EN-US
If the signal RESET is HIGH, SMPPTRC will set all the reported current magnitudes to
-1.000A, voltage magnitudes to -0.001kV, current and voltage angles to -1.000deg values
respectively.
If the group connections of current and voltage are not connected to SMAI or the signal
quality is bad, the SMPPTRC function will set all the reported current magnitudes to -2.000A,
voltage magnitudes to -0.002kV, current and voltage angles to -2.000deg values respectively,
indicating Invalid data.
tTripMin
BLOCK TRIPALL
OR
AND t
TRINP_A
TRINP_B
TRINP_C
TRINP_3P OR
1PTRGF
1PTRZ
ANSI05000517=4=en=Original.vsd
ANSI05000517 V4 EN-US
TRINP_3P
TRINP_A
L1TRIP
OR
PS_A
AND
TRINP_B
L2TRIP
OR
PS_B
AND
TRINP_C
L3TRIP
OR
PS_C
AND
-LOOP
OR OR
OR
AND
AND
OR
tWaitForPHS
-LOOP t
OR
1PTRGF AND
AND
1PTRZ OR
ANSI10000056=4=en=Original.vsd
ANSI10000056 V4 EN-US
tTripMin
BLOCK
OR TRIPL1
L1TRIP AND t OR
tEvolvingFault
t TRIP
AND
L2TRIP
L3TRIP
OR
P3PTR
IEC17000065 V3 EN-US
Figure 564: Simplified additional logic per phase, Program = 1p/3p or 1p/2p/3p
BLKLKOUT
TRIPL1
TR_A
OR
TRIPL2
TR_B
OR
TRIPL3
TR_C
OR
TRIP
TRIPALL OR
OR
-LOOP
OR
AND
TR3P
AND
AND
AND
AND OR
OR
-LOOP
AND
-LOOP
AND
AutoLock
CLKLKOUT
OR AND
SETLKOUT OR AND
3ms
RSTLKOUT t
AND
TripLockout
-LOOP
ANSI17000066=1=en=Original.vsd
ANSI17000066 V1 EN-US
IntToBits
CND
in b0 BFI_3P BFI_3P
FW BFI_A
b1
REV BFI_B
b2
BFI_A BFI_C
b3
FW_A
b4
REV_A FW
b5
BFI_B dirGeneral (61850
b6
FW_B BitsToInt Standard)
b7
REV_B 0 = unknown
b8 b0 out DIR
BFI_C 1 = forward
b9 b1
FW_C 2 = backward (reverse)
b10
REV_C 3 = both
b11
REV
b0 = BFI_3P
b1 = FW
b2 = REV
BitsToInt dirPhsA (61850 Standard, phase
b3 = BFI_A
wize)
b4 = FW_A
AND b0 out DIRL1 0 = unknown
b5 = REV_A
b1 1 = forward
b6 = BFI_B
2 = backward (reverse)
b7 = FW_B
b8 = REV_B XOR
b9 = BFI_C
b10 = FW_C
b11 = REV_C AND
AND
AND
ANSI16000179=1=en=Original.vsdx
ANSI16000179 V2 EN-US
Function Description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Generat start matrix block SMAGAPC - -
The Start Matrix (SMAGAPC) merges start and directional output signals from different application
functions and creates a common start and directional output signal (STDIR) to be connected to the Trip
function, see Figure 567.
The purpose of this functionality is to provide general start and directional information for the IEC 61850
trip logic data model SMPPTRC.
SMAGAPC
BLOCK CND
PU_DIR1
PU_DIR2
PU_DIR3
PU_DIR4
PU_DIR5
PU_DIR6
PU_DIR7
PU_DIR8
PU_DIR9
PU_DIR10
PU_DIR11
PU_DIR12
PU_DIR13
PU_DIR14
PU_DIR15
PU_DIR16
ANSI16000165=1=en=Original.vsdx
ANSI16000165 V1 EN-US
18.2.4 Signals
PID-6906-INPUTSIGNALS v2
PID-6906-OUTPUTSIGNALS v2
18.2.5 Settings
PID-6906-SETTINGS v2
Start matrix
The Start Matrix function requires that a protection function delivers the directional output signals in a
fixed order to Start Matrix.
A directional input signal STDIRX of the Start Matrix is of type word. Each input contains 14 individual
Boolean signals, which are positioned as, see Figure 569.
STDIRX=[b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14]
b0= START (start)
b1= FW (forward)
b2= REV (reverse)
b3= STL1 (startL1)
b4= FWL1 (forwardL1)
b5= REVL1 (reverseL1)
b6= STL2 (startL2)
b7= FWL2 (forwardL2)
b8= REVL2 (reverseL2)
b9= STL3 (startL3)
b10= FWL3 (forwardL3)
b11= REVL3 (reverseL3)
b12= STN (startN)
b13= FWN (forwardN)
b14= REVN (reverseN)
The StartMatrix function contains two function: the START criteria and the DIRECTION criteria, see
Figure 568.
The START criteria is to ensure that a forward and reverse signal shall come together with a start
signal to pass through the block. This is done individually for each protection function connected to the
StartMatrix via the STDIRX inputs, see Figure 569.
All STDIROUT signals are then connected via an OR gate, see Figure 568.
The DIRECTION criteria allow either forward or reverse (phase-wise forward FWLx or forward neutral
FWN or phase-wise reverse REVLx or reverse neutral REVN) to pass through to the general STDIR
output. If both forward and reverse are active phase-wise (e.g. REVLx=FWLx = True) or at neutral (e.g.
FWN = REVN = True) at the same time, none will be shown, see Figure 570.
SMAGAPC
(StartMatrix)
START Criteria
PU_DIR1
PU_DIRX CNDOUT
START Criteria
PU_DIR2
PU_DIRX CNDOUT
START Criteria
PU_DIR3
PU_DIRX CNDOUT
DIRECTION Criteria
CND
OR CNDIN CND
START Criteria
PU_DIR4
PU_DIRX CNDOUT
START Criteria
PU_DIR5
PU_DIRX CNDOUT
START Criteria
PU_DIR6
PU_DIRX CNDOUT
START Criteria
PU_DIR7
PU_DIRX CNDOUT
START Criteria
PU_DIR8
PU_DIRX CNDOUT
START Criteria
PU_DIR9
PU_DIRX CNDOUT
START Criteria
PU_DIR10
PU_DIRX CNDOUT
START Criteria
PU_DIR11
PU_DIRX CNDOUT
START Criteria
PU_DIR12
PU_DIRX CNDOUT
START Criteria
PU_DIR13
PU_DIRX CNDOUT
START Criteria
PU_DIR14
PU_DIRX CNDOUT
START Criteria
PU_DIR15
PU_DIRX CNDOUT
START Criteria
PU_DIR16
PU_DIRX CNDOUT
ANSI16000161-2-en.vsdx
ANSI16000161 V2 EN-US
START Criteria
BFI_3P (in)
BFI_A (in)
BFI_B (in) OR BFI_3P (out)
BFI_C (in)
IntToBits STN (in) BitsToint
PU_DIRX CNDOUT
in b0 BFI_3P (in) BFI_A (out) BFI_3P (out) b0 out
b1 FW (in) BFI_B (out) FW (out) b1
b2 REV (in) BFI_C (out) REV (out) b2
b3 BFI_A (in) STN (out) BFI_A (out) b3
b4 FW_A (in) FW_A (out) b4
b5 REV_A (in) REV_A (out) b5
AND
b6 BFI_B (in) FW (in) BFI_B (out) b6
b7 FW_B (in) FW_B (out) b7
OR FW (out)
b8 REV_B (in) REV_B (out) b8
b9 BFI_C (in) BFI_C (out) b9
b10 FW_C (in) FW_C (out) b10
b11 REV_C (in) AND REV_C (out) b11
REV (in)
b12 STN (in) STN (out) b12
b13 FWN (in) OR REV (out) FWN (out) b13
b14 REVN (in) REVN (out) b14
b15 N/A FALSE b15
ANSI16000162-1-en.vsdx
ANSI16000162 V1 EN-US
DIRECTION Criteria
FW_A (in)
XOR
REV_A (in)
FW_B (in)
XOR
REV_B (in)
FW_C (in)
XOR
REV_C (in)
FWN (in)
XOR
REVN (in)
ANSI16000163-2-en.vsdx
ANSI16000163 V2 EN-US
STARTCOMB
To make it possible to provide the directional information from a protection function, a STARTCOMB
block is used in between the application function and the Start Matrix function.
The STARTCOMB function has one block input and 14 Boolean inputs that convert the 14 Boolean
inputs into a WORD output CND, see Figure 571.
STDIRX=[b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14]
b0= START (start)
b1= FW (forward)
b2= REV (reverse)
b3= STL1 (startL1)
b4= FWL1 (forwardL1)
b5= REVL1 (reverseL1)
b6= STL2 (startL2)
b7= FWL2 (forwardL2)
b8= REVL2 (reverseL2)
b9= STL3 (startL3)
b10= FWL3 (forwardL3)
b11= REVL3 (reverseL3)
b12= STN (startN)
b13= FWN (forwardN)
b14= REVN (reverseN)
STARTCOMB
BLOCK CND
BFI_3P
FW
REV
BFI_A
FW_A
REV_A
BFI_B
FW_B
REV_B
BFI_C
FW_C
REV_C
STN
FWN
REVN
ANSI16000166-2-en.vsdx
ANSI16000166 V2 EN-US
Protection functions
Some protection functions are provided with start and directional outputs, for example:
Connection example
In Figure 572 below is an example how to connect start and directional signals from protection functions
via STARTCOMB and SMAGAPC to SMPPTRC.
SMAGAPC
STARTCOMB
BLOCK CND
SMPPTRC (94)
PROTECTION 1 BLOCK CND PU_DIR1
BLOCK TRIP
BFI_3P BFI_3P PU_DIR2
BLKLKOUT TR_A
FW FW PU_DIR3
TRINP_3P TR_B
REV REV PU_DIR4
TRINP_A TR_C
BFI_A PU_DIR5
TRINP_B TR1P
FW_A PU_DIR6
REV_A TRINP_C TR2P
PU_DIR7
BFI_B PU_DIR8 PS_A TR3P
FW_B PU_DIR9 PS_B CLLKOUT
REV_B PU_DIR10 PS_C BFI_3P
BFI_C PU_DIR11 1PTRZ BFI_A
FW_C PU_DIR12 1PTRGF BFI_B
REV_C PU_DIR13 P3PTR BFI_C
STN PU_DIR14 SETLKOUT STN
FWN PU_DIR15 RSTLKOUT FW
REVN PU_DIR16 CND REV
STARTCOMB
BLOCK CND
BFI_3P
FW
PROTECTION 2 REV
BFI_A BFI_A
FW_A FW_A
REV_A REV_A
BFI_B BFI_B
FW_B FW_B
REV_B REV_B
BFI_C BFI_C
FW_C FW_C
REV_C REV_C
STN
FWN
REVN
STARTCOMB
BLOCK CND
BFI_3P
FW
REV
BFI_A
FW_A
REV_A
BFI_B
FW_B
REV_B
BFI_C
FW_C PROTECTION 4
PROTECTION 3 REV_C -
STN STN CND
FWN FWN -
REVN REVN -
ANSI16000164-2-en.vsdx
ANSI16000164 V2 EN-US
Figure 572: Connection example of protection functions using STARTCOMB, SMAGAPC to SMPPTRC
18.3.1 Identification
SEMOD167882-2 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Trip matrix logic TMAGAPC - -
The trip matrix logic (TMAGAPC) function is used to route trip signals and other logical output signals to
different output contacts on the IED.
The trip matrix logic function has 3 output signals and these outputs can be connected to physical
tripping outputs according to the specific application needs for settable pulse or steady output.
TMAGAPC
BLOCK OUTPUT1
BLK1 OUTPUT2
BLK2 OUTPUT3
BLK3
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
INPUT17
INPUT18
INPUT19
INPUT20
INPUT21
INPUT22
INPUT23
INPUT24
INPUT25
INPUT26
INPUT27
INPUT28
INPUT29
INPUT30
INPUT31
INPUT32
IEC13000197 V2 EN-US
18.3.4 Signals
PID-6513-INPUTSIGNALS v4
18.3.5 Settings
PID-6513-SETTINGS v4
The trip matrix logic (TMAGAPC) block is provided with 32 input signals and 3 output signals. The
function block incorporates internal logic OR gates in order to provide grouping of connected input
signals to the three output signals from the function block.
Internal built-in OR logic is made in accordance with the following three rules:
1. when any one of first 16 inputs signals (INPUT1 to INPUT16) has logical value 1 the first output
signal (OUTPUT1) will get logical value 1.
2. when any one of second 16 inputs signals (INPUT17 to INPUT32) has logical value 1 the second
output signal (OUTPUT2) will get logical value 1.
3. when any one of all 32 input signals (INPUT1 to INPUT32) has logical value 1 the third output signal
(OUTPUT3) will get logical value 1.
By use of the settings ModeOutput1, ModeOutput2, ModeOutput3, PulseTime, OnDelay and OffDelay
the behavior of each output can be customized. The OnDelay is always active and will delay the input
to output transition by the set time. The ModeOutput for respective output decides whether the output
shall be steady with an drop-off delay as set by OffDelay or if it shall give a pulse with duration set by
PulseTime. Note that for pulsed operation and that the inputs are connected in an OR-function, a new
pulse will only be given on the output if all related inputs are reset and then one is activated again. For
steady operation the OffDelay will pickup when all related inputs have reset. Detailed logical diagram is
shown in Figure 574.
PulseTime
t
AND
ModeOutput1
INPUT 1
OUTPUT 1
OR
0-OnDelay 0 AND
OR
0 0-OffDelay
INPUT 16
PulseTime
t
AND
ModeOutput2
INPUT 17
OUTPUT 2
OR
0-OnDelay 0 AND
OR
0 0-OffDelay
INPUT 32
PulseTime
t
AND
ModeOutput3
OUTPUT 3
OR
0-OnDelay 0 AND
OR
0 0-OffDelay
ANSI10000055-3-en.vsd
ANSI10000055 V3 EN-US
Output signals from TMAGAPC are typically connected to other logic blocks or directly to output contacts
in the IED. When used for direct tripping of the circuit breaker(s) the pulse time shall be set to at least
0.150 seconds in order to obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip
coils.
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Logic for group alarm ALMCALH - -
The group alarm logic function (ALMCALH) is used to route several alarm signals to a common
indication, LED and/or contact, in the IED.
ALMCALH
BLOCK ALARM
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC13000181 V2 EN-US
18.4.4 Signals
PID-6510-INPUTSIGNALS v5
18.4.5 Settings
PID-6510-SETTINGS v5
The logic for group alarm ALMCALH block is provided with 16 input signals and one ALARM output
signal. The function block incorporates internal logic OR gate in order to provide grouping of connected
input signals to the output ALARM signal from the function block.
When any one of 16 input signals (INPUT1 to INPUT16) has logical value 1, the ALARM output signal
will get logical value 1.
The function has a drop-off delay of 200 ms when all inputs are reset to provide a steady signal.
Input 1
ALARM
1 200 ms
0
Input 16
ANSI13000191-1-en.vsd
ANSI13000191 V1 EN-US
The group warning logic function (WRNCALH) is used to route several warning signals to a common
indication, LED and/or contact, in the IED.
WRNCALH
BLOCK WARNING
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC13000182 V2 EN-US
18.5.4 Signals
PID-4127-INPUTSIGNALS v3
18.5.5 Settings
PID-4127-SETTINGS v3
The logic for group warning WRNCALH block is provided with 16 input signals and 1 WARNING output
signal. The function block incorporates internal logic OR gate in order to provide grouping of connected
input signals to the output WARNING signal from the function block.
When any one of 16 input signals (INPUT1 to INPUT16) has logical value 1, the WARNING output
signal will get logical value 1.
The function has a drop-off delay of 200 ms when all inputs are reset to provide a steady signal.
INPUT1
WARNING
1 200 ms
0
INPUT16
ANSI13000192-1-en.vsd
ANSI13000192 V1 EN-US
The group indication logic function (INDCALH) is used to route several indication signals to a common
indication, LED and/or contact, in the IED.
INDCALH
BLOCK IND
INPUT1
INPUT2
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
INPUT9
INPUT10
INPUT11
INPUT12
INPUT13
INPUT14
INPUT15
INPUT16
IEC13000183 V2 EN-US
18.6.4 Signals
PID-4128-INPUTSIGNALS v4
18.6.5 Settings
PID-4128-SETTINGS v4
The logic for group indication INDCALH block is provided with 16 input signals and 1 IND output signal.
The function block incorporates internal logic OR gate in order to provide grouping of connected input
signals to the output IND signal from the function block.
When any one of 16 input signals (INPUT1 to INPUT16) has logical value 1, the IND output signal will
get logical value 1.
The function has a drop-off delay of 200 ms when all inputs are reset to provide a steady signal.
INPUT1
IND
1 200 ms
0
INPUT16
ANSI13000193-1-en.vsd
ANSI13000193 V1 EN-US
The basic configurable logic blocks do not propagate the time stamp and quality of signals (have no
suffix QT at the end of their function name). A number of logic blocks and timers are always available
as basic for the user to adapt the configuration to the specific application needs. The list below shows a
summary of the function blocks and their features.
The logic blocks are available as a part of an extension logic package. The list below is a summary of
the function blocks and their features.
• AND function block. The AND function is used to form general combinatory expressions with boolean
variables. The AND function block has up to four inputs and two outputs. One of the outputs is
inverted.
• GATE function block is used for whether or not a signal should be able to pass from the input to the
output.
• INVERTER function block that inverts the input signal to the output.
• LLD function block. Loop delay used to delay the output signal one execution cycle.
• OR function block. The OR function is used to form general combinatory expressions with boolean
variables. The OR function block has up to six inputs and two outputs. One of the outputs is inverted.
• PULSETIMER function block can be used, for example, for pulse extensions or limiting of operation of
outputs, settable pulse time.
• RSMEMORY function block is a flip-flop that can reset or set an output from two inputs respectively.
Each block has two outputs where one is inverted. The memory setting controls if, after a power
interruption, the flip-flop resets or returns to the state it had before the power interruption. RESET input
has priority.
• SRMEMORY function block is a flip-flop that can set or reset an output from two inputs respectively.
Each block has two outputs where one is inverted. The memory setting controls if, after a power
interruption, the flip-flop resets or returns to the state it had before the power interruption. The SET
input has priority.
• TIMERSET function has pick-up and drop-out delayed outputs related to the input signal. The timer
has a settable time delay.
• XOR is used to generate combinatory expressions with boolean variables. XOR has two inputs and
two outputs. One of the outputs is inverted. The output signal OUT is 1 if the input signals are different
and 0 if they are the same.
M11453-3 v4
The AND function is used to form general combinatory expressions with boolean variables. The AND
function block has up to four inputs and two outputs. One of the outputs is inverted.
AND
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
IEC14000071 V2 EN-US
18.7.1.2 Signals
PID-3437-INPUTSIGNALS v8
M11489-3 v2
The Controllable gate function block (GATE) is used for controlling if a signal should be able to pass
from the input to the output or not depending on a setting.
IEC04000410 V3 EN-US
18.7.2.2 Signals
PID-3801-INPUTSIGNALS v7
18.7.2.3 Settings
PID-3801-SETTINGS v7
INV
INPUT OUT
IEC04000404 V3 EN-US
18.7.3.2 Signals
PID-3803-INPUTSIGNALS v6
GUID-64B24094-010D-4B8F-8B7B-DDD49499AAE5 v3
The Logic loop delay function block (LLD) function is used to delay the output signal one execution
cycle, that is, the cycle time of the function blocks used.
LLD
INPUT OUT
IEC15000144 V2 EN-US
18.7.4.2 Signals
PID-3805-INPUTSIGNALS v6
M11449-3 v2
The OR function is used to form general combinatory expressions with boolean variables. The OR
function block has up to six inputs and two outputs. One of the outputs is inverted.
OR
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
INPUT5
INPUT6
IEC04000405 V3 EN-US
18.7.5.2 Signals
PID-3806-INPUTSIGNALS v6
M11466-3 v3
The pulse (PULSETIMER) function can be used, for example, for pulse extensions or limiting the
operation time of outputs. The PULSETIMER has a settable length. When the input is 1, the output will
be 1 for the time set by the time delay parameter t. Then it returns to 0.
PULSETIMER
INPUT OUT
IEC04000407 V4 EN-US
18.7.6.2 Signals
PID-6985-INPUTSIGNALS v2
18.7.6.3 Settings
PID-6985-SETTINGS v2
GUID-4C804DEA-3C83-4C20-82C6-BAD03BD48242 v6
The Reset-set with memory function block (RSMEMORY) is a flip-flop with memory that can reset or set
an output from two inputs respectively. Each RSMEMORY function block has two outputs, where one is
inverted. The memory setting controls if, after a power interruption, the flip-flop resets or returns to the
state it had before the power interruption. For a Reset-Set flip-flop, RESET input has higher priority over
SET input.
RSMEMORY
SET OUT
RESET NOUT
IEC09000294 V2 EN-US
18.7.7.2 Signals
PID-3811-INPUTSIGNALS v6
18.7.7.3 Settings
PID-3811-SETTINGS v6
M11485-3 v4
The Set-reset with memory function block (SRMEMORY) is a flip-flop with memory that can set or reset
an output from two inputs respectively. Each SRMEMORY function block has two outputs, where one is
inverted. The memory setting controls if, after a power interruption, the flip-flop resets or returns to the
state it had before the power interruption. The input SET has priority.
SRMEMORY
SET OUT
RESET NOUT
IEC04000408 V4 EN-US
18.7.8.2 Signals
PID-3813-INPUTSIGNALS v6
18.7.8.3 Settings
PID-3813-SETTINGS v6
M11494-3 v3
The Settable timer function block (TIMERSET) timer has two outputs for the delay of the input signal at
drop-out and at pick-up. The timer has a settable time delay. It also has an Operation setting Enabled
and Disabled that controls the operation of the timer.
Input
tdelay
On
Off
tdelay
t
IEC08000289 V3 EN-US
TIMERSET
INPUT ON
OFF
IEC04000411 V3 EN-US
18.7.9.2 Signals
PID-6976-INPUTSIGNALS v2
18.7.9.3 Settings
PID-6976-SETTINGS v2
M11477-3 v4
The exclusive OR function (XOR) is used to generate combinatory expressions with boolean variables.
XOR has two inputs and two outputs. One of the outputs is inverted. The output signal OUT is 1 if the
input signals are different and 0 if they are the same.
XOR
INPUT1 OUT
INPUT2 NOUT
IEC04000409 V3 EN-US
18.7.10.2 Signals
PID-3817-INPUTSIGNALS v2
The configurable logic blocks QT propagate the time stamp and the quality of the input signals (have
suffix QT at the end of their function name).
The function blocks assist the user to adapt the IEDs' configuration to the specific application needs.
The list below shows a summary of the function blocks and their features.
• ANDQT AND function block. The function also propagates the time stamp and the quality of input
signals. Each block has four inputs and two outputs where one is inverted.
• INDCOMBSPQT combines single input signals to group signal. Single position input is copied to value
part of SP_OUT output. TIME input is copied to time part of SP_OUT output. Quality input bits are
copied to the corresponding quality part of SP_OUT output.
• INDEXTSPQT extracts individual signals from a group signal input. The value part of single position
input is copied to SI_OUT output. The time part of single position input is copied to TIME output. The
quality bits in the common part and the indication part of inputs signal are copied to the corresponding
quality output.
• INVALIDQT function which sets quality invalid of outputs according to a "valid" input. Inputs are copied
to outputs. If input VALID is 0, or if its quality invalid bit is set, all outputs invalid quality bit will be set to
invalid. The time stamp of an output will be set to the latest time stamp of INPUT and VALID inputs.
• INVERTERQT function block that inverts the input signal and propagates the time stamp and the
quality of the input signal.
• ORQT OR function block that also propagates the time stamp and the quality of the input signals.
Each block has six inputs and two outputs where one is inverted.
• PULSETIMERQT Pulse timer function block can be used, for example, for pulse extensions or limiting
of operation of outputs. The function also propagates the time stamp and the quality of the input
signal.
• RSMEMORYQT function block is a flip-flop that can reset or set an output from two inputs respectively.
Each block has two outputs where one is inverted. The memory setting controls if the block after a
power interruption should return to the state before the interruption, or be reset. The function also
propagates the time stamp and the quality of the input signal.
• SRMEMORYQT function block is a flip-flop that can set or reset an output from two inputs respectively.
Each block has two outputs where one is inverted. The memory setting controls if the block after a
power interruption should return to the state before the interruption, or be reset. The function also
propagates the time stamp and the quality of the input signal.
• TIMERSETQT function has pick-up and drop-out delayed outputs related to the input signal. The timer
has a settable time delay. The function also propagates the time stamp and the quality of the input
signal.
• XORQT XOR function block. The function also propagates the time stamp and the quality of the input
signals. Each block has two outputs where one is inverted.
The ANDQT function is used to form general combinatory expressions with boolean variables. The
ANDQT function block has four inputs and two outputs.
ANDQT
INPUT1 OUT
INPUT2 NOUT
INPUT3
INPUT4
IEC09000297 V2 EN-US
PID-3800-INPUTSIGNALS v7
GUID-EEBD65A5-394C-4ECD-BF6F-D556B610FC57 v3
The value of single point input (SP_IN) is copied to the value part of the SP_OUT output. The TIME
input is copied to the time part of the SP_OUT output. State input bits are copied to the corresponding
state part of the SP_OUT output. If the state or value on the SP_OUT output changes, the Event bit in
the state part is toggled.
INDCOMBSPQT can propagate the quality, the value and the time stamps of the signals via IEC 61850.
INDCOMBSPQT
SP_IN* SP_OUT
TIME*
BLOCKED*
SUBST*
INVALID*
TEST*
IEC15000146 V2 EN-US
PID-3792-INPUTSIGNALS v2
GUID-9B700C69-4DAE-434A-BCE6-CE2D1139680A v3
The value part of the single point input signal SI_IN is copied to SI_OUT output. The time part of single
point input is copied to the TIME output. The state bits in the common part and the indication part of the
input signal are copied to the corresponding state output.
INDEXTSPQT can propagate the quality, the value and the time stamps of the signals via IEC 61850.
INDEXTSPQT
SI_IN* SI_OUT
TIME
BLOCKED
SUBST
INVALID
TEST
IEC14000067 V2 EN-US
PID-3821-INPUTSIGNALS v2
The values of the input signals INPUTx (where 1<x<16) are copied to the outputs OUTPUTx (where
1<x<16). If the input VALID is 0 or if its quality bit is set invalid, all outputs OUTPUTx (where 1<x<16)
quality bit will be set to invalid. The time stamp of any output OUTPUTx (where 1<x<16) will be set to the
latest time stamp of any input and the input VALID.
INVALIDQT can propagate the quality, the value and the time stamps of the signals via IEC 61850.
INVALIDQT
INPUT1 OUTPUT1
INPUT2 OUTPUT2
INPUT3 OUTPUT3
INPUT4 OUTPUT4
INPUT5 OUTPUT5
INPUT6 OUTPUT6
INPUT7 OUTPUT7
INPUT8 OUTPUT8
INPUT9 OUTPUT9
INPUT10 OUTPUT10
INPUT11 OUTPUT11
INPUT12 OUTPUT12
INPUT13 OUTPUT13
INPUT14 OUTPUT14
INPUT15 OUTPUT15
INPUT16 OUTPUT16
VALID
IEC08000169 V2 EN-US
PID-3822-INPUTSIGNALS v6
The INVERTERQT function block inverts one binary input signal to the output. It can propagate the
quality, value and the time stamps of the signals via IEC 61850.
INVERTERQT
INPUT OUT
IEC09000299 V2 EN-US
PID-3804-INPUTSIGNALS v6
GUID-F8AECD9C-83FC-4025-9AB5-809D88122277 v4
The ORQT function block (ORQT) is used to form general combinatory expressions OR with boolean
variables. ORQT function block has up to six inputs and two outputs. One of the outputs is inverted. It
can propagate the quality, value and the timestamps of the signals via IEC 61850.
IEC09000298 V3 EN-US
PID-3807-INPUTSIGNALS v6
GUID-D930E5A7-C564-4464-B97F-C72B4801C917 v4
The pulse timer function block (PULSETIMERQT) can be used, for example, for pulse extensions or for
limiting the operation time of the outputs. PULSETIMERQT has a settable output pulse length.
When the input goes to 1, the output will be 1 for the time set by the time delay parameter t. Then it
returns to 0.
When the output changes value, the time stamp of the output signal is updated.
The supported “quality” state bits are propagated from the input to the output at each execution cycle. A
change of these bits will not lead to an updated time stamp on the output.
PULSETIMERQT can propagate the quality, value and the time stamps of the signals via IEC 61850.
PULSETIMERQT
INPUT OUT
IEC15000145 V2 EN-US
PID-3810-INPUTSIGNALS v6
18.8.7.3 Settings
PID-3810-SETTINGS v6
GUID-32A1B759-2ED8-45B3-8385-762167626CE2 v7
The Reset-set function (RSMEMORYQT) is a flip-flop with memory that can reset or set an output from
two inputs respectively. Each RSMEMORYQT function block has two outputs, where one is inverted.
The memory setting controls if, after a power interruption, the flip-flop resets or returns to the state it had
before the power interruption. For a Reset-Set flip-flop, the RESET input has higher priority than the SET
input.
RSMEMORYQT can propagate the quality, the value and the time stamps of the signals via IEC 61850.
RSMEMORYQT
SET OUT
RESET NOUT
IEC14000069 V2 EN-US
PID-3812-INPUTSIGNALS v6
18.8.8.3 Settings
PID-3812-SETTINGS v6
GUID-39060D4B-9AA7-4505-9487-88B2CBC534F0 v7
The Set-reset function (SRMEMORYQT) is a flip-flop with memory that can set or reset an output from
two inputs respectively. Each SRMEMORYQT function block has two outputs, where one is inverted.
The memory setting controls if, after a power interruption, the flip-flop resets or returns to the state it had
before the power interruption. The SET input has priority.
SRMEMORYQT can propagate the quality, the value and the time stamps of the signals via IEC 61850.
SRMEMORYQT
SET OUT
RESET NOUT
IEC14000070 V2 EN-US
PID-3814-INPUTSIGNALS v6
18.8.9.3 Settings
PID-3814-SETTINGS v6
The Settable timer function block (TIMERSETQT) has two outputs for delay of the input signal at pick-up
and drop-out. The timer has a settable time delay (t). It also has an Operation setting On/Off that
controls the operation of the timer.
Input
t t
On
Off
t t
time
D0E12352T201305151403 V2 EN-US
When the output changes value, the timestamp of the output signal is updated. The supported “quality”
state bits are propagated from the input to the output at each execution cycle. A change of these bits will
not lead to an updated timestamp on the output.
TIMERSETQT can propagate the quality, value and the timestamps of the signals via IEC 61850.
TIMERSETQT
INPUT ON
OFF
IEC14000068 V3 EN-US
PID-3816-INPUTSIGNALS v6
18.8.10.4 Settings
PID-3816-SETTINGS v6
The exclusive OR function (XORQT) function is used to generate combinatory expressions with boolean
variables. XORQT function has two inputs and two outputs. One of the outputs is inverted. The output
signal OUT is 1 if the input signals are different and 0 if they are equal.
XORQT can propagate the quality, value and time stamps of the signals via IEC 61850.
XORQT
INPUT1 OUT
INPUT2 NOUT
IEC09000300 V2 EN-US
PID-3818-INPUTSIGNALS v6
When extra configurable logic blocks are required, an additional package can be ordered.
GUID-19810098-1820-4765-8F0B-7D585FFC0C78 v8
The Fixed signals function (FXDSIGN) has nine pre-set (fixed) output signals that can be used in the
configuration of an IED, either for forcing the unused inputs in other function blocks to a certain level/
value, or for creating certain logic. Boolean, integer, floating point, string types of signals are available.
IEC05000445 V4 EN-US
18.10.3 Signals
PID-6191-OUTPUTSIGNALS v7
18.10.4 Settings
PID-1325-SETTINGS v13
The function does not have any settings available in WebUI or Protection and Control IED Manager
(PCM600).
18.11.1 Identification
SEMOD175721-2 v3
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Boolean 16 to integer B16I - -
conversion
Boolean to integer conversion, 16 bit (B16I) is used to transform a set of 16 boolean (logical) signals into
an integer.
B16I
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IEC07000128 V3 EN-US
18.11.4 Signals
PID-3606-INPUTSIGNALS v4
The function does not have any parameters available in the local HMI or PCM600.
The Boolean 16 to integer conversion function (B16I) will transfer a combination of up to 16 binary inputs
INx, where 1≤x≤16, to an integer. Each INx represents a value according to the table below from 0 to
32768. This follows the general formula: INx = 2x-1 where 1≤x≤16. The sum of all the values on the
activated INx will be available on the output OUT as a sum of the integer values of all the inputs INx
that are activated. OUT is an integer. When all INx (where 1≤x≤16) are activated, that is = Boolean 1,
it corresponds to that integer 65535 is available on the output OUT. The B16I function is designed for
receiving up to 16 booleans input locally. If the BLOCK input is activated, it will freeze the output at the
last value.
Values of each of the different OUTx from function block B16I for 1≤x≤16.
The sum of the value on each INx corresponds to the integer presented on the output OUT on the
function block B16I
The sum of the numbers in column “Value when activated” when all INx (where 1≤x≤16) are active that
is=1; is 65535. 65535 is the highest boolean value that can be converted to an integer by the B16I
function block.
18.12.1 Identification
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Boolean to integer BTIGAPC - -
conversion with logical node
representation, 16 bit
Boolean to integer conversion with logical node representation, 16 bit (BTIGAPC) is used to transform a
set of 16 boolean (logical) signals into an integer. The block input will freeze the output at the last value.
BTIGAPC
BLOCK OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IEC13000303 V2 EN-US
18.12.4 Signals
PID-6944-INPUTSIGNALS v3
The function does not have any parameters available in the local HMI or PCM600.
The Boolean 16 to integer conversion with logic node representation function (BTIGAPC) will transfer
a combination of up to 16 binary inputs INx, where 1≤x≤16, to an integer. Each INx represents a value
according to the table below from 0 to 32768. This follows the general formula: INx = 2x-1 where 1≤x≤16.
The sum of all the values on the activated INx will be available on the output OUT as a sum of the
integer values of all the inputs INx that are activated. OUT is an integer. When all INx (where 1≤x≤16)
are activated, that is = Boolean 1, it corresponds to that integer 65535 is available on the output OUT. If
the BLOCK input is activated, it will freeze the logical outputs at the last value.
Table 778: Values of each of the different OUTx from function block BTIGAPC for 1≤x≤16
18.13.1 Identification
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Integer to boolean 16 IB16 - -
conversion
Integer to boolean 16 conversion function (IB16) is used to transform an integer into a set of 16 boolean
(logical) signals.
IB16
BLOCK OUT1
INP OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
ANSI06000501-1-en.vsd
ANSI06000501 V1 EN-US
18.13.4 Signals
PID-6938-INPUTSIGNALS v1
The function does not have any parameters available in local HMI or Protection and Control IED
Manager (PCM600)
With integer 15 on the input INP the OUT1 = OUT2 = OUT3= OUT4 =1 and the remaining OUTx = 0 for
(5≤x≤16).
OUTx represents a value when activated. The value of each of the OUTx is in accordance with the table
IB16_1. When not activated the OUTx has the value 0.
In the above example when integer 15 is on the input INP the OUT1 has a value =1, OUT2 has a value
=2, OUT3 has a value =4 and OUT4 has a value =8. The sum of these OUTx is equal to 1 + 2 + 4 + 8 =
15.
This follows the general formulae: The sum of the values of all OUTx = 2x-1 where 1≤x≤16 will be equal
to the integer value on the input INP.
The Integer to Boolean 16 conversion function (IB16) will transfer an integer with a value between 0 to
65535 connected to the input INP to a combination of activated outputs OUTx where 1≤x≤16. The sum
of the values of all OUTx will then be equal to the integer on input INP. The values of the different OUTx
are according to the table below. When an OUTx is not activated, its value is 0.
When all OUTx where 1≤x≤16 are activated that is = Boolean 1 it corresponds to that integer 65535
is connected to input INP. The IB16 function is designed for receiving the integer input locally. If the
BLOCK input is activated, it will freeze the logical outputs at the last value.
Values of each of the different OUTx from function block IB16 for 1≤x≤16.
The sum of the value on each INx corresponds to the integer presented on the output OUT on the
function block IB16.
The sum of the numbers in column “Value when activated” when all OUTx (where x = 1 to 16) are active
that is=1; is 65535. 65535 is the highest integer that can be converted by the IB16 function block.
18.14.1 Identification
SEMOD167944-2 v6
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Integer to boolean ITBGAPC - -
conversion with logical node
representation, 16 bit
Integer to boolean conversion with logic node representation function (ITBGAPC) is used to transform
an integer which is transmitted over IEC 61850 and received by the function to 16 boolean (logic) output
signals.
ITBGAPC function can only receive remote values over IEC 61850 when the R/L (Remote/Local) push
button on the front HMI indicates that the control mode for the operator is in position R (Remote i.e.
the LED adjacent to R is lit), and the corresponding signal is connected to the input PSTO ITBGAPC
function block. The input BLOCK will freeze the output at the last received value and blocks new integer
values to be received and converted to binary coded outputs.
ITBGAPC
BLOCK OUT1
PSTO OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
IEC14000012 V2 EN-US
18.14.4 Signals
PID-3627-INPUTSIGNALS v7
18.14.5 Settings
GUID-F573CA16-4821-4203-970A-F7D01AF5E63B v1
This function does not have any setting parameters.
An example is used to explain the principle of operation: With integer 15 sent to and received by the
ITBGAPC function on the IEC 61850 the OUTx changes from 0 to 1 on each of the OUT1; OUT2 OUT3
and OUT4. All other OUTx (5≤x≤16) remains 0. The boolean interpretation of this is represented by
the assigned values of each of the outputs OUT1 = 1; and OUT2 = 2; and OUT3= 4; and OUT4 = 8.
The sum of these OUTx (1≤x≤4) is equal to the integer 15 received via the IEC 61850 network. The
remaining OUTx = 0 for (5≤x≤16).
OUTx represents a value when activated. The value of each of the OUTx is in accordance with the Table
785. When not activated the OUTx has the value 0.
The value of each OUTx for 1≤x≤16 (1≤x≤16) follows the general formulae: OUTx = 2x-1 The sum of the
values of all activated OUTx = 2x-1 where 1≤x≤16 will be equal to the integer value received over IEC
61850 to the ITBGAPC_1 function block.
The Integer to boolean conversion with logical node representation, 16 bit function (ITBGAPC) will
transfer an integer with a value between 0 to 65535 communicated via IEC 61850 and connected to
the ITBGAPC function block to a combination of activated outputs OUTx where 1≤x≤16. The values
represented by the different OUTx are according to Table 785. When an OUTx is not activated, its value
is 0.
The ITBGAPC function is designed for receiving the integer input from a station computer - for example,
over IEC 61850. If the BLOCK input is activated, it will freeze the logical outputs at the last value.
The sum of the numbers in column “Value when activated” when all OUTx (1≤x≤16) are active equals
65535. This is the highest integer that can be converted to boolean by the ITBGAPC function block.
The operator position input (PSTO) determines the operator place. The integer number that is
communicated to the ITBGAPC can only be written to the block while the PSTO is in position “Remote”.
If PSTO is in position ”Off” or ”Local”, then no changes are applied to the outputs.
Elapsed Time Integrator (TEIGAPC) function is a function that accumulates the elapsed time when a
given binary signal has been high, see also Figure 604.
BLOCK
RESET
IN Time Integration ACCTIME
with Retain
q-1
a
OVERFLOW
AND
a>b
999 999 s b
a
WARNING
AND
a>b
tWarning b
a
ALARM
AND
a>b
tAlarm b
IEC13000290 V2 EN-US
TEIGAPC
BLOCK WARNING
IN ALARM
RESET OVERFLOW
ACCTIME
IEC14000014-1-en.vsd
IEC14000014 V1 EN-US
18.15.4 Signals
PID-6836-INPUTSIGNALS v3
PID-6836-OUTPUTSIGNALS v4
18.15.5 Settings
PID-6836-SETTINGS v2
• time integration, accumulating the elapsed time when a given binary signal has been high
• blocking and reset of the total integrated time
• supervision of limit transgression and overflow, the overflow limit is fixed to 999999.9 seconds
• retaining of the integrated value
Figure 606 describes the simplified logic of the function where the block “Time Integration“ covers
the logics for the first two items listed above while the block “Transgression Supervision Plus
Retain“ contains the logics for the last two.
Loop Delay
tWarning
OVERFLOW
tAlarm
Transgression Supervision WARNING
Plus Retain
ALARM
BLOCK
RESET ACCTIME
Time Integration
IN
Loop Delay
IEC12000195-4-en.vsd
IEC12000195 V4 EN-US
• RESET: Reset of the integration value. Consequently all other outputs are also reset
• unconditionally on the input IN value
• reset the value of the nonvolatile memory to zero
The ACCTIME output represents the integrated time in seconds while tOverflow, tAlarm and tWarning
are the time limit parameters in seconds.
tAlarm and tWarning are user settable limits. They are also independent, that is, there is no check if
tAlarm > tWarning.
tAlarm and tWarning are possible to be defined with a resolution of 10 ms, depending on the level of the
defined values for the parameters.
The limit for the overflow supervision is fixed at 999999.9 seconds. The outputs freeze if an overflow
occurs.
In principle, a shorter function cycle time, longer integrated time length or more pulses may lead to
reduced accuracy.
The function gives the possibility to monitor the level of integer values in the system relative to each
other or to a fixed value. It is a basic arithmetic function that can be used for monitoring, supervision,
interlocking and other logics.
INTCOMP
INPUT INEQUAL
REF INHIGH
INLOW
IEC15000052-1-en.vsdx
IEC15000052 V1 EN-US
18.16.4 Signals
PID-6928-INPUTSIGNALS v3
18.16.5 Settings
PID-6928-SETTINGS v2
The selection of reference value for comparison is done through setting RefSource. If RefSource is
selected as "Input REF" then the reference value for comparison is taken from second input signal
(REF). If RefSource is selected as "Set Value" then the reference value for comparison is taken from
setting (SetValue).
The comparison can be done either between absolute values or signed values, which is governed by
on the setting EnaAbs. If EnaAbs is selected as "Absolute" then both input and reference values are
converted into absolute values and comparison is done. If EnaAbs is selected as "Signed" then the
comparison is done without any conversion.
The function has three binary outputs representing the result of the comparison:
• If the input is above the reference value then INHIGH is set HIGH
• If the input is below the reference value then INLOW is set HIGH
• If the input is equal to reference value then INEQUAL is set HIGH
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Comparator for real inputs REALCOMP Real<=>
The function gives the possibility to monitor the level of real value signals in the system relative to each
other or to a fixed value. It is a basic arithmetic function that can be used for monitoring, supervision,
interlocking and other logics.
REALCOMP
INPUT INEQUAL
REF INHIGH
INLOW
IEC15000053-1-en.vsdx
IEC15000053 V1 EN-US
18.17.5 Signals
PID-7248-INPUTSIGNALS v2
18.17.6 Settings
PID-7248-SETTINGS v1
The selection of reference value for comparison is done through setting RefSource. If RefSource is
selected as "Input REF" then the reference value for comparison is taken from second input signal
(REF). If RefSource is selected as "Set Value" then the reference value for comparison is taken from
setting (SetValue).
Generally the inputs to the function are in units, but when the comparison is to be done with respect
to set level, then the user can scale the reference value in steps of 1000, as per the setting RefPrefix.
Internally the function handles the reference value for comparator as SetValue*RefPrefix.
Additionally the comparison can be done either between absolute values or signed values, which is
determined by the setting EnaAbs. If EnaAbs is selected as "Absolute" then both input and reference
values are converted into absolute values and then comparison is done. If EnaAbs is selected as
"Signed" then the comparison is done without absolute conversion.
This function has two settings EqualBandHigh and EqualBandLow to provide margins from reference
value for equal to condition. When the INPUT value is within high and low band around the reference
value, output INEQUAL will get set.
In order to avoid oscillations at boundary conditions of equal band low limit and high limit, hysteresis has
been provided. If the INPUT is above the equal high level margin including hysteresis, then INHIGH will
set. Similarly if the INPUT is below the equal low level margin including hysteresis, then INLOW will set.
EqualBandHigh
Internal
Equal Band REF or SetValue Hysteresis for
equal band
EqualBandLow
IEC15000261 V1 EN-US
When EnaAbs is set as absolute comparison and SetValue is set less than 0.1% of the set
unit then INLOW output will never pick up. During the above mentioned condition, due to
marginal value for avoiding oscillations of function outputs, the INLOW output will never set.
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Hold maximum and minimum of HOLDMINMAX - -
input
Hold minimum and maximum of input (HOLDMINMAX) function will acquire, compare and hold the
minimum and maximum values of INPUT as soon as the START input goes to 1, the outputs are
updated as long as the START is 1. After START goes to 0, the last updated value is stored. The outputs
are reset when the RESET is 1.
HOLDMAXMIN
HOLDMINMAX
INPUT MAX
START MIN
RESET
IEC21000053-1-en.vsdx
IEC21000053 V1 EN-US
18.18.4 Signals
GUID-5B941634-5868-427A-80F8-9CA5740D3039 v1
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Converter for Integer to Real INT_REAL - -
The converter integer to real (INT_REAL) function can be used to convert integer to real values.
INT_REAL
INT_REAL
INT REAL
IEC21000055-1-en.vsdx
IEC21000055 V1 EN-US
18.19.4 Signals
PID-7883-INPUTSIGNALS v1
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Definable constant for logic CONST_INT - -
function
The definable constant for logic function CONST_INT can be used to provide a constant output in an
integer format based on the set value in PST.
CONST_INT
CONST_INT
OUT
IEC21000056-1-en.vsdx
IEC21000056 V1 EN-US
18.20.4 Signals
PID-7894-OUTPUTSIGNALS v1
18.20.5 Settings
PID-7894-SETTINGS v1
Analog input selector for integer values (INTSEL) selects one out of eight possible integer inputs. Each
input (INPUTx) has its dedicated select input (SELx). The function provides the output for the value of
the selected input, and its respective select number (INSEL).
If more than one input is selected, the output will be the lowest in order INPUT value. If inputs are not
selected, the select value number shall be 0.
INTSEL
INTSEL
INPUT1 VALUE
INPUT2 INSEL
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
SEL1
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
SEL8
IEC21000057-1-en.vsdx
IEC21000057 V1 EN-US
18.21.4 Signals
PID-7884-INPUTSIGNALS v1
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Definable limiter LIMITER - -
The definable limiter (LIMITER) function can be used to limit the output values within the minimum and
maximum limits set in the PST. If the input is outside the set range then the value OUTLIMIT is set to 1
to indicate the output value is limited.
LIMITER
LIMITER
IN OUT
OUTLIMIT
IEC21000064-1-en.vsdx
IEC21000064 V1 EN-US
18.22.4 Signals
PID-7881-INPUTSIGNALS v1
18.22.5 Settings
PID-7881-SETTINGS v1
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Absolute value ABS - -
The absolute value (ABS) function gives the absolute value of the input.
ABS
ABS
IN OUT
IEC21000063-1-en.vsdx
IEC21000063 V1 EN-US
18.23.4 Signals
PID-7885-INPUTSIGNALS v1
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Polar to rectangular converter POL_REC - -
The polar to rectangular converter (POL_REC) function gives the possibility to convert an input values in
polar form to a rectangular form.
POL_REC
MAG REAL
ANGLE IMAG
IEC22005900 V1 EN-US
18.24.4 Signals
PID-7887-INPUTSIGNALS v1
PID-7887-OUTPUTSIGNALS v1
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2
device number
Radians to degree angle converter RAD_DEG - -
The radians to degree angle converter (RAD_DEG) function gives the possibility to convert an input
value from radian angles to degree angles.
RAD_DEG
RAD_DEG
RAD DEG
IEC21000058-1-en.vsdx
IEC21000058 V1 EN-US
18.25.4 Signals
PID-7886-INPUTSIGNALS v1
The definable constant for logic function (CONST_REAL) can be used to provide a constant output in an
real format based on the set value in PST.
CONST_REAL
CONST_REAL
OUT
IEC21000059-1-en.vsdx
GUID-6A878306-1E98-469E-9E4F-1B0C46381ADE V1 EN-US
18.26.4 Signals
PID-7888-OUTPUTSIGNALS v1
18.26.5 Signals
PID-7888-SETTINGS v1
Analog input selector for real values (REALSEL) function selects one out of eight possible real inputs.
Each input (INPUTx) has its dedicated select input (SELx).
The function provides the output for the value of the selected input and its respective select number
(INSEL). If more than one input is selected, the output will be the lowest in order INPUT value. If inputs
are not selected, the select value number shall be 0.
REALSEL
REALSEL
INPUT1 VALUE
INPUT2 INSEL
INPUT3
INPUT4
INPUT5
INPUT6
INPUT7
INPUT8
SEL1
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
SEL8
IEC21000062-1-en.vsdx
IEC21000062 V1 EN-US
18.27.4 Signals
PID-7889-INPUTSIGNALS v1
The store value for integer inputs (STOREINT) function can be used to store the integer value upon the
trigger, the minimum trigger duration for it to be stored is 100ms. The stored value is reset to 0 when the
RESET input is set to 1.
GUID-4AF5186E-2BF2-4D6D-AEAC-D1854A0D04EB V1 EN-US
18.28.4 Signals
PID-7890-INPUTSIGNALS v1
The store value for real inputs (STOREREAL) function can be used to store the real value upon the
trigger, the minimum trigger duration for it to be stored is 100ms. The stored value is reset to 0 when the
RESET input is set to 1.
STOREREAL
STOREREAL
IN STOREDVAL
TRIGGER
RESET
IEC21000060-1-en.vsdx
IEC21000060 V1 EN-US
18.29.4 Signals
PID-7891-INPUTSIGNALS v1
The degree to radians angle converter (DEG_RAD) function gives the possibility to convert an input
value from degree angles to radian angles.
DEG_RAD
DEG_RAD
DEG RAD
IEC21000052-2-en.vsdx
IEC21000052 V2 EN-US
18.30.4 Signals
PID-7893-INPUTSIGNALS v1
Section 19 Monitoring
19.1 Measurements IP14593-1 v5
19.1.2 Identification
SEMOD56123-2 v9
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Power system CVMMXN -
measurements
P, Q, S, I, U, f
SYMBOL-RR V1 EN-US
SYMBOL-SS V1 EN-US
SYMBOL-UU V1 EN-US
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Current sequence CMSQI -
component measurement
I1, I2, I0
SYMBOL-VV V1 EN-US
SYMBOL-TT V1 EN-US
SYMBOL-UU V1 EN-US
Measurement functions are used for power system measurement, supervision and reporting to the local
HMI, monitoring tool within PCM600 or to station level for example, via IEC 61850. The possibility to
continuously monitor measured values of active power, reactive power, currents, voltages, frequency,
power factor etc. is vital for efficient production, transmission and distribution of electrical energy. It
provides to the system operator fast and easy overview of the present status of the power system.
Additionally, it can be used during testing and commissioning of protection and control IEDs in order to
verify proper operation and connection of instrument transformers (CTs and VTs). During normal service
by periodic comparison of the measured value from the IED with other independent meters the proper
operation of the IED analog measurement chain can be verified. Finally, it can be used to verify proper
direction orientation for distance or directional overcurrent protection function.
The available measured values from an IED are depending on the actual hardware (TRM)
and the logic configuration made in PCM600.
All measured values can be supervised with four settable limits that is, low-low limit, low limit, high limit
and high-high limit. A zero clamping reduction is also supported, that is, the measured value below a
settable limit is forced to zero which reduces the impact of noise in the inputs.
Dead-band supervision can be used to report measured signal value to station level when change in
measured value is above set threshold limit or time integral of all changes since the last time value
updating exceeds the threshold limit. Measure value can also be based on periodic reporting.
All measurement functions use fundamental frequency phasors (that is, DFT filtering) for internal
calculations and for reporting of measured values. However, from the following three measurement
functions CMMXU, VMMXU and VNMMXU it is also possible to report the total measured quantity
(that is, true RMS filtering). By selecting the RMS mode, the reported value will be in addition to the
fundamental magnitude also include harmonics.
The measurement function, CVMMXN, provides the following power system quantities:
,
The measuring functions CMMXU, VMMXU and VNMMXU provide physical quantities:
Fundamental frequency filtered values (DFT) or true RMS values can be selected as a measurement
type in CMMXU, VMMXU and VNMMXU functions.
The CVMMXN function calculates three-phase power quantities by using fundamental frequency
phasors (DFT values) of the measured current and voltage signals. The measured power quantities
are available either, as instantaneously calculated quantities or, averaged values over a period of time
(low pass filtered) depending on the selected settings.
It is possible to calibrate the measuring function above to get better then class 0.5 presentation. This is
accomplished by angle and magnitude compensation at 5, 30 and 100% of rated current and at 100% of
rated voltage.
The power system quantities provided, depends on the actual hardware, (TRM) and the logic
configuration made in PCM600.
The measuring functions CMSQI and VMSQI provide sequence component quantities:
The available function blocks of an IED are depending on the actual hardware (TRM) and the logic
configuration made in PCM600.
CVMMXN
I3P* S
V3P* S_RANGE
P_INST
P
P_RANGE
Q_INST
Q
Q_RANGE
PF
PF_RANGE
ILAG
ILEAD
V
V_RANGE
I
I_RANGE
F
F_RANGE
ANSI10000016-1-en.vsd
ANSI10000016 V1 EN-US
CMMXU
I3P* I_A
IA_RANGE
IA_ANGL
I_B
IB_RANGE
IB_ANGL
I_C
IC_RANGE
IC_ANGL
ANSI05000699-2-en.vsd
ANSI05000699 V2 EN-US
VMMXU
V3P* V_AB
VAB_RANG
VAB_ANGL
V_BC
VBC_RANG
VBC_ANGL
V_CA
VCA_RANG
VCA_ANGL
ANSI05000701-2-en.vsd
ANSI05000701 V2 EN-US
CMSQI
I3P* 3I0
3I0RANG
3I0ANGL
I1
I1RANG
I1ANGL
I2
I2RANG
I2ANGL
IEC05000703 V3 EN-US
VMSQI
V3P* 3V0
3V0RANG
3V0ANGL
V1
V1RANG
V1ANGL
V2
V2RANG
V2ANGL
ANSI05000704-2-en.vsd
ANSI05000704 V2 EN-US
VNMMXU
V3P* V_A
VA_RANGE
VA_ANGL
V_B
VB_RANGE
VB_ANGL
V_C
VC_RANGE
VC_ANGL
ANSI09000850-1-en.vsd
ANSI09000850 V1 EN-US
19.1.5 Signals
PID-6713-INPUTSIGNALS v3
PID-7953-INPUTSIGNALS v2
The available setting parameters of the measurement function (MMXU, MSQI) are depending on the
actual hardware (TRM) and the logic configuration made in PCM600.
These six functions are not handled as a group, so parameter settings are only available in the first
setting group.
The following terms are used in the Unit and Description columns:
• VBase (VB): Base voltage in primary kV. This voltage is used as reference for voltage setting. It can
be suitable to set this parameter to the rated primary voltage supervised object.
• IBase (IB): Base current in primary A. This current is used as reference for current setting. It can be
suitable to set this parameter to the rated primary current of the supervised object.
• SBase (SB): Base setting for power values in MVA.
PID-6713-SETTINGS v3
PID-6736-SETTINGS v3
The protection, control, and monitoring IEDs have functionality to measure and further process
information for currents and voltages obtained from the pre-processing blocks. The number of processed
alternate measuring quantities depends on the type of IED and built-in options.
The information on measured quantities is available for the user at different locations:
All phase angles are presented in relation to a defined reference channel. The General setting
parameter PhaseAngleRef defines the reference, see section "Analog inputs".
Measured value below zero point clamping limit is forced to zero. This allows the noise in the input
signal to be ignored. The zero point clamping limit is a general setting (XZeroDb where X equals S, P,
Q, PF, V, I, F, IA, IB, IC, VA, VB, VC, VAB, VBC, VCA, I1, I2, 3I0, V1, V2 or 3V0). Observe that this
measurement supervision zero point clamping might be overridden by the zero point clamping used for
the measurement values within CVMMXN.
Users can continuously monitor the measured quantity available in the function block by means of four
defined operating thresholds, see figure 627. The monitoring has two different modes of operating:
• Overfunction, when the measured quantity exceeds the High limit (XHiLim) or High-high limit
(XHiHiLim) pre-set values
• Underfunction, when the measured quantity decreases under the Low limit (XLowLim) or Low-low limit
(XLowLowLim) pre-set values.
X_RANGE = 3
High-high limit
X_RANGE= 1 Hysteresis
High limit
X_RANGE=0
X_RANGE=0 t
Low limit
X_RANGE=2
Low-low limit
X_RANGE=4
IEC05000657 V4 EN-US
Each analog output has one corresponding supervision level output (X_RANGE). The output signal is an
integer in the interval 0-4 (0: Normal, 1: High limit exceeded, 3: High-high limit exceeded, 2: below Low
limit and 4: below Low-low limit).
The logical value of the functional output signals changes according to figure 627.
The user can set the hysteresis (XLimHyst), which determines the difference between the operating
and reset value at each operating point, in wide range for each measuring channel separately. The
hysteresis is common for all operating values within one channel.
The actual value of the measured quantity is available locally and remotely. The measurement is
continuous for each measured quantity separately, but the reporting of the value to the higher levels
depends on the selected reporting mode. The following basic reporting modes are available:
The cyclic reporting of measured value is performed according to chosen setting (XRepTyp). The
measuring channel reports the value independent of magnitude or integral dead-band reporting.
In addition to the normal cyclic reporting the IED also report spontaneously when measured value
passes any of the defined threshold limits.
Y
Value Reported Value Reported
Value Reported Value Reported
(1st)
Y3 Value Reported
Y2 Y4
Y1 Y5
t
Value 1
Value 2
Value 3
Value 4
Value 5
(*)Set value for t: XDbRepInt
IEC05000500 V3 EN-US
If a measuring value is changed, compared to the last reported value, and the change is larger than
the ±ΔY pre-defined limits that are set by user (XDbRepInt), then the measuring channel reports the
new value to a higher level. This limits the information flow to a minimum necessary. Figure 629 shows
an example with the magnitude dead-band supervision. The picture is simplified: the process is not
continuous but the values are evaluated with a time interval of one execution cycle from each other.
Value Reported
Y
Value Reported Value Reported
Value Reported
(1st)
Y3 Y
Y
Y2 Y
Y
Y
Y
Y1
IEC99000529 V3 EN-US
After the new value is reported, the ±ΔY limits for dead-band are automatically set around it. The new
value is reported only if the measured quantity changes more than defined by the ±ΔY set limits.
The measured value is reported if the time integral of all changes exceeds the pre-set limit (XDbRepInt),
figure 630, where an example of reporting with integral dead-band supervision is shown. The picture
is simplified: the process is not continuous but the values are evaluated with a time interval of one
execution cycle from each other.
The last value reported, Y1 in figure 630 serves as a basic value for further measurement. A difference
is calculated between the last reported and the newly measured value and is multiplied by the time
increment (discrete integral). The absolute values of these integral values are added until the pre-set
value is exceeded. This occurs with the value Y2 that is reported and set as a new base for the following
measurements (as well as for the values Y3, Y4 and Y5).
The integral dead-band supervision is particularly suitable for monitoring signals with small variations
that can last for relatively long periods.
Y A1 >=
A >= pre-set value A2 >=
pre-set value pre-set value
Y3 A3 + A4 + A5 + A6 + A7 >=
pre-set value
Y2 A1 A2
A4 A6
Value Reported Y4 A3 A5 A7
(1st) Value
Value Reported Y5
A Reported Value
Reported Value
Y1 Reported
t
IEC99000530 V4 EN-US
The measurement function must be connected to three-phase current and three-phase voltage input
in the configuration tool (group signals), but it is capable to measure and calculate above mentioned
quantities in nine different ways depending on the available VT inputs connected to the IED. The end
user can freely select by a parameter setting, which one of the nine available measuring modes shall be
used within the function. Available options are summarized in the following table:
Set value Formula used for complex, Formula used for voltage Comment
for three-phase power calculation and current magnitude
parameter calculation
“Mode”
1 A, B, C Used when three phase-to-ground
S = VA × I A* + VB × I B* + VC × I C* (
V = VA + VB + VC )/ 3 voltages are available
( )
2 Arone Used when two phase-to-phase
S = VAB × I A - VBC × I C
* *
V = VAB + VBC / 2 voltages are available
( )
4 AB Used when only VAB phase-to-
S = VAB × I A - I B
* *
V = VAB phase voltage is available
Set value Formula used for complex, Formula used for voltage Comment
for three-phase power calculation and current magnitude
parameter calculation
“Mode”
( )
5 BC Used when only VBC phase-to-
S = VBC × I B - I C
* *
V = VBC phase voltage is available
( )
6 CA Used when only VCA phase-to-
S = VCA × I C - I A
* *
V = VCA phase voltage is available
(Equation 203)
EQUATION1573 V1 EN-US
I = IA
EQUATION1574 V1 EN-US (Equation 204)
8 B Used when only VB phase-to-
S = 3 × VB × I B
*
V = 3 × VB ground voltage is available
(Equation 205)
I = IB
EQUATION1575 V1 EN-US
(Equation 207)
I = IC
EQUATION1577 V1 EN-US
It shall be noted that only in the first two operating modes that is, 1 & 2 the measurement function
calculates the three-phase power accurately. In other operating modes that is, from 3 to 9 it calculates
the three-phase power under assumption that the power system is fully symmetrical. Once the complex
apparent power is calculated then the P, Q, S, & PF are calculated in accordance with the following
formulas:
P = Re( S )
EQUATION1403 V1 EN-US (Equation 209)
Q = Im( S )
EQUATION1404 V1 EN-US (Equation 210)
S = S = P2 + Q2
EQUATION1405 V1 EN-US (Equation 211)
PF = cosj = P
S
EQUATION1406 V1 EN-US (Equation 212)
Additionally to the power factor value, the two binary output signals from the function are provided which
indicates the angular relationship between the current and voltage phasors. Binary output signal ILAG
is set TRUE when current phasor is lagging behind voltage phasor. Binary output signal ILEAD is set
TRUE when current phasor is leading the voltage phasor.
Each analog output has a corresponding supervision level output (X_RANGE). The output signal is an
integer in the interval 0-4, see section "Measurement supervision".
Measured currents and voltages used in the CVMMXN function can be calibrated to get 0.5 class
measuring accuracy. This is achieved by magnitude and angle compensation at 5, 30 and 100% of rated
current and voltage. The compensation below 5% and above 100% is constant and linear in between,
see example in figure 631.
Magnitude
% of In compensation
+10
IMagComp5 Measured
IMagComp30 current
IMagComp100
5 30 100 % of In
0-5%: Constant
-10 5-30-100%: Linear
>100%: Constant
Degrees Angle
compensation
+10
IAngComp30 Measured
current
IAngComp5
IAngComp100
5 30 100 % of In
-10
ANSI05000652_3_en.vsd
ANSI05000652 V3 EN-US
The first current and voltage phase signal, in the group signals will be used as reference. The magnitude
and angle compensation will be used for other related input signals.
In order to minimize the influence of the noise signal on the measurement it is possible to introduce the
recursive, low pass filtering of the measured values for P, Q, S, V, I and power factor. This will make
slower measurement response to the step changes in the measured quantity. Filtering is performed in
accordance with the following recursive formula:
X = k × X Old + (1 - k ) × X Calculated
EQUATION1407 V1 EN-US (Equation 213)
where:
X is a new measured value (that is P, Q, S, V, I or PF) to be given out from the function
XOld is the measured value given from the measurement function in previous execution cycle
XCalculated is the new calculated value in the present execution cycle
k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is immediately given out
without any filtering (that is, without any additional delay). When k is set to value bigger than 0, the
filtering is enabled. Appropriate value of k shall be determined separately for every application. Some
typical value for k =0.14.
In order to avoid erroneous measurements when either current or voltage signal is not present, it is
possible for the end user to set the magnitudeIGenZeroDb level for current and voltage measurement
VGenZeroDb is forced to zero. When either current or voltage measurement is forced to zero
automatically the measured values for power (P, Q and S) and power factor are forced to zero as well.
Since the measurement supervision functionality, included in CVMMXN, is using these values the zero
clamping will influence the subsequent supervision (observe the possibility to do zero point clamping
within measurement supervision, see section "Measurement supervision").
In order to compensate for small magnitude and angular errors in the complete measurement chain
(CT error, VT error, IED input transformer errors and so on.) it is possible to perform on site calibration
of the power measurement. This is achieved by setting the complex constant which is then internally
used within the function to multiply the calculated complex apparent power S. This constant is set
as magnitude (setting parameter PowMagFact, default value 1.000) and angle (setting parameter
PowAngComp, default value 0.0 degrees). Default values for these two parameters are done in such
way that they do not influence internally calculated value (complex constant has default value 1). In
this way calibration, for specific operating range (for example, around rated power) can be done at site.
However, to perform this calibration it is necessary to have an external power meter with high accuracy
class available.
Directionality SEMOD54417-256 v7
If CT grounding parameter is set as described in section "Analog inputs", active and reactive power will
be always measured towards the protected object. This is shown in the following figure 632.
Busbar
52
IED
P Q
Protected
Object
ANSI05000373_2_en.vsd
ANSI05000373 V2 EN-US
Practically, it means that active and reactive power will have positive values when they flow from
the busbar towards the protected object and they will have negative values when they flow from the
protected object towards the busbar.
In some application, for example, when power is measured on the secondary side of the power
transformer it might be desirable, from the end client point of view, to have actually opposite directional
convention for active and reactive power measurements. This can be easily achieved by setting
parameter PowAngComp to value of 180.0 degrees. With such setting the active and reactive power
will have positive values when they flow from the protected object towards the busbar.
Frequency SEMOD54417-261 v2
Frequency is actually not calculated within measurement block. It is simply obtained from the pre-
processing block and then just given out from the measurement block as an output.
The Phase current measurement (CMMXU) function must be connected to three-phase current input in
the configuration tool to be operable. Currents handled in the function can be calibrated to get better
then 0.5 class measuring accuracy for internal use, on the outputs and IEC 61850. This is achieved by
magnitude and angle compensation at 5, 30 and 100% of rated current. The compensation below 5%
and above 100% is constant and linear in between, see figure 631.
There are two types of measurement available in the function through the MeasurementType setting:
• DFT
• RMS
DFT is used to calculate amplitude and angle values for the fundamental frequency component (that is,
phasor) in the current waveform. This method uses full cycle fourier filtering.
RMS calculates a true RMS value over one cycle of data. Hence, it has both the fundamental frequency
and harmonics frequency component in its measurement.
When RMS measurement mode is selected, all phase angles are forced to zero degree.
Phase currents (magnitude and angle) are available on the outputs and each magnitude output has a
corresponding supervision level output (Ix_RANGE). The supervision output signal is an integer in the
interval 0-4, see section "Measurement supervision".
The voltage function must be connected to three-phase voltage input in the configuration tool to be
operable. Voltages are handled in the same way as currents when it comes to class 0.5 calibrations, see
above.
DFT and RMS measurement types are available in VMMXU and VNMMXU functions also, as explained
in CMMXU function.
The voltages (phase-to-ground or phase-to-phase voltage, magnitude and angle) are available on the
outputs and each magnitude output has a corresponding supervision level output (Vxy_RANG). The
supervision output signal is an integer in the interval 0-4, see section "Measurement supervision".
The measurement functions must be connected to three-phase current (CMSQI) or voltage (VMSQI)
input in the configuration tool to be operable. No outputs, other than X_RANG, are calculated within
the measuring blocks and it is not possible to calibrate the signals. Input signals are obtained from the
pre-processing block and transferred to corresponding output.
Positive, negative and three times zero sequence quantities are available on the outputs (voltage and
current, magnitude and angle). Each magnitude output has a corresponding supervision level output
(X_RANGE). The output signal is an integer in the interval 0-4, see section "Measurement supervision".
GUID-ED634B6D-9918-464F-B6A4-51B78129B819 v6
19.2.2 Identification
GUID-AD96C26E-C3E5-4B21-9ED6-12E540954AC3 v6
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Insulation gas monitoring SSIMG - 63
function
Insulation supervision for gas medium (SSIMG (63) ) is used for monitoring the circuit breaker condition.
Binary information based on the gas pressure in the circuit breaker can be used as input to the function.
In addition, the function can be used with an analog value of gas pressure and temperature of the
insulation medium and binary inputs. The SSIMG function generates alarms based on the received
information.
SSIMG (63)
BLOCK LOCKOU T
BLKALM PRESLO
SENPRES TEMPLO
SENTEMP ALARM
SENPRESALM PRESALM
SENPRESLO TEMPALM
SETP LO PRESSURE
SETTLO TEMP
RESETLO
ANSI09000129-2-en.vsdx
ANSI09000129 V2 EN-US
19.2.5 Signals
GUID-89749F71-CAEB-4A57-A1F0-148CCF68E97E v3
PID-7402-INPUTSIGNALS v2
19.2.6 Settings
PID-7402-SETTINGS v2
Gas medium supervision SSIMG (63) is used to monitor the gas pressure in the circuit breaker and
temperature of the medium. The gas pressure is monitored to detect low pressure. Binary inputs of gas
are considered to initiate the gas pressure alarm PRESALM
If any gas pressure sensor measurement is available and connected to the function input, then gas
pressure sensor quality input also considered for pressure alarm and lockout detections.
Gas pressure alarm PRESALM is activated when any of the following condition occurs,
Gas pressure lockout PRESLO is activated when any of the following condition occurs,
Thus, the function can be used without any sensor inputs and allowing alarm and lockout outputs based
on binary inputs.
To avoid false alarms due to a sudden change in gas pressure, two time delays tPressureAlarm or
tPressureLO are included. If the pressure goes below the settings for more than these time delays, the
corresponding alarm PRESALM or lockout PRESLO will be initiated. The SETPLO binary input is used
for setting the gas pressure lockout PRESLO. The PRESLO output retains the last value until it is reset
by using the binary input RESETLO. The binary input BLKALM can be used to block the alarms, and the
BLOCK input can be used to block both alarm and the lockout indications.
Temperature of the medium is available from the input signal of temperature SENTEMP. The signal is
monitored to detect high temperature.
Temperature alarm TEMPALM is activated if temperature SENTEMP goes above the setting
TempAlarmLimit and quality input SENTEMPQ is high.
Temperature lockout TEMPLO is activated when any of the following condition occurs,
To avoid false alarm due to the sudden change in temperature, two time delays tTempAlarm or
tTempLockOut are included. If the temperature goes below the settings for more than these time delays,
the corresponding alarm TEMPALM or lockout TEMPLO will be initiated. The SETTLO binary input is
used for setting the gas pressure lockout TEMPLO. The TEMPLO output retains the last value until it is
reset by using the binary input RESETLO. The binary input BLKALM can be used to block the alarms,
and the BLOCK input can be used to block both alarm and the lockout indications.
The output ALARM goes high if the pressure alarm condition or the temperature alarm condition exists.
The output ALARM can be blocked by activating BLOCK or BLKALM inputs.
The output LOCKOUT goes high if the pressure lockout condition or the temperature lockout condition
exists and it gets reset by activating binary input RESETLO. The output LOCKOUT can be blocked by
activating BLOCK input.
19.3.2 Identification
GUID-4CE96EF6-42C6-4F2E-A190-D288ABF766F6 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Insulation liquid monitoring SSIML - 71
function
Insulation supervision for liquid medium (SSIML (71)) is used for monitoring the oil insulated device
condition. For example, transformers, shunt reactors, and so on. Binary information based on the liquid
level in the circuit breaker can be used as input to the function. In addition, the function can be used with
an analog value of liquid level and temperature of the insulation medium and binary inputs. The function
generates alarms based on the received information.
SSIML (71)
BLOCK LOCKOU T
BLKALM LVLLO
SENLEVEL TEMPLO
SENTEMP ALARM
SENLVLALM LVLALM
SENLEVELLO TEMPALM
SETLLO LEVEL
SETTLO TEMP
RESETLO
ANSI09000128-2-en.vsdx
ANSI09000128 V2 EN-US
19.3.5 Signals
GUID-0C378BB3-2104-417F-94B5-16EFC55151FE v3
PID-7403-INPUTSIGNALS v2
19.3.6 Settings
PID-7403-SETTINGS v2
Liquid medium supervision SSIML(71) is used to monitor the oil level and temperature of oil in the
oil insulated devices. The liquid level is monitored to detect low liquid level. Binary inputs of oil level
SENLVLALM, SENLVLLO, and gas pressure signal SENLEVEL are considered to initiate the liquid level
alarm LVLALM and the liquid level alarm lockout LVLLO.
If any gas pressure sensor measurement is available and connected to the function input, then gas
pressure sensor quality input also considered for pressure alarm and lockout detections.
Liquid level alarm LVLALM is activated when any of the following condition occurs,
Liquid level lockout LVLLO is activated when any of the following condition occurs,
Thus, the function can be used without any sensor inputs and allowing alarm and lockout outputs based
on binary inputs.
To avoid false alarm due to the sudden change in the oil level, two time delays tLevelAlarm or
tLevelLockOut are included. If the pressure goes below the settings for more than these time delays, the
corresponding alarm LVLALM or lockout LVLLO will be initiated. The SETLLO binary input is used for
setting the liquid level lockout LVLLO. The LVLLO output retains the last value until it is reset by using
the binary input RESETLO. The binary input BLKALM can be used to block the alarms, and the BLOCK
input can be used to block both alarm and the lockout indications.
Temperature of the medium is available from the input signal of temperature. The signal is monitored
to detect high temperature. If any gas temperature sensor measurement is available and connected to
the function input, then gas temperature sensor quality input also considered for temperature alarm and
lockout detections.
Temperature alarm TEMPALM is activated if temperature SENTEMP goes above the setting
TempAlarmLimit and quality input SENTEMPQ is high.
Temperature lockout TEMPLO is activated when any of the following condition occurs,
To avoid false alarm due to the sudden change in the temperature, two time delays tTempAlarmor
tTempLockOut are included. If the temperature goes below the settings for more than these time delays,
the corresponding alarm TEMPALM or lockout TEMPLO will be initiated. The SETTLO binary input is
used for setting the gas pressure lockout TEMPLO. The TEMPLO output retains the last value until it is
reset by using the binary input RESETLO. The binary input BLKALM can be used to block the alarms,
and the BLOCK input can be used to block both alarm and the lockout indications.
The output ALARM goes high if the pressure alarm condition or the temperature alarm condition exists.
The output ALARM can be blocked by activating BLOCK or BLKALM inputs.
The output LOCKOUT goes high if the pressure lockout condition or the temperature lockout condition
exists and it gets reset by activating binary input RESETLO. The output LOCKOUT can be blocked by
activating BLOCK input.
The circuit breaker condition monitoring function (SSCBR) is used to monitor different parameters of
the breaker condition. The breaker requires maintenance when the number of operations reaches a
predefined value. For a proper functioning of the circuit breaker, it is essential to monitor the circuit
breaker operation, spring charge indication or breaker wear, travel time, number of operation cycles and
estimate the accumulated energy during arcing periods. Each SCCBR function instance is made to be
used with a 1-pole, 1-phase breaker.
SSCBR
I3P* OPNPOS
BLOCK CLSPOS
BLKALM INVDPOS
TRIND COLOPN
POSOPN OPTMOPNALM
POSCLS OPTMCLSALM
PRESALM OPCNTWRN
PRESLO OPCNTALM
SPC RMNLIFEALM
SPD MONALM
RSRMNLIFE ACCMABRWRN
RSOPTM ACCMABRALM
RSACCMABR SPCALM
RSSPCTM GPRESALM
EXEOPNXCBR GPRESLO
EXEOPNCSWI
IEC13000231 V4 EN-US
SSCBR
I3P* OPENPOS
BLOCK CLOSEPOS
BLKALM INVDPOS
TRIND TRCMD
POSOPEN TRVTOPAL
POSCLOSE TRVTCLAL
PRESALM OPERALM
PRESLO OPERLO
SPRCHRST CBLIFEAL
SPRCHRD MONALM
RSTCBWR IPOWALPH
RSTTRVT IPOWLOPH
RSTIPOW SPCHALM
RSTSPCHT GPRESALM
GPRESLO
ANSI14000061-1-en.vsd
ANSI14000061 V1 EN-US
19.4.5 Signals
PID-8315-INPUTSIGNALS v1
19.4.6 Settings
PID-8315-SETTINGS v1
The breaker monitoring function includes metering and monitoring subfunctions. The subfunctions can
be enabled and disabled with the Operation setting. The corresponding parameter values are Enabled
and Disabled.
The operation of the subfunctions is described by the module diagram as shown in figure 636. All the
modules in the diagram are explained in subsequent sections.
IRMSPh OPTMOPN
POSCLS OPTMCLS
POSOPN CB Contact Operation OPTMOPNALM
BLOCK Time OPTMCLSALM
BLKALM OPTMOPNDIFALM
RSOPTM OPTMCLSDIFALM
OPNPOS
CB Status CLSPOS
INVDPOS
RMNLIFEALM
Remaining Life of CB
RMNLIFE
RSRMNLIFE
ACCMABRWRN
Accumulated
contact abrasion ACCMABRALM
IL
TRIND ACCMABR
RSACCMABR
CB Operation OPCNTWRN
Cycles OPNUM
CB Operation MONALM
Monitoring INADAYS
SPCALM
SPC CB Spring Charge SPCTM
SPD Monitoring
RSSPCTM
GUID-BC6063F6-8206-4E20-BE3A-7859C9A24836 V1 EN-US
The circuit breaker contact operation time sub function calculates the breaker contact operation time for
opening and closing operations. The operation of the breaker contact operation time measurement is
described in Figure 637.
POSCLS OPTMOPN
Contact
POSOPN operation time OPTMCLS
calculation
RSOPTM OPTMOPNALM
GUID-B421E15B-2ED1-400D-92A8-E0E03C4F366B V1 EN-US
Figure 637: Functional module diagram for circuit breaker contact operation time
Main Contact
1
0
POSCLS
1
POSOPN
1
t1 tOpen t2 t3 tClose t4
GUID-352EA7A6-004C-4D3A-AF87-52210EC81707 V1 EN-US
Main Contact
1
0
POSCLS
1
POSOPN
1
t1 tOpen t2 t3 tClose t4
GUID-352EA7A6-004C-4D3A-AF87-52210EC81707 V1 EN-US
There is a time difference t1 between the pickup of the main contact opening and the opening of the
POSCLS auxiliary contact. Similarly, there is a time difference t2 between the time when the POSOPN
auxiliary contact opens and the main contact is completely open. Therefore, a correction factor needs to
be added to get the actual opening time. This factor is added with the OpTmOpnCor (t1+t2) setting. The
closing time is calculated by adding the value set with the OpTmClsCor (t3+t4) setting to the measured
closing time.
The last measured opening operation time (OPTMOPN) and the closing operation time (OPTMCLS) are
given as service values.
The values can be reset using the Clear menu on the LHMI or by activation of the input RSRMNLIFE.
It is also possible to block the OPTMCLSALM and OPTMOPNALM alarm signals by activating the BLKALM
input.
The circuit breaker status subfunction monitors the position of the circuit breaker, that is, whether the
breaker is in the open, closed or error position. The operation is described in figure 639.
OPNPOS
Contact position
POSCLS CLSPOS
indicator
POSOPN INVDPOS
GUID-E78F2E25-2D81-40AC-B044-058D03488A4E V1 EN-US
Figure 639: Functional module diagram for monitoring circuit breaker status
The status of the breaker is indicated with the binary outputs OPNPOS, CLSPOS and INVDPOS for open,
closed and error position respectively.
The Remaining life of circuit breaker subfunction is used to give an indication on the wear and tear of the
circuit breaker. Every time the breaker operates, the life of the circuit breaker reduces due to wear. The
breaker wear depends on the interrupted current. The remaining life of the breaker is estimated from the
circuit breaker trip curve provided by the manufacturer. The remaining life is decreased by at least one
when the circuit breaker is opened. The operation of the remaining life of circuit breaker subfunction is
described in figure 640.
IRMSPH
CB remaining RMNLIFE
POSCLS life estimation
RSRMNLIFE
Alarm limit
BLOCK RMNLIFEALM
Check
BLKALM
GUID-BBBAC955-DE50-4FC8-90DB-A5D180251BF2 V1 EN-US
Figure 640: Functional module diagram for estimating the life of the circuit breaker
It is possible to deactivate the RMNLIFEALM alarm signal by activating the binary input BLKALM.
The old circuit breaker operation counter value can be used by adding the value to the InitRmnLife
parameter. The value can be reset using the Clear menu from LHMI or by activating the input
RSRMNLIFE.
The Accumulated contact abrasion subfunction calculates the accumulated contact abrasion (Iyt) based
on current samples, where the setting CurExponent (y) ranges from 0.5 to 3.0. The operation is
described in figure 641.
The TRCMD output is enabled when either of the trip indications from the trip coil circuit TRIND is high or
the breaker status isOPNPOS.
IL
IRMSPH Accumulated
ACCMABR
POSCLS contact
abrasion
TRIND calculation
RSACCMABR
ACCMABRWRN
Alarm limit
BLOCK
Check ACCMABRALM
BLKALM
GUID-F430402D-11DC-4381-AF58-8322329A8E30 V1 EN-US
Figure 641: Functional module diagram for estimating accumulated contact abrasion
The calculation is initiated with the POSCLS or TRIND input events. It ends when the RMS current is
lower than the AccmAbrStopCur setting.
The OpnTmTrvlCor setting is used to determine the accumulated contact abrasion in relation to the time
the main contact opens. If the setting is positive, the calculation of contact abrasion starts after the
auxiliary contact has opened and the delay equal to the value of the OpnTmTrvlCor setting has passed.
When the setting is negative, the calculation starts in advance by the correction time in relation to when
the auxiliary contact opened.
close close
Main Contact Main Contact
open open
1 1
POSCLS POSCLS
0 0
Energy Energy
Accumulation Accumulation
starts starts
OpnTmTrvlCor OpnTmTrvlCor
(Negative) (Positive)
GUID-D03E3522-BFD0-4129-A3A9-700367E5B37E V1 EN-US
Accumulated contact abrasion can also be calculated by using the change of state of the trip output.
TRIND is used to get the instance of the trip output and the time delay between the trip initiation and the
opening of the main contact is introduced by the setting OpTmDelay.
The accumulated contact abrasion output ACCMABR is provided as a service value. The value can be
reset by enabling RSACCMABR through LHMI or activating the input RSACCMABR.
ACCMABRALM is activated when the accumulated contact abrasion exceeds the limit of the
AccmAbrAlmLev setting.
The ACCMABRWRN and ACCMABRALM outputs can be blocked by activating the binary input BLKALM.
The circuit breaker operation cycles subfunction counts the number of closing-opening sequences of the
breaker. The operation counter value is updated after each closing-opening sequence. The operation is
described in figure643.
POSCLS
Operation
POSOPN OPNUM
counter
RSRMNLIFE
OPCNTWRN
Alarm limit
BLOCK
Check
OPCNTALM
BLKALM
GUID-A50229B5-B78C-4043-807D-ECFCE9440A2B V1 EN-US
Figure 643: Functional module diagram for circuit breaker operation cycles
Operation counter
The operation counter counts the number of operations based on the state of change of the auxiliary
contact inputs POSCLS and POSOPN.
The number of operations OPNUM is given as a service value. The old circuit breaker operation counter
value can be used by adding the value to the InitCntVal parameter and can be reset by activating the
input RSRMNLIFE.
If the number of operations increases and exceeds the limit value set with the OpNumAlmLev setting,
the OPCNTALM output is activated.
The binary outputs OPCNTWRN and OPCNTALM are deactivated when the BLKALM input is activated.
The circuit breaker operation monitoring subfunction indicates the inactive days of the circuit breaker
and gives an alarm when the number of days exceed the set level. The operation of the circuit breaker
operation monitoring is shown in figure 644.
POSCLS
Inactive timer INADAYS
POSOPN
GUID-B761217E-CE5D-4F76-9B73-0093097D34F9 V1 EN-US
Figure 644: Functional module diagram for circuit breaker operation monitoring
Inactive timer
The Inactive timer module calculates the number of days the circuit breaker has remained in the same
open or closed state. The value is calculated by monitoring the states of the POSOPN and POSCLS
auxiliary contacts.
The number of inactive days INADAYS is available as a service value. The initial number of inactive days
is set using the InitInaDay parameter.
The circuit breaker spring charge monitoring subfunction calculates the spring charging time. The
operation is described in figure 645.
SPC
Spring charging
SPD time SPCTM
measurement
RSSPCTM
Alarm limit
BLOCK SPCALM
Check
BLKALM
GUID-3DB117D1-A927-47CF-937D-0AC0BAB5A25F V1 EN-US
Figure 645: Functional module diagram for circuit breaker spring charge indication
The binary input SPC indicates the pickup of circuit breaker spring charging time. SPD indicates that the
circuit breaker spring is charged. The spring charging time is calculated from the difference of these two
signal timings. Spring charging indication is described in figure 645.
The last measured spring charging time SPCTM is provided as a service value. The spring charging time
SPCTM can be reset on the LHMI or by activating the input RSSPCTM.
It is possible to block the SPCALM alarm signal by activating the BLKALM binary input.
The circuit breaker gas pressure indication subfunction monitors the gas pressure inside the arc
chamber. The operation is described in figure 646.
PRESALM
tON
BLOCK AND t GPRESALM
BLKALM
tON
PRESLO AND t GPRESLO
GUID-ADE5256E-4676-4EA9-AFF6-6B4EC9079A12 V1 EN-US
PRESALM
tDGasPresAlm
BLOCK AND 0 GPRESALM
BLKALM
PRESLO tDGasPresLO
AND 0 GPRESLO
ANSI12000622 V1 EN-US
Figure 646: Functional module diagram for circuit breaker gas pressure indication
When the PRESALM binary input is activated, the GPRESALM output is activated after a time delay set
with the tGasPresAlm setting. The GPRESALM alarm can be blocked by activating the BLKALM input.
If the pressure drops further to a very low level, the PRESLO binary input goes high, activating the
lockout alarm GPRESLO after a time delay set with the tGasPresLO setting. The GPRESLO alarm can be
blocked by activating the BLKALM input.
The binary input BLOCK can be used to block the function. The activation of the BLOCK input deactivates
all outputs and resets internal timers. The alarm signals from the function can be blocked by activating
the binary input BLKALM.
The output COLOPN indicates that opening coil has been operated through the open command. The
binary inputs EXEOPNXCBR and EXEOPNCSWI are open command from the control function, not from
the protection function. COLOPN is achieved by AND operation between EXEOPNXCBR and EXEOPNCSWI.
The output can be blocked by the BLOCK binary input signal.
EXEOPNXCBR
Coil Open
EXEOPNCSWI Indication COLOPN
BLOCK
GUID-AAEBD59C-5DDD-40A0-913E-6E20F3E61E3C V1 EN-US
19.5.1 Identification
SEMOD167950-2 v2
When using a Substation Automation system with LON or SPA communication, time-tagged events can
be sent at change or cyclically from the IED to the station level. These events are created from any
available signal in the IED that is connected to the Event function (EVENT). The EVENT function block
is used for remote communication.
Analog, integer and double indication values are also transferred through the EVENT function.
EVENT
BLOCK
^INPUT1
^INPUT2
^INPUT3
^INPUT4
^INPUT5
^INPUT6
^INPUT7
^INPUT8
^INPUT9
^INPUT10
^INPUT11
^INPUT12
^INPUT13
^INPUT14
^INPUT15
^INPUT16
IEC05000697-2-en.vsd
IEC05000697 V2 EN-US
PID-4145-INPUTSIGNALS v6
PID-4145-SETTINGS v6
The main purpose of the Event function (EVENT) is to generate events when the state or value of any of
the connected input signals is in a state, or is undergoing a state transition, for which event generation is
enabled.
Each EVENT function has 16 inputs INPUT1 - INPUT16. Each input can be given a name from the
Application Configuration tool. The inputs are normally used to create single events, but are also
intended for double indication events. For double indications, only the first eight inputs, 1–8, must be
used. Inputs 9–16 can be used for other types of events in the same EVENT block.
The EVENT function also has an input BLOCK to block the generation of events.
Events that are sent from the IED can originate from both internal logical signals and binary input
channels. The internal signals are time-tagged in the main processing module, while the binary input
channels are time-tagged directly on the input module. Time-tagging of the events that are originated
from internal logical signals have a resolution corresponding to the execution cycle-time of the source
application. Time-tagging of the events that are originated from binary input signals have a resolution of
1 ms.
The outputs from the EVENT function are formed by the reading of status, events and alarms by the
station level on every single input. The user-defined name for each input is intended to be used by the
station level.
All events according to the event mask are stored in a buffer, which contains up to 1000 events. If
new events appear before the oldest event in the buffer is read, the oldest event is overwritten and an
overflow alarm appears.
Events are produced according to set event masks. The event masks are treated commonly for both
the LON and SPA communication. An EventMask can be set individually for each input channel. These
settings are available:
• NoEvents
• OnSet
• OnReset
• OnChange
• AutoDetect
It is possible to define which part of the EVENT function generates the events. This can be performed
individually for communication types SPAChannelMask and LONChannelMask. For each communication
type these settings are available:
• Disabled
• Channel 1-8
• Channel 9-16
• Channel 1-16
For LON communication, events are normally sent to station level at change. It is also possible to set a
time for cyclic sending of the events individually for each input channel.
To protect the SA system from signals with a high change rate that can easily saturate the EVENT
function or the communication subsystems behind it, a quota limiter is implemented. If an input creates
events at a rate that completely consume the granted quota then further events from the channel will be
blocked. This block will be removed when the input calms down and the accumulated quota reach 66%
of the maximum burst quota. The maximum burst quota per input channel is 45 events per second.
19.6.2 Identification
M16055-1 v10
Complete and reliable information about disturbances in the primary and/or in the secondary system
together with continuous event-logging is accomplished by the disturbance report functionality.
Disturbance report (DRPRDRE), always included in the IED, acquires sampled data of all selected
analog input and binary signals connected to the function block with a maximum of 70 analog and 352
binary signals.
• Sequential of events
• Indications
• Event recorder
• Trip value recorder
• Disturbance recorder
• Fault locator
• Settings information
The Disturbance report function is characterized by great flexibility regarding configuration, initiating
conditions, recording times, and large storage capacity.
Every disturbance report recording is saved in the IED in the standard COMTRADE format. In the
COMTRADE1999 format it is saved as a header file HDR, a configuration file CFG, and a data file
DAT. In the COMTRADE2013 format, it is saved as CFF single file format. The same applies to all
events, which are continuously saved in a ring-buffer. The local HMI is used to get information about
the recordings. The disturbance report files can be uploaded to PCM600 for further analysis using the
disturbance handling tool.
M12510-3 v3
DRPRDRE
DRPOFF
RECSTART
RECMADE
CLEARED
MEMUSED
IEC05000406 V4 EN-US
A1RADR
^GRPINPUT1
^GRPINPUT2
^GRPINPUT3
^GRPINPUT4
^GRPINPUT5
^GRPINPUT6
^GRPINPUT7
^GRPINPUT8
^GRPINPUT9
^GRPINPUT10
IEC05000430 V5 EN-US
C1RADR
^INPUT41
^INPUT42
^INPUT43
^INPUT44
^INPUT45
^INPUT46
^INPUT47
^INPUT48
^INPUT49
^INPUT50
GUID-7F42F48F-7E32-412E-8E61-D3753C8A4926 V1 EN-US
C2RADR
^INPUT51
^INPUT52
^INPUT53
^INPUT54
^INPUT55
^INPUT56
^INPUT57
^INPUT58
^INPUT59
^INPUT60
GUID-B0809445-D5BE-4548-886C-618E27E8E156 V1 EN-US
C3RADR
^INPUT61
^INPUT62
^INPUT63
^INPUT64
^INPUT65
^INPUT66
^INPUT67
^INPUT68
^INPUT69
^INPUT70
GUID-D98EE545-29D9-4805-93FD-EDBB8DC17476 V1 EN-US
B1RBDR
^INPUT1
^INPUT2
^INPUT3
^INPUT4
^INPUT5
^INPUT6
^INPUT7
^INPUT8
^INPUT9
^INPUT10
^INPUT11
^INPUT12
^INPUT13
^INPUT14
^INPUT15
^INPUT16
IEC05000432 V4 EN-US
Figure 654: B1RBDR function block, binary inputs, example for B1RBDR - B22RBDR
19.6.5 Signals
PID-7839-OUTPUTSIGNALS v1
PID-4014-INPUTSIGNALS v7
PID-8032-INPUTSIGNALS v1
19.6.6 Settings
PID-7839-SETTINGS v1
A2RADR to A4RADR functions have the same Non group settings (advanced) as A1RADR but with
different numbering (examples given in brackets):
B2RBDR to B22RBDR functions have the same Non group settings (advanced) as B1RBDR but with
different numbering (examples given in brackets):
Figure 655 shows the relations between Disturbance Report, included functions and function blocks.
Sequential of events (SOE), Event recorder (ER) and Indications (IND) use information from the binary
input function blocks (BxRBDR). Trip value recorder (TVR) use analog information from the analog
input function blocks (AxRADR) which is used by FL after estimation by TVR. Disturbance recorder
DRPRDRE acquires information from both AxRADR and BxRBDR.
DRPRDRE FL
Analog signals
Trip value rec Fault locator
BxRBDR Disturbance
recorder
Binary signals
Sequential of
events
Event recorder
Indications
ANSI09000336-2-en.vsdx
ANSI09000336 V2 EN-US
The whole disturbance report can contain information for a number of recordings, each with the data
coming from all the parts mentioned above. The sequential of events function is working continuously,
independent of disturbance triggering, recording time, and so on. Settings information function contains
all the visible settings, parameter information of components configured in ACT, runtime status and
IEC 61850 behavior that is added to the disturbance record header file. These settings information is
recorded in XML format and then grouped for each function instance in the HDR file. The function,
setting names and Enum values are same as in the HMI and can be translated to the selected HMI
language. All setting values are updated along with the units. If the setting values are related to the
global base value, then the setting value is scaled and updated with corresponding global base unit.
All information in the disturbance report is stored in non-volatile flash memories. This implies that no
information is lost in case of loss of auxiliary power. Each report will get an identification number in the
interval from 0-999.
Up to 200 disturbance reports can be stored. If a new disturbance is to be recorded when the maximum
recording limit is reached, the oldest disturbance report is overwritten by the new one.
The IED flash disk should not be used to store any user files. This causes lack of space for
new disturbance recordings.
Date and time of the disturbance, the indications, events, fault location and the trip values are available
on the local HMI. To acquire a complete disturbance report the user must use a PC and - either the
PCM600 Disturbance handling tool - or a FTP or MMS (over 61850) client. The PC can be connected to
the IED front, rear or remotely via the station bus (Ethernet ports).
Indications is a list of signals that were activated during the total recording time of the disturbance (not
time-tagged).
The event recorder may contain a list of up to 150 time-tagged events, which have occurred during the
disturbance. The information is available via the local HMI or PCM600.
The sequetial of events may contain a list of totally 5000 time-tagged events. The list information is
continuously updated when selected binary signals change state. The oldest data is overwritten. The
logged signals may be presented via the local HMI or PCM600.
The recorded trip values include phasors of selected analog signals before the fault and during the fault.
Disturbance recorder records analog and binary signal data before, during and after the fault.
For each disturbance recording, the setting values of the configured components are read twice; once
during the trigger of disturbance record and again during post processing of the disturbance record.
During post processing of the disturbance record, the header file is updated with a section called
Settings . Settings has complete setting values of the configured components that are read during the
trigger time. The setting values, runtime status and the behavior of each component are compared
between the trigger and the post processing time. If there are any differences, then it will be added in the
header file under section Changed_settings.
In the HDR file, section tag Settings has an attribute tag called function which includes parameters
that are grouped based on the function instance. The function tag has content called name which is
the function name provided together with the user-defined name in brackets similar to the HMI. Status
content will indicate the runtime status of the function and beh content will indicate the IEC 61850
behavior of the components, if supported. Non runtime components will not have status and beh tag
contents.
Parameters of the function are listed as a child tag Set with contents name, value and unit:
The changed_settings attribute tag is similar to the settings section. It contains functions which have
changes in parameter value or runtime status or IEC 61850 behavior when compared with trigger and
post-processing settings values.
The IED has a built-in real-time calendar and clock. This function is used for all time tagging within the
disturbance report
Disturbance report DRPRDRE records information about a disturbance during a settable time frame.
The recording times are valid for the whole disturbance report. Disturbance recorder (DR), event
recorder (ER) and indication function register disturbance data and events during tRecording, the total
recording time.
Trig point
TimeLimit
PreFaultRecT PostFaultRecT
1 2 3
en05000487.vsd
IEC05000487 V1 EN-US
PreFaultRecT, 1 Pre-fault or pre-trigger recording time. The time before the fault including the trip time of the trigger. Use
the setting PreFaultRecT to set this time.
tFault, 2 Fault time of the recording. The fault time cannot be set. It continues as long as any valid trigger
condition, binary or analog, persists (unless limited by TimeLimit the limit time).
PostFaultRecT, 3 Post fault recording time. The time the disturbance recording continues after all activated triggers are
reset. Use the setting PostFaultRecT to set this time.
TimeLimit Limit time. The maximum allowed recording time after the disturbance recording was triggered. The limit
time is used to eliminate the consequences of a trigger that does not reset within a reasonable time
interval. It limits the maximum recording time of a recording and prevents subsequent overwriting of
already stored disturbances. Use the setting TimeLimit to set this time.
Up to 40 analog signals can be selected for recording by the Disturbance recorder and triggering of
the Disturbance report function. Out of these 40, 30 are reserved for external analog signals from
analog input modules (TRM) and line data communication module (LDCM) via preprocessing function
blocks (SMAI) and summation block (3PHSUM). The last 10 channels may be connected to internally
calculated analog signals available as function block output signals (mA input signals, phase differential
currents, bias currents and so on).
SMAI A1RADR
Block AI3P A2RADR
^GRP2_A AI1 INPUT1 A3RADR
External analog
^GRP2_B AI2 INPUT2
signals
^GRP2_C AI3 INPUT3
^GRP2_N AI4 INPUT4
Type AIN INPUT5
INPUT6
...
A4RADR
INPUT31
INPUT32
INPUT33
Internal analog signals INPUT34
INPUT35
INPUT36
...
INPUT40
ANSI10000029-1-en.vsd
ANSI10000029 V1 EN-US
The external input signals will be acquired, filtered and skewed and (after configuration) available as
an input signal on the AxRADR function block via the SMAI function block. The information is saved at
the Disturbance report base sampling rate (1000 or 1200 Hz). Internally calculated signals are updated
according to the cycle time of the specific function. If a function is running at lower speed than the base
sampling rate, Disturbance recorder will use the latest updated sample until a new updated sample is
available.
If the IED is preconfigured the only tool needed for analog configuration of the Disturbance report is the
Signal Matrix Tool (SMT, external signal configuration). In case of modification of a preconfigured IED or
general internal configuration the Application Configuration tool within PCM600 is used.
The preprocessor function block (SMAI) calculates the residual quantities in cases where only the three
phases are connected (AI4-input not used). SMAI makes the information available as a group signal
output, phase outputs and calculated residual output (AIN-output). In situations where AI4-input is used
as an input signal the corresponding information is available on the non-calculated output (AI4) on the
SMAI function block. Connect the signals to the AxRADR accordingly.
For each of the analog signals, Operation = Enabled means that it is recorded by the disturbance
recorder. The trigger is independent of the setting of Operation, and triggers even if operation is set to
Disabled. Both undervoltage and overvoltage can be used as trigger conditions. The same applies for
the current signals.
If Operation = Disabled, no waveform (samples) will be recorded and reported in graph. However, Trip
value, pre-fault and fault value will be recorded and reported. The input channel can still be used to trig
the disturbance recorder.
If Operation = Enabled, waveform (samples) will also be recorded and reported in graph.
The analog signals are presented only in the disturbance recording, but they affect the entire
disturbance report when being used as triggers.
Up to 352 binary signals can be selected to be handled by disturbance report. The signals can be
selected from internal logical and binary input signals. A binary signal is selected to be recorded when:
Each of the 352 signals can be selected as a trigger of the disturbance report (Operation = Operation—
>TrigDR =Enabled). A binary signal can be selected to activate the red LED on the local HMI (SetLED =
Enabled ).
The selected signals are presented in the event recorder, sequential of events and the disturbance
recording. But they affect the whole disturbance report when they are used as triggers. The indications
are also selected from these 352 signals with local HMI IndicationMask = Show/Hide.
The trigger conditions affect the entire disturbance report, except the sequential of events, which runs
continuously. As soon as at least one trigger condition is fulfilled, a complete disturbance report is
recorded. On the other hand, if no trigger condition is fulfilled, there is no disturbance report, no
indications, and so on. This implies the importance of choosing the right signals as trigger conditions.
• Manual trigger
• Binary-signal trigger
• Analog-signal trigger (over/under function)
A disturbance report can be manually triggered from the local HMI, PCM600 or via station bus (IEC
61850). When the trigger is activated, the manual trigger signal is generated. This feature is especially
useful for testing. Refer to the operator's manual for procedure.
Any binary signal state (logic one or a logic zero) can be selected to generate a trigger ( Triglevel = Trig
on 0/Trig on 1). When a binary signal is selected to generate a trigger from a logic zero, the selected
signal will not be listed in the indications list of the disturbance report.
All analog signals are available for trigger purposes, no matter if they are recorded in the disturbance
recorder or not. The settings are OverTrigOp, UnderTrigOp, OverTrigLe and UnderTrigLe.
The check of the trigger condition is based on peak-to-peak values. When this is found, the absolute
average value of these two peak values is calculated. If the average value is above the threshold level
for an overvoltage or overcurrent trigger, this trigger is indicated with a greater than (>) sign with the
user-defined name.
If the average value is below the set threshold level for an undervoltage or undercurrent trigger, this
trigger is indicated with a less than (<) sign with its name. The procedure is separately performed for
each channel.
This method of checking the analog trigger conditions gives a function which is insensitive to DC offset
in the signal. The trip time for this initiation is typically in the range of one cycle, 16 2/3 ms for a 60 Hz
network.
All under/over trig signal information is available on the local HMI and PCM600.
The Logical signal status report (BINSTATREP) function makes it possible for a SPA master to poll
signals from various other functions.
BINSTATREP
BLOCK OUTPUT1
^INPUT1 OUTPUT2
^INPUT2 OUTPUT3
^INPUT3 OUTPUT4
^INPUT4 OUTPUT5
^INPUT5 OUTPUT6
^INPUT6 OUTPUT7
^INPUT7 OUTPUT8
^INPUT8 OUTPUT9
^INPUT9 OUTPUT10
^INPUT10 OUTPUT11
^INPUT11 OUTPUT12
^INPUT12 OUTPUT13
^INPUT13 OUTPUT14
^INPUT14 OUTPUT15
^INPUT15 OUTPUT16
^INPUT16
IEC09000730-1-en.vsd
IEC09000730 V1 EN-US
19.7.4 Signals
PID-4144-INPUTSIGNALS v6
19.7.5 Settings
PID-4144-SETTINGS v6
The Logical signal status report (BINSTATREP) function has 16 inputs and 16 outputs. The output status
follows the inputs and can be read from the local HMI or via SPA communication.
When an input is set, the respective output is set for a user defined time. If the input signal remains set
for a longer period, the output will remain set until the input signal resets.
INPUTn
OUTPUTn
t t
IEC09000732-1-en.vsd
IEC09000732 V1 EN-US
19.8.2 Identification
SEMOD113212-2 v5
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Measured values expander RANGE_XP - -
block
The current and voltage measurements functions (CVMMXN, CMMXU, VMMXU and VNMMXU),
current and voltage sequence measurement functions (CMSQI and VMSQI) and IEC 61850 generic
communication I/O functions (MVGAPC) are provided with measurement supervision functionality. All
measured values can be supervised with four settable limits: low-low limit, low limit, high limit and high-
high limit. The measure value expander block (RANGE_XP) has been introduced to enable translating
the integer output signal from the measuring functions to 5 binary signals: below low-low limit, below low
limit, normal, above high limit or above high-high limit. The output signals can be used as conditions in
the configurable logic or for alarming purpose.
RANGE_XP
RANGE* HIGHHIGH
HIGH
NORMAL
LOW
LOWLOW
IEC05000346 V3 EN-US
PID-3819-INPUTSIGNALS v6
The input signal must be connected to a range output of a measuring function block (CVMMXN,
CMMXU, VMMXU, VNMMXU, CMSQI, VMSQ or MVGAPC). The function block converts the input
integer value to five binary output signals according to Table 905.
Measured supervised below low- between low‐ between low between above high-high limit
value is: low limit low and low and high limit high-high and
Output: limit high limit
LOWLOW High
LOW High
NORMAL High
HIGH High
HIGHHIGH High
19.9.1 Identification
GUID-F3FB7B33-B189-4819-A1F0-8AC7762E9B7E v4
Function description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Limit counter L4UFCNT -
The 12 Up Limit counter (L4UFCNT) provides a settable counter with four independent limits where the
number of positive and/or negative sides on the input signal are counted against the setting values for
limits. The output for each limit is activated when the counted value reaches that limit.
BLOCK
INPUT
Operation
Counter
RESET
VALUE
Overflow
CountType Detection OVERFLOW
OnMaxValue
Limit LIMIT1 … 4
MaxValue Check
CounterLimit1...4
Error ERROR
Detection
InitialValue
IEC12000625 V2 EN-US
The counter can be initialized to count from a settable non-zero value after reset of the function. The
function has also a maximum counted value check. The three possibilities after reaching the maximum
counted value are:
• Stops counting and activates a steady overflow indication for the next count
• Rolls over to zero and activates a steady overflow indication for the next count
• Rolls over to zero and activates a pulsed overflow indication for the next count
The pulsed overflow output lasts up to the first count after rolling over to zero, as illustrated in Figure
663.
Overflow indication
Actual value ... Max value -1 Max value Max value +1 Max value +2 Max value +3 ...
IEC12000626 V2 EN-US
The Error output is activated as an indicator of setting the counter limits and/or initial value setting(s)
greater than the maximum value. The counter stops counting the input and all the outputs except the
error output remains at zero state. The error condition remains until the correct settings for counter limits
and/or initial value setting(s) are applied.
The function can be blocked through a block input. During the block time, input is not counted and
outputs remain in their previous states. However, the counter can be initialized after reset of the function.
In this case the outputs remain in their initial states until the release of the block input.
Reset of the counter can be performed from the local HMI or via a binary input.
Reading of content and resetting of the function can also be performed remotely, for example from a IEC
61850 client. The value can also be presented as a measurement on the local HMI graphical display.
L4UFCNT
BLOCK ERROR
INPUT OVERFLOW
RESET LIMIT1
LIMIT2
LIMIT3
LIMIT4
VALUE
IEC12000029 V2 EN-US
19.9.5 Signals
PID-6966-INPUTSIGNALS v3
19.9.6 Settings
PID-6966-SETTINGS v3
Function Description IEC 61850 identification IEC 60617 identification ANSI/IEEE C37.2 device
number
Running hour-meter TEILGAPC - -
The Running hour-meter (TEILGAPC) function is a function that accumulates the elapsed time when a
given binary signal has been high, see also Figure 665.
BLOCK
RESET
IN Time Accumulation ACC_HOUR
ADDTIME with Retain
ACC_DAY
tAddToTime
q-1
OVERFLOW
a
&
a>b
99 999.9 h b
WARNING
a
&
a>b
b
tWarning
ALARM
a
&
a>b
b
tAlarm
TEILGAPC
BLOCK ALARM
IN WARNING
ADDTIME OVERFLOW
RESET ACC_HOUR
ACC_DAY
IEC15000323 V2 EN-US
19.10.4 Signals
PID-6998-INPUTSIGNALS v2
PID-6998-OUTPUTSIGNALS v2
19.10.5 Settings
PID-6998-SETTINGS v2
Loop Delay
tWarning
OVERFLOW
tAlarm
Transgression Supervision WARNING
Plus Retain
ALARM
BLOCK
RESET ACC_HOUR
Time Accumulation
IN
ADDTIME ACC_DAY
tAddToTime
Loop Delay
IEC15000322 V2 EN-US
• RESET: Reset of the accumulated value. Consequently all other outputs are also reset
• independent of the input IN value
• reset the value of the nonvolatile memory to zero.
Note that the nonvolatile memory will not reset to zero if the input IN is high during the reset.
• reset can be made by activation of input RESET or from WebUI or with IEC 61850 command
The ACC_HOURoutput represents the accumulated time in hours and the ACC_DAY output represents
the accumulated time in days.
tAlarm and tWarning are user settable time limit parameters in hours. They are also independent of each
other, that is, there is no check if tAlarm > tWarning.
tAlarm, tWarning and tAddToTime are possible to be defined with a resolution of 0.1 hours (6 minutes).
The limit for the overflow supervision is fixed at 99999.9 hours. The outputs will reset and the
accumulated time will reset and pickup from zero if an overflow occurs.
Consequently in case of a power failure, there is a risk of losing the difference in time between actual
time and last time stored in the non-volatile memory.
19.11.1 Identification
GUID-B62A30E5-C1F3-4E1F-B351-4F4CC60BA53F v1
The through fault monitoring function PTRSTHR(51TF) is used to monitor the mechanical stress on a
transformer and place it against its designed withstand capability. During through faults, the fault-current
magnitude is higher as the allowed overload current range. At low fault current magnitudes which
are below the overload capability of the transformer, mechanical effects are considered less important
unless the frequency of fault occurrence is high. Since through fault current magnitudes are typically
closer to the extreme design capabilities of the transformer, mechanical effects are more significant than
thermal effects.
For other power system objects, for example, an over-head line, this function can be used to make a log
of primary quantities of a protected line.
PTRSTHR (51TF)
I3PW1* ALARM
I3PW2* W1L1ALM
I3PW3* W1L2ALM
V3P* W1L3ALM
BLOCK W2L1ALM
ACCFREEZE W2L2ALM
EXTTRIG W2L3ALM
INHIBIT W3L1ALM
RSTTFCNT W3L2ALM
RSTCMLI2T W3L3ALM
TAPOLTC1 MTFWRN
TAPOLTC2 I2TALM
CMLI2TALM
REPMADE
ANSI18000072-1-en.vsdx
ANSI18000072 V1 EN-US
19.11.4 Signals
PID-7144-INPUTSIGNALS v1
19.11.5 Settings
PID-7144-SETTINGS v1
The PTRSTHR(51TF) function monitors the transformer during through fault and predicts the
degradation of its withstand capability. It detects the fault when the measured RMS current is above
the set threshold current limit. When the fault is detected, it calculates the I2t value for the through
fault duration with the calculated winding current. This calculation is triggered for all individual events
of through fault, winding-wise and in all phases. The function compares the calculated I2t for each fault
event with the set limit of I2t and an alarm is raised when the limit is exceeded.
Similarly, the cumulative effect of through faults with the accumulated I2t is calculated throughout the
transformer lifetime. This cumulative I2t is compared with the set limit of ΣI2t and an alarm is raised when
the limit is exceeded.
Additionally, the function monitors the time between subsequent through faults against the set time. If
this time is shorter than the set time, then the multi-through faults in short time detection warning is
raised.
The function also reports the below monitoring parameters of each winding and phases:
This function can be used for both 2-winding and 3-winding transformer configurations with maximum
two on-line load tap changers. It calculates all required parameters for each through faults and produces
an individual report per event.
Generally, line currents are measured by current transformers at the transformer terminals. However, the
winding current should be calculated and used to estimate the degradation of withstand capability due to
through faults. Winding currents calculation from line currents depend upon the transformer connection
type and the phase displacement between winding currents. Therefore, winding current calculation is
required to protect the transformer within its capacity. On the other hand, CT measurements done at the
windings do not require any further derivations of the winding current.
Consider the Dy11 transformer configuration shown in Figure 669, where ia, ib and ic are delta winding
side line currents and iA, iB and iC are wye winding side line currents.
ia iA
ic iB
ibc
ib iC
IEC18000073-1-en.vsdx
IEC18000073 V1 EN-US
In this example, both line currents and winding currents (phase) are equal in the wye winding side.
The delta winding currents iac, ibc and ica are derived from the line currents ia, ib and ic. Line currents
at the delta side do not have zero sequence currents, which are present at the wye winding side in
case of ground faults. In order to calculate the transformer through fault withstand capability, these
delta side winding currents are required to be calculated from the measured currents. To perform this
calculation, the number of windings is selected by the NoOfWindings setting and the transformer winding
configuration is selected by the ConnTypeWx (where, x = winding number 1, 2 or 3) setting.
The winding current calculation requires voltage ratio information, which is dynamically calculated from
the present OLTC tap position. The tap position inputs TAPOLTC1 and TAPOLTC2 can be driven from
the tap changer supervision function (YLTC). The RatedVoltageWx (where, x = winding number 1, 2 or
3) settings and settings corresponding to OLTC1 and OLTC2 are required to calculate the voltage ratio.
The placement of OLTC1 and OLTC2 are selected using the OLTCWinding setting.
Parameter Setting
Rated tap position RatedTapOLTC#1)
Minimum voltage tap position HighTapOLTC#
Maximum voltage tap position LowTapOLTC#
Step size StepSizeOLTC#
Table Note:
1) # = OLTC number 1 or 2
Phase displacement between the windings decides the direction of circulating zero sequence current.
The clock position of the phase displacement between winding 1 and winding 2 is set using the
ClockNumberW2 setting. Similarly, the clock position between winding 1 and winding 3 is set using
the ClockNumberW3 setting.
The zero sequence current correction can be enabled or disabled by selecting the ZSCurrCor setting. If
the ZSCurrCor setting is selected as Enabled, then the zero sequence current which circulates internally
in the delta winding is estimated from the available winding currents and used for further calculations.
If the ZSCurrCor setting is selected as Disabled, then the zero sequence current is considered as zero.
The utility can select the ZSCurrCor setting as Disabled when:
The function internally calculates the winding RMS current and peak current from the measured current
samples and used for further calculations.
Through faults are detected if the measured RMS current in any phase among all windings is above the
set limit. The user can set the limit with reference to the IEEE standard (3.5 times Irated) or according
to the transformer manufacturer specification. The settings for the through fault detection threshold (W1 I
pickup, W2 I pickup and W3 I pickup) are given winding-wise.
In addition to the limit check, through fault detection is verified against the INHIBIT binary input. The
INHIBIT input can be connected, for example, from the transformer differential protection TxWPDIF
(87T) function which blocks the through fault detection in case of an internal fault. Similarly, the function
can be blocked during transformer energization inrush by connecting the second harmonic blocking to
the INHIBIT input.
If both conditions are through, then the persistence of the signal is checked for set minimum time
t_MinTripDelay value. Through fault is declared only when the signal persists for the minimum duration
and BLOCK or INHIBIT input are not high. The function resets the through fault detection alarm output
when the measured current goes below the set limit including hysteresis limits.
The through fault detection alarm outputs, WxLyALM (x = winding number 1 to 3 and y = phase A, B
or C) are given for all windings phase-wise. Additionally, the function has a general alarm to indicate
through fault detection. Once the through fault detection alarm has raised, the function starts to calculate
the I2t.
Besides this, the binary input EXTTRIG is used to trigger the through fault withstand capability
calculations.
W1L1ALM
t_MinTripDelay
W1L1IRMS
OR t CalculationStart
OR
W1 I pickup
t_MinTripDelay
EXTTRIG
ANSI18000074-1-en.vsdx
ANSI18000074 V1 EN-US
In order to avoid the I2t calculation during any unwanted conditions, either the BLOCK or INHIBIT
inputs should be activated. Below cases describes the interoperability between BLOCK, INHIBIT and I2t
calculation:
• If BLOCK or INHIBIT input is activated first and a fault is detected, then that particular fault is
discarded.
• If BLOCK or INHIBIT input is activated first and deactivated before confirming the detected fault, then
that particular fault is considered.
• If BLOCK or INHIBIT input is activated after the fault confirmation, then that particular fault is not
discarded.
The through fault withstand capacity is decided based on the fault current magnitude and duration of
the fault. The fault duration is calculated from the instant the measured RMS current crosses the set
threshold current limit to the through fault detection reset. The TFDUR output gives the duration of
through fault in seconds. The through fault detection alarm is picked up after confirming the fault with a
time delay of t_MinTripDelay. If the fault is not confirmed, then the TFDUR output will not be updated.
Additionally, the function measures the time between transformers subsequent through fault events.
When this time difference is smaller than the tMultiThroFlt setting, then the function issues a warning
signal MTFWRN. The transformer manufacturer may indicate the maximum number of through fault per
time period in order to set the tMultiThroFlt setting.
The function counts the number of through faults for all windings and phases whenever a through fault
is detected. Also, the overall transformer through fault count is incremented by one if any winding phase
detects the fault. The fault count increment occurs after each fault has been cleared.
The through fault counts can be reset to the default value by activating either the RSTTFCNT binary
input or the command input. The default values for each individual winding phase and the overall
transformer is set through the InitCmlTFCnt and InitTFCntWxLy parameters respectively.
The binary input ACCFREEZE can be activated to stop incrementing through fault counters. In order
to control the function during the test mode, connect the PTRSTHR (51TF) function block with the
TESTMODE function block, as shown in Figure 671.
PTRSTHR (51TF)
I3PW1* ALARM
I3PW2* W1L1ALM
I3PW3* W1L2ALM
TESTMODE V3P* W1L3ALM
IED_TEST TEST BLOCK W2L1ALM
IED_TEST ACCFREEZE W2L2ALM
BLOCK EXTTRIG W2L3ALM
NOEVENT INHIBIT W3L1ALM
INPUT RSTTFCNT W3L2ALM
SETTING RSTCMLI2T W3L3ALM
IEC61850 TAPOLTC1 MTFWRN
TAPOLTC2 I2TALM
CMLI2TALM
REPMADE
ANSI18000075-1-en.vsdx
ANSI18000075 V1 EN-US
The transformer is subjected to electrical and mechanical stress when a fault current flows through it,
which is more than the transformer overload current. In general, stress reduces the transformer life
and it becomes even worse when stress occurs due to through faults. Stress can cause insulation
damages, conductor displacement and overall it weakens the windings and collapses their structure.
Therefore, stress reduces the transformer withstand capability throughout its lifetime. Degradation of the
transformer withstand capability can be predicted using the equation:
Where,
t = Duration of fault
k = Constant
Once the function detects a through fault based on the measured RMS current, it starts to calculate I2t.
The I2t calculation is based on the fault current instantaneous sample value and the duration of the fault.
If the fault is confirmed after the minimum time delay, then the I2t calculation will be carried-out until the
fault is cleared. If the fault is cleared before minimum time delay, then the calculated I2t is discarded.
This calculation is done for all windings and phases individually and repeats for all individual faults.
The calculated I2t value is used to check whether the transformer is within its withstand capability or
not. This is monitored with respect to the maximum withstand capability set limit. The I2t limits can be
set winding-wise using MaxI2tW1, MaxI2tW2 and MaxI2tW3 settings and this limit is applicable for all
phases of the respective winding. If the calculated I2t value of any winding crosses the corresponding
set limit, then a general alarm I2TALM is raised. Once the I2TALM alarm is raised, it resets after the set
time tPulse.
Transformer through faults produces physical forces that cause insulation compression, insulation
wear, and friction-induced displacement in the winding. These effects are cumulative and should be
considered throughout the transformer lifetime. The damage intensity from through faults depends on
the current magnitude, fault duration, and the total number of fault occurrences. Therefore, the function
accumulates the calculated I2t value over all through faults for winding and phase-wise.
The calculated cumulative ƩI2t values are used to check whether the transformer is within its withstand
capability or not. This is monitored with respect to the maximum cumulative withstand capability set
limit. The ƩI2t limits can be set winding-wise using MaxI2tCmlW1, MaxI2tCmlW2 and MaxI2tCmlW3
settings and this limit is applicable for all phases of the respective winding. If the calculated ƩI2t values
of any winding cross the corresponding set limit, then a general alarm CMLI2TALM is raised. Once
the CMLI2TALM alarm is raised, it resets only if the cumulative I2t values are reset to value below
the set limit. In order to reset the ƩI2t values to default, activate either the RSTCMLI2T binary input
or the command input. Default values for each individual winding phase is set using InitCmlI2tWxLy
parameters.
t_MinTripDelay
WxL1zRMS
a≥b t Time TFDUR
OR
Wx I pickup accumulation
1 T WxLzTFCNT
t_MinTripDelay Ʃ
0 F
EXTTRIG
RSTTFCNT
InitTFCntWxLz T
F
WxLzISAMPLES q‐1
a2
T WxLzI2T
Ʃ
SAMPLINGRATE F
0.0 T 0.0
F q‐1
I2TALM
a≥b
MaxI2tWx
÷ WxLzI2TP
100.0 WxLzCI2T
RSTTFCNT Ʃ
InitTFCntWxLz T
F
q‐1 CMLI2TALM
a≥b
MaxCmlI2tWx
÷ WxLzCI2TP
100.0
ANSI18000076-1-en.vsdx
x – winding 1, 2 and 3
z – Phase A, B and C
ANSI18000076 V1 EN-US
Both I2t and ƩI2t values are limited to 3.6 e12 and the maximum fault duration for I2t calculation is limited
to 1 min. Additionally, the function performs a plausibility check on the measured current samples prior
to the calculation, which limits the maximum sample value as ±1e6 A.
The function monitors the following parameters which are related to through fault for all windings and
phases:
The peak and RMS current are measured during the interval of through fault period.
Additionally, the function gives the percentage degradation of withstand capability for individual through
faults and all faults as a cumulative effect.
The percentage degradation of withstand capability for the individual through fault event is calculated as:
I 2 teventwise
Event-wise % degradation of withstand capability= 100
MaxI 2tWx
IECEQUATION18023 V1 EN-US (Equation 215)
Where,
MaxI2Wx = xth winding maximum allowable withstand capability degradation during through fault.
The total percentage degradation of withstand capability for the transformer is calculated as:
I 2t
Total % degradation of withstand capability 100
MaxI 2tCmlWx
IECEQUATION18024 V1 EN-US (Equation 216)
Where,
MaxI2tCmlWx = xth winding maximum allowable withstand capability degradation over all through faults.
The function provides general outputs from all windings and phases, which is displayed in the local HMI
and monitoring tool apart from the through fault monitoring report. The general data are calculated as
the maximum value out of all available data. The maximum fault peak current, maximum cumulative fault
peak current, and maximum fault RMS current outputs are derived for each winding as the maximum of
respective winding all phase values. The event wise % degradation and total % degradation of withstand
capability outputs are derived as the maximum value of all winding and phase values. In the through
fault monitoring report, the data is divided into two parts; general and winding wise for maximum 3
windings.
The function provides service values of measured current RMS values for each phase of all windings.
Also, it displays the measured RMS phase-to-ground voltage values for any one of the windings (which
is connected to the function block). The instantaneous RMS voltage values are captured at one and a
half power cycle delayed from the point of detected fault or the fault detection reset, whichever is earlier.
In order to indicate the report is ready for file transfer, the function provides a binary output REPMADE,
see Figure 673. The outputs given as ‘general data’ and ‘winding wise for all phases’ in the through fault
monitoring report are shown in Table 923.