Name: S.

Rahul
Roll No.: CH23B042
Mobile No.: 9353646500
Email ID: [email protected]
CGPA: 7.32
 GENERAL QUESTIONNAIRE
1. Why do you think developing a hyperloop is necessary in India,
and according to you, is the hyperloop concept feasible?
For a fast moving and developing nation like India, introduction of
hyperloop brings a revolutionary change in the society. It reduces the travel time
significantly, which in turn helps in movement of trade and goods at a much
faster rate, thereby increasing the economy of that place. Construction of
hyperloop helps in providing job opportunities to the skilled and unemployed
engineers. It becomes the stepping stone for the technical advancement of our
nation. It can also help in reducing traffic congestions in roads and railways.
There are many such advantages associated with development and construction
of the hyperloop.
Although hyperloop has many advantages, it has disadvantages as well.
For example, the cost of the travel would be high, maybe unaffordable by the
lower and middle-class societies, who make up about 75% of our society. With
the help of the government and society, I believe that hyperloop would be
feasible in India.

2. What motivates your interest in becoming a part of Avishkar

Hyperloop? How do you envision your potential contributions to
the team, and what do you hope to achieve in career development
through this association?
The mind-blowing concept itself makes me motivated to join the team
Avishkar Hyperloop. My strong passion for electrical systems combined with the
opportunity to work with the innovative students, drives my eagerness to
contribute. With my interest in electrical systems and in the team, I can give me
maximum contribution to the team. As a keen learner, I can guarantee you that I
will utilize the resource and try to keep myself updated and put my maximum
effort that can be helpful to the team. By joining the team, I am looking forward
for seeking more insight about the technical world and improve my thinking and
problem-solving abilities by working with the innovative team members.
3. What do you want to work on in the team once you join? Once you
go through the app, you’ll realize that the subsystem works on
various aspects. What interests you the most? Mention specific
details about what you would like to work on. Give some time for
this question and answer it seriously. It is important for both of us
to understand how you’ll fit into the team.
Questions 1 and 2 interested me a lot as they lie within my field of interest. I would like
to work in areas that involve more coding and software development, specifically focusing on
the following aspects:
 H-Bridge Control (Question 1): I am fascinated by the H-Bridge design. I would
love to work on developing the control algorithms that manage the H-Bridge
operation, ensuring efficient switching and optimal performance of the motor.
My interest in embedded systems and motor control would allow me to
contribute effectively to this subsystem, particularly in creating robust software
that can handle varying load conditions and improve overall system efficiency.
 Relay Management (Question 2) : The use of relays in the system for switching
and controlling various electrical components also fascinates me. I am interested
in working on the coding and logic that govern relay operations, ensuring
reliable and responsive switching under different scenarios. This would involve
developing algorithms that can monitor system states and control the relays
accordingly, enhancing the safety and functionality of the vehicle’s electrical
systems.

4. Avishkar is a competition team apart from an innovation team. To

compete, you should know about other players in the competition.
Search about similar teams like Avishkar and write two
innovations done by any team in Hyperloop and two specifically in
the subsystem part.
Some teams similar to Avishkar that is in the competition of developing a
hyperloop are: TUM hyperloop, UMD loop, UNSW Hyperloop, Swissloop,
EPFLoop and many more.
 TUM Hyperloop (Pod IV): New custom battery cells with impressive
power density, improved power electronics for even more power, a custom
braking system with higher pressures, an all-titanium design, and an even
lighter but stronger reinforced carbon fiber chassis all contributed to the
pod's performance reaching new heights.
 This led in a new race speed record: on the last run of the July 2019
competition, the pod reached an incredible peak speed of 482 kilometres
per hour.
It has created the demonstrator, a 24-meter long concrete vacuum
tube with a matching human sized capsule. Rigorous tests are carried out
on the demonstrator to identify the faults in the design of the pod at an
early stage.
 Swissloop (Bertrand Piccard): The linear switching reluctance motor
(LSRM) drives the vehicle by pulsing direct current via 24 coils,
maintaining constant forward propulsion.
The system consists of five high-voltage boxes, three propulsion
modules capable of controlling up to 150 A currents and 1.6g
accelerations, and four levitation and navigation modules.
The low-voltage box contains controllers and a battery management
system capable of supporting up to 24 lithium-polymer battery packs at
800 V.
The pod has a lightweight carbon fiber monocoque frame, improved
suspension for stability, and a pneumatic braking system capable of 2.1 g
deceleration.
Energy recovery is accomplished by regenerative braking and novel
cooling via a 3D-printed heat battery that stores thermal energy in paraffin,
hence improving performance and safety.
 EPFLoop: It has a test track of length 120m, 40m diameter and a min-
pressure of 10 milli-bars.
It has a real time simulator with 12 CPU cores and integration time
step of 10-50 micro-seconds. The RT simulation test bed aims to reproduce
the real-time behaviour of electrical power networks under the following
conditions: steady-state, electromechanical, and electromagnetic transients.
It has a Vacuum chamber with 250 litres of volume, pressure-level
of 0.05 milli-bars, and pumping speed of 33 m3/hr. The vacuum chamber is
made up of two curved half tubes that are fastened and sealed together. It is
constructed from a 6° piece of the infrastructure.
It has a Battery testing system which can provide a maximum power
supply of 3000W and 80V. The test bench is able to discharge and charge a
cell or module controlled through compactDaQs using Labview.

Resources:
  Hyperloop Prototypes | TUM Hyperloop
 Bertrand Piccard – Swissloop
 Experimental Facilities | EPFLoop
5. What are your other PORs/commitments this academic year? How
much time can you dedicate to the team every week?
I am presently a coordinator at GameDev in Envisage.
It requires maximum of 2-3 hours per week. Therefore, I can spend as much time
as required for the team.

6. Please list the software you are familiar with and your proficiency
level. Sharing project links related to these software skills would be
appreciated.
I am at an intermediate level in Python and JAVA. I have a very
basic knowledge of C++ which I acquired during the process of filling
the application. I am also doing a Data Science course and have a fairly
good knowledge of Data Structures and Algorithm. I also have a good
knowledge of Linux, Latex and some game developing languages like
Unity.

Some Projects that I have done are attached in this git:

Rahul-3-6-9 · GitHub
Question: 1
A. Understand how H-Bridge works in detail and explain it in your own
words. Give a circuit diagram for a H-bridge using the appropriate
switching devices available there. Choose components wisely and give a
feasible circuit. The Gate signals are the inputs for your circuits and H
bridge has a DC Motor load. Assume you have a DC power source of
sufficient voltage. (Include any protection circuitry if you feel like)
A H-Bridge is a circuit with a motor (Usually DC), 4 switching components and
voltage difference. It allows us to change the direction of rotation of the motor by
changing the trigger values, where triggers can be voltage in case of MOSFETs.

A basic H-Bridge looks as figure beside.

Here Q1, Q2, Q3 and Q4 represents the
MOSFETs (Switching Components). M
represents a motor.

The circuit for the same is

shown to the left. Here, PMOS and
NMOS are MOSFETs used as the
switching components representing
Q1, Q2, Q3 and Q4 respectively.

Here, the motor M can run forward or backward depending on the switch position.
 In case of the forward motion, the
components Q1 and Q4 are switched on while
the components Q2 and Q3 are switched off.
This makes the circuit appear as shown to the right.
The Orange line shows the flow of current.

The implementation of the same is shown below. Here switching on the right
switch while keeping the left switch in the off state makes the motor run in the forward
direction.
 In case of the forward motion, the
components Q2 and Q3 are switched on
while the components Q1 and Q4 are
switched off. This makes the circuit appear
as shown to the right. The Orange line shows
the flow of current.

The implementation of the same is shown below. Here switching on the left
switch while keeping the right switch in the off state makes the motor run in the
backward direction.
Note: If we try to switch on all the switching components on/off, then the motor does
not run, while switching the components in an order that is not intended reduces the
motor velocity to zero with rapid deceleration.

Tinkercad circuit: Circuit design H-Bridge circuit - Tinkercad

References:
 H-bridge: Working, Circuits and Applications - Utmel
 The Difference Between Slow Decay Mode and Fast Decay Mode in H-
Bridge DC Motor Applications - Technical Articles
(allaboutcircuits.com)

B. Why do we need a DC-link capacitor for H-bridge? What are all the
parameters that decide/influence the Capacitance value for the DC- link
Capacitor? State the dependence of the capacitance on these
parameters.
A DC-Link Capacitor is a capacitor that is
connected parallel to the load primarily for
voltage stabilization around the load and smooth
out the fluctuations caused due to rapid switching
of the flow of the current.
The implementation of the DC-Link
capacitor is ass shown in the figure. Here, the
Bus Link represents the DC-Link capacitor.

The purpose of using the DC-Link Capacitors are as follows:

 Voltage stabilization around the load.
 Smoothening of the fluctuations in current flow to the load caused by
the rapid switching.
 Storing energy and supplying it when there is a demand for the supply
of a high power by the load.
 Controls the ripple current flowing through the circuit.
 Some of the factors that affect the capacitor value are:
 Ripple Voltage:
Greater the maximum allowable ripple voltage in the
circuit, Lesser is the capacitor value because a higher ripple
voltage requirement means that the capacitor must be able to
store and release more charge to maintain the DC voltage.
 Current delivered to the load:
Greater the current delivered to the circuit, Greater is
the capacitor value because increasing the output current leads
to increase in the Ripple current and greater capacitance is
required to absorb it.
 Duty Cycle of the PWM used:
Duty Cycle of the PWM used directly affects the
capacitance value. A larger duty cycle indicates that the input
voltage is applied for a longer amount of time, which might
result in increased average current and, as a result, higher
ripple voltage. This requires a higher capacitance in order to
produce the required voltage stability.

 Switching frequency:
As switching frequency increases, the value of the
ripple current increases. As the switching frequency increases,
so does the ripple current. This can result in increased ripple
voltage if the capacitance is unable to manage the rapid
fluctuations in current. Higher switching
frequencies requires higher capacitance to ensure that the
capacitor responds properly to changing conditions.

References:
 Why dc link capacitor is required? | ResearchGate
 Lost Secrets of the H-Bridge, Part III: Practical Issues of Inductor
and Capacitor Ripple Current - Jason Sachs
(embeddedrelated.com)
 Lost Secrets of the H-Bridge, Part IV: DC Link Decoupling and
Why Electrolytic Capacitors Are Not Enough - Jason Sachs
(embeddedrelated.com)
C. What is a Dead-band in the gate signals in the MOSFETs, Explain
with Input waveform example with proper dead band. Assume we are
using this Gate Driving IC. Find how you can make a hardware
deadband using this gate-driver and also mention the type and
specification of the component you are using.
Dead-band in gate signals for MOSFETs is an intended delay or gap in switching
signals that prevents both the high-side and low-side MOSFETs in a H-bridge design
from being turned on at the same time. This is essential for avoiding short circuit
conditions, which can cause excessive current flow and device damage.

In the above figure, PWM refers to the input signal given from a PWM circuit. Q
represents the signal to the forward motion of the motor and Q’ is the complementary
signal for enabling the backward motion of the motor. The Dead Time makes sure that
the forward motion circuit and the backward motion circuit are not switched on
simultaneously. This way it prevents the complete circuit from being short circuited as
it provides a low resistance path when they are switched on simultaneously.
The hardware deadband can be made as follows:
Material requirements:
 PWM circuit
 Gate Driver IC:
Here, we are going to use UCC21520 gate driver IC with the
specifications:
 Dual-channel gate driver.
 Built-in dead time control.
 High speed operational ability.
 With the required voltage range functionality.

 Load Circuit with the switching components (H-Bridge with MOSFETs for
instance).
 Resistors for changing value of the dead time.
Circuit building:

The above shown component represents the UCC21520 gate driver IC.
Major connections include:
 Connection between PWM circuit output to the input pins (1 or/and 3).
 Connecting resistor between pin 6 and pin 4 to change the dead time value.
 Connecting pin 3 and 8 to the voltage supply and pin 4 to ground.
 Connecting pin 15 or/and 10 to the load circuit.
 Further connections can be referred from the below table.
References:
 H-bridge DC Motor Control Using Complementary PWM, Shoot-through,
and Dead-time - Technical Articles (allaboutcircuits.com)
 ucc21520.pdf (ti.com)
Question: 2
Given below is a circuit diagram of a battery supplying power to an
induction motor M. Notice the switch labeled as pre-charge. Read about
pre-charge and answer the following questions:

1) The battery can be connected to the inverter by closing the Main

relay (+) and main relay (-). If that’s the case, then why are the pre-
charge relay and the resistor connected? What purpose do they serve?
Initially the capacitor is uncharged and no electric current is flowing in the
circuit, in this case when the Main relays (+ and -) are closed there will be a sudden
surge of electricity in the circuit which can damage the circuit. To prevent this from
happening we use pre-charger relay with the resistor. This makes sure that voltage
across the circuit rises gradually until the capacitor is fully charged after which the pre-
charger relay is opened or disconnected to allow the motor to function at its maximum
efficiency thus protecting it from the surge.

2) Think of an approach to calculate the value of the resistor that should

be used. (Assume battery voltage V and capacitance value C. Make
other assumptions, if necessary, but clearly state them.)
Assumptions:
 Motor does not start or draw current until the potential difference across it
reaches the low voltage of the motor.
 Time elapsed before starting the motor = T.

Working:
3) Explain the purpose of the capacitor in this circuit. In continuation,
describe how you would calculate the value of this capacitor. Mention
all the parameters that you need and how you will work with them.
The capacitor has various purposes like:
 Voltage maintenance around the motor.
 Protect the motor from voltage fluctuations.
 Helping the pre-charge to prevent the sudden surge of current into the motor.

The value of this capacitor can be calculated using:

 Specifications of the motor (like Voltage and Current Rating).
 Time required to start the motor.
 Value of the resistance connected with the pre-charge.
Equations required to calculate the value of the capacitor are:
 Current through the capacitor = Current through resistor - Current through the
motor (found using the specifications).
 Voltage across capacitor = Voltage across the motor (as they are in parallel
connection).
 Charge flowing through the capacitor = Current through capacitor * Time
required to start the motor
 Capacitance = Charge flowing through the capacitor / Voltage across the
capacitor.

Combining these equations, we can find the value of the capacitor.

Question: 3
A. Designing a PCB involves a flow of action. Each step is ahead for a
reason. Arrange the blocks in the right way and justify your order
in detail.
1. Interacting with Other subsystem to jot down purpose and
requirements
2. Power Consumption calculations
3. Finalize Inputs & Outputs
4. Design Power circuit
5. Design Signal Processing circuit
6. Design processor schematic
7. Impedance matching & differential pair routing
8. Trace width calculations
9. Normal Routing
10. EMI/EMC optimization
11. Adding Polygon pours
12. Mounting Holes

Process of designing of the PCB should be as follows:

1. Interacting with Other Subsystems to Jot Down Purpose and
Requirements
 The first step in PCB design involves understanding the system's
requirements.
 This includes communication between subsystem teams to define the
purpose, constraints, and requirements of the PCB.
 This ensures that all design decisions are aligned with the overall system's
needs.
2. Power Consumption Calculations
 Understanding power consumption is crucial for developing power
circuits.
 This step involves calculating the power requirements for all
components on the PCB so that the power circuit can handle the load
without overheating or causing any instability.
3. Finalize Inputs & Outputs

 The next step is to finalize the inputs and outputs of the PCB.
 This includes determining all connections, components, and signal
types that the PCB will be handling.

4. Design Power Circuit

 After calculating the power consumption, the next step is to design the
power supply circuit.
 This involves selecting voltage regulators, capacitors, and other
components necessary to provide a stable output power to the PCB
components.
5. Design Signal Processing circuit
 Signal processing circuits handle the manipulation and transmission of
data signals within the PCB.
 This step comes after designing the processor schematic because the
signal circuits often interact closely with the processor.
6. Design Processor Schematic
 The processors play a significant role in functioning of the PCB. They
help in deciding whether the components should be activated and how
much power to be given to each component.
 Designing its schematic involves ensuring it is correctly powered and
connected to other components as per the requirements defined earlier.
7. Impedance Matching & Differential Pair Routing
 When a signal travels from one part of network to another, then due to
impedance mismatch, the signal gets partially deflected and raises
issues regarding signal integrity.
 So, differential Pair Routing is used to eliminate noises (where
complementary signals are sent) that has been caused by external
interference, this methodology is opted in CAN.
8. Trace Width Calculations
 With the circuits designed, the next step is to calculate the trace widths
required to handle the expected current levels and ensure the traces can
carry the necessary signals without excessive loss or overheating.
 This should work accordingly with impedance matching and the
amount of current passing through the traces.
 9. Normal Routing
 Once trace widths are calculated, we can proceed with the normal
routing of all the signal and power traces.
 This step involves laying out the PCB traces according to the schematic
and calculated requirements.
10. EMI/EMC Optimization
 After routing the traces, it is important to optimize the design for
electromagnetic interference (EMI) and electromagnetic compatibility
(EMC).
 This involves tweaking the routing, adding shielding, or using other
techniques like using decoupling capacitors to minimize noise and
ensure the PCB complies with regulatory standards.
11. Adding Polygon Pours
 With the main routing and EMI/EMC optimization complete, the next
step is to add polygon pours (often for ground planes or power planes).
 These pours help with heat dissipation, and providing a stable reference
voltage across the PCB.
12. Mounting Holes
 Finally, after all the circuits and routing are in place, you can add
mounting holes.
 These are mechanical features used to attach the PCB to a chassis or
enclosure and are added last to ensure they don’t interfere with any
circuitry.

B. In electronic systems, signals acquired from sensors are often

analog in nature. Why is it common practice to isolate analog
signal reference grounds from digital signal grounds? When
designing a PCB, both digital and analog signals often need to be
routed to a microprocessor. However, this presents a challenge, as
the microprocessor requires both analog and digital grounds to
reference the signals accurately. What are the techniques used to
effectively separate these grounds while maintaining proper signal
integrity?
In electronic systems, especially in mixed-signal environments
where both analog and digital signals are present, it is essential to
isolate analog signal reference grounds from digital signal grounds.
This practice helps in minimizing noise interference and
maintaining signal integrity.
Why Isolating Analog and Digital Grounds is Important?
Nature of Analog and Digital Signals:
Analog Signals: These are continuous signals that can have any value over a range
and are susceptible to noise and interference. Analog signals are typically used to
represent sensor outputs, audio signals, and other forms of real-world data.
Digital Signals: These are discrete signals with distinct high (1) and low (0) states,
often used in microprocessors, digital logic circuits, and communication systems.
Digital circuits can create significant noise due to fast switching transitions.
Ground Noise and Interference:
Digital circuits generate switching noise due to their high-speed transitions. This
noise can induce voltage spikes on the ground plane, referred to as ground bounce or
digital ground noise.
If analog and digital grounds are not properly isolated, this noise can couple into the
sensitive analog circuitry, degrading the analog signal integrity and causing
inaccuracies in analog-to-digital conversion (ADC) processes.
Signal Integrity:
As far as I know, Maintaining separate ground planes for analog and digital circuits
helps in minimizing the crosstalk and electromagnetic interference (EMI) that can
affect the accuracy of signal processing.
Techniques to Separate Analog and Digital Grounds on a PCB:
When designing a PCB that contains both analog and digital components, certain
techniques can be used to effectively separate these grounds while ensuring that both
analog and digital signals are correctly referenced to the microprocessor or
microcontroller:
1. Use of Split Ground Planes
Definition: A split ground plane involves creating separate ground planes for analog
(AGND) and digital (DGND) signals on the PCB layout.
Purpose: By separating the ground planes, the high-frequency noise generated by
digital circuits is confined to the digital ground plane, preventing it from coupling
into the analog ground plane where sensitive analog signals are referenced.
Star Ground Connection: The analog and digital grounds are connected at a single
point (often near the ADC or microcontroller) to ensure a common reference
potential. This connection point is chosen to minimize the current path overlap and
reduce noise coupling.
2. Use of Ground Plane Guarding (Moat or Guard Ring)
Definition: A guard ring or moat is a trace or narrow strip of grounded copper
placed around sensitive analog components to shield them from digital noise.
Purpose: It acts as a barrier that prevents digital ground noise from leaking into the
analog sections. The guard ring is connected to the analog ground plane and is
placed between the digital and analog circuitry to provide effective shielding.

3. Common Ground Reference with Strategic Ground Routing

Definition: This technique involves routing the ground traces in such a way that
high-current paths (usually from digital circuits) do not interfere with low-noise
analog signals.
Purpose: It ensures that the return current from digital circuits does not share the
same path as the analog signals, minimizing noise coupling through the ground
return paths.
4. Microprocessor Ground Pin Configuration
Definition: Many microcontrollers or ADCs have separate AGND and DGND pins.
These pins should be connected to their respective ground planes on the PCB,
converging at a single point (star connection).
Purpose: This helps the microprocessor or ADC differentiate between analog and
digital signals, allowing for proper sampling and conversion without introducing
digital noise into the analog circuitry.
C. The Arduino Uno R3 is a board that is frequently used for
hobbyist purposes*. Here is the official schematic of the board
assigned for reference. Use this schematic for this question.
Analyze the power circuitry on the Arduino, and explain how the
various sources of power (PWRIN, VIN, USBVCC) are used
together to give the +5V and 3V3 supply. Every Capacitor,
Resistor and Diode on the board serves a purpose; understand it.

This is a simple flow chart describing the voltage conversions and power supply
to all other components.
Role of FDN340P in Power Supply:
1. Automatic Power Source Selection:
 The FDN340P is used in the power supply section of the Arduino Uno to
automatically switch between USB power and an external power supply.
 When an external power supply (VIN) is connected and is above a certain
threshold (typically around 6.6V or higher), the comparator (U5A) detects
this higher voltage and turns off the FDN340P, disconnecting the USB
power from the board. I guess it is 6.6 V because I can notice the Linear
 Voltage Divider at the top left of the photo, and the Vin should be twice as
the 3.3 V.
 If the external power supply is not present or is below the threshold, the
comparator outputs a signal that turns the FDN340P on, allowing USB
power (USBVCC) to power the board.
 The gate of the FDN340P is controlled by the comparator (U5A). If the
comparator outputs a high signal, the gate is pulled high, turning off the
FDN340P (as it is a P-channel MOSFET). This isolates the USBVCC line,
preventing it from providing power.
 Conversely, if the comparator outputs a low signal, the gate is pulled low,
turning on the FDN340P and allowing USBVCC to provide power to the
board.
 The output of the MOSFET is connected to 5V rail , from where every
GPIO pins and components get powered .


 In this circuit the 5V produced is used to light the indicator LED
2. Protection and Efficiency:
 This arrangement protects the board from drawing power from both the
USB and external sources simultaneously, which could cause damage or
reduce efficiency.
 The MOSFET provides a low-resistance path when turned on, ensuring
minimal voltage drop and power loss and I guess this is a feature of
Arduino, such that if any user wants to use an external power supply, then
he can use it instead of the supply via the user.
 The diode in the Arduino Uno Rev3 circuit near the FDN340P MOSFET is
used for reverse voltage protection and to prevent back feeding between
the USB and the external power supply. The diode ensures that no current
flows back through the USB if Potential of the battery is higher (this could
cause potential damage for the USB port). And useful in the case if we
give the reverse polarity, as it would not allow the circuit to get
completed.
 Role of LP2985 in Power Supply
 The LP2985 is a low-dropout (LDO) linear voltage regulator designed to provide
a stable output voltage with minimal voltage drop from the input. It is capable of
regulating an input voltage down to a precise output of 3.3V, making it ideal for
powering low-voltage devices in mixed-voltage environments. This module
ensures that the output voltage is close to 3.3 even if the input voltage drops too
much (till 1 percent of the input voltage). The circuitry of that IC has PNP
transistor and error amplification logic and does have overcurrent and overheat
protection. And it also has custom on/off switch.
 The 3.3 V produced is stabilized by a capacitor which is grounded on another
side and to reduce the noise. This ensures a clean 3.3V supply, which is crucial
for sensitive analog and digital components. Then this voltage is provided 3.3V
pin and any other component powered at 3.3V. And I think TP is a test point
where the voltage can be verified.

Role of Circuit in the right top

In the above circuit we get input from the external DC voltage through a connector. The
positive terminal (pin 1) receives the input voltage, while pin 2 connects to ground
(GND).

As I said in the previous case the diode D1 (schotky) is used to provide reverse voltage
protection. It ensures that if the external power supply is connected with incorrect
polarity, the diode will block the current, protecting the circuit from damage. And the
capacitor is used to smoothen the voltage.
NCP1117ST50T3G

This is a linear voltage regulator that steps down the input voltage (VIN) to a stable
5V output. Even if we can adjust the output voltage in the IC, we need 5V. The input
(VIN) to the regulator is taken from the node after the diode (TP_VIN), and the
regulated 5V output is provided on the OUT pin. The voltage regulator is crucial for
ensuring that the Arduino Uno operates at a stable 5V regardless of variations in the
input voltage within the specified range.

And again the capacitors are there to stabilize the output voltage of Linear Voltage
Regulator and in the PCB’s generally those are used as decoupling capacitors which is
used to reduce the external noises.
Question: 4
A. The CAN protocol is a widely adopted and highly robust
communication standard in the industry, known for its efficiency
and reliability. To understand its operation, please provide a brief
overview of how a CAN message frame is structured, detailing the
purpose of each of its components. Additionally, explain the
process of bus arbitration in CAN communication and how the
protocol seamlessly ensures that messages are prioritized and
transmitted without conflicts.

A Standard CAN message format looks as follows:

The components of a CAN message are:

1. Bus Idle: This makes sure that the components of the CAN Bus can
send message only when the Bus is free from the recessive bits after the
End of Field (EOF) so that it does not clash with the new message that
is to be sent in the bus. It is of 1 bit length.
 2. Start of Field (SOF): This marks the start of the CAN Bus message. It
is of 1 bit length.
3. Identifier: This is used to establish a priority order of execution of the
messages by the components of the CAN Bus. It is of 11- or 29-bits
length based on the type of CAN message.
4. Remote Transmission Request (RTR): This is used to indicate
whether the message is sent in the data-frame (0) or in the remote-
frame (1). It is of 1 bit length.
5. Identifier Extension bit (IDE): This is used to indicate whether the
identifier is in standard (0) or extended (1) format. This is of 1 bit
length.
6. Reserved Bit (r): This is set for the future updates of the CAN Bus and
is not used in most cases. This is of 1 bit length.
7. Data Length Code (DLC): This is used to indicate the size of the data
field. This ifs of 4-bit length.
8. Data Field: This contains the actual message to be delivered to the
CAN Bus components. This can be of length up to 64-bits and its size is
determined by the value of the DLC component of the CAN Bus
message.
9. Cyclic Redundancy Check (CRC Field): This is used to detect the
errors that occur during the data transmission. CRC value is checked at
the time of transmission and receiving and checked for transmission
error. This is of 15-bit length. This is followed by a delimiter bit (del)
of 1-bit length to separate it from the other components of the message.
10.ACK Field: This is used to give acknowledgement to the CAN Bus
that the component has received (or not), the message. This is of 1-bit
length and is followed by a delimiter bit (del) of 1-bit length to separate
it from the other components of the message.
11.End of Field (EOF): This is used to mark the end of the CAN Bus
message. It is of 1-bit length.

When multiple components of the CAN Bus try to transmit data on the bus, a
process called Bus Arbitration to determine which message will be transmitted
first. The process is as follows:
1. The Bus Idle field is checked to see if the bus is free for transmission.
 2. If the Bus is not free, all the other components are put on hold until the
high priority component has finished the transmission and the Bus is set
to Idle state.
3. Higher priority is given to the component with the lower Identifier field
value or in other words, the component with the dominant bit (0) has
higher priority over the component with the recessive bit (1) while
checking the identifiers in binary numbers. For example, let Component
A have an identifier value of 0x010 (decimal value of 16) and
Component B have an identifier value of 0x020 (decimal value of 32),
then Component A has higher priority over Component B.
4. When Bus is free, the higher priority component is allowed to transmit
and the lower priority components are set to receiving state until the
higher priority component finishes its transmission.
This process of prioritization of the components makes sure that the collision of
the messages between two or more components of the CAN Bus does not happen.
Resources:
 CAN Protocol: Architecture, Working, Types & Its Applications
(watelectronics.com)
 A CAN Protocol Overview: Basics And Benefits - NetBurner
 101: Controller Area Network (CAN) standard - NXP Community

B. Why is message filtering essential in an Hyperloop pod? Is filtering

managed at the protocol level or hardware level? What potential
issues could arise if messages are not filtered? Explain the message
filtering process in CAN communication.

Message filtering plays a very crucial in Hyperloop pod where time and space
required for execution of the process matters. Message filtering filters out the
non-essential and unwanted messages from saving into the log and allowing only
required messages like speed, location, and system diagnostics to be stored into
the log. Message filtering enables a smoother communication between the
components with the crucial messages.
Not using message filtering can lead to information overload on the log, reduced
communication between the components with the crucial messages because of
 processing of unwanted messages, processing of lots of data can lead to the
increased power consumption and reduced overall efficiency of the CAN Bus.
The filtering process can be thought of a two-step process. Firstly, the priority of
the messages is checked based on the identifier value and secondly, the CAN Bus
contains an acceptance filter which is configured such that if a component
requires a message with a specific CAN ID, then the configuration is done so that
the message with that CAN ID is accepted and the remaining are ignored.
Resources:
 Understanding Message filter in CAN (influxtechnology.com)
 38.7.2.3 Filtering on Data Bytes (microchip.com)

C. Now that you have learned about how Filtering works in CAN.
Here is a Node A and its corresponding Filter and Mask:
Filter ID: 0x15608423
Mask ID: 0x1FBB777F
How many and what are the message IDs that Node A can read?
Also, how to make Node A:
i) read all message IDs
ii)read no message IDs

Filter Id is the specific CAN Id that the Node A is interested in and Mask Id
refers to bits of the Filter ID that should be considered for matching against the
incoming message IDs. A bit set to '1' in the Mask ID means that the
corresponding bit in the message ID will be compared with the Filter ID. A bit set
to '0' means that the corresponding bit can be any value.

Here, Filter ID = 0x15608423 = 00010101011000001000010000100011 and

Mask ID = 0x1FBB777F = 00011111101110111101111101111111

On applying AND operation on both IDs, we get

00010101001000001000010000100011.
And the IDs that Node A can read are 00010101001000001000010000100011
with 0 being either 0 or 1, and 1 being fixed.
 So, the number of messages which the Node A can read are 223 combinations of
the CAN ID.

To make the Node A read:

1. All the messages: Set the Filter ID = 0x00000000 and the Mask ID =
0x00000000.
2. No messages: Set the Filter ID = 0x00000000 and the Mask ID =
0xFFFFFFFF.

D. The CAN frame and protocol has been intelligently designed to act
as a key to ensuring that the CAN message integrity is not
compromised. Explain briefly how this has been implemented in
CAN.
One of the key features and advantages of using the CAN Bus is the
message integrity and error handling mechanism. The CAN Bus message consists
of the CRC Field to check the error in message that can occur during the
transmission of data. The CAN Bus message consists of the ACK Field to make
sure that the correct node reads the correct message. Bus Arbitration makes sure
no error occurs due to clash of messages transmitted by various nodes at the same
time. Each node consists of an error counter to check the number of errors
occurred, if the count exceeds a threshold the node has the option to change its
state between active, passive and off state.
Resources:
 CAN Bus Explained - A Simple Intro [2024] – CSS Electronics
 101: Controller Area Network (CAN) standard - NXP Community
 E. Here you have the series of bits that is sent and the corresponding
CANH and CANL voltages that is sensed by the transceiver. How
does the CAN transceiver interpret these bits separately?

The CAN transceiver receives the message as the CANH and CANL graph as
shown in the figure. For each time frame it calculates the difference between the
CANH and CANL values. If the difference is significant and positive, it
corresponds to the dominant bit (0) and if the difference is negligible, it
corresponds to the recessive bit (1).

Question 5:
A. Moving to the software stack, we code out microcontrollers using
concepts of multi-threading and RTOS. Learn a bit about them
and explain:
1. Thread and Processes:
A task or program is also known as a process. Each process can be
sub-divided into smaller programs known as threads. These threads
represent a single flow of execution within a larger program. They can be
scheduled and executed individually and concurrently with other threads.
Threads of the same program share a common memory space (memory
space of the parent program) but have its own call stacks and registers. By
splitting the process into different threads, it can be processed faster and
the processor can be utilized efficiently. For example, playing a movie is a
process and audio and video are controlled by different threads.
Source: Thread in Operating System - GeeksforGeeks
 2. MUTEX and Semaphores:
MUTEX is a program object that prevents multiple threads from
accessing the same resource simultaneously. The resource refers to a
component of the parent program that only one thread can access at a time.
The priority inheritance process ensures that the thread with the highest
priority waits the least amount of time to access the program. A
disadvantage of MUTEX is that new threads are only processed after the
previous ones have finished the program.

Semaphores deal with synchronization of objects in RTOS

environment. They allow multiple threads to access the program
simultaneously. They are of two types:
i. Binary semaphores: They assign binary values 0 and 1. A
thread can take it only if it has value 1. The value changes to
0 when the threads take it and changed back to 1 when it
returns the program after accessing it. MUTEX is a special
kind of binary semaphores with additional features
ii. Counting semaphores: They maintain a non-negative integer
representing the number of available resources for threads. A
thread takes it if the number is greater than 0. Once the thread
takes it the value is decremented by 1 and is incremented
once the thread returns it. It does not implement mutual exclusion

Source: RTOS: Mutex and Semaphore Basics - Open4Tech

B. Having learnt about threads, design the code structure for the
following problem statement.
An FSM system has three states: initialization, operation, and
teardown. The system is in contact with the user interface and
sensors and continuously collects data from them.
The FSM is initially configured in manual mode, which means that
you only switch between states when the user interface prompts me
to do so. However, the user has the option to go back to automated
mode, in which case everything is done automatically.
Please be aware that you are just needed to provide a very high-
level overview of the code; in other words, you can describe your
code in detail without having to make any syntactical expressions.
 An FSM (Finite State Machine) manages various states and gives them access
only when their respective triggers are activated or deactivated.
A basic code overview may look as follows:
1. Classes to be defined:
 FSM class: to manage the states and to check the respective
triggers.
 User_Interface class: to manage the inputs received from and
outputs shown to the user.
 Sensor_Interface class: to manage the sensor inputs and
commands to be given to them (if any).
 Manual_Mode class: to give control over changing the states to
the user.
 Automatic_Mode class: to change the states automatically
without involvement of the user in changing the states.
2. States involved:
 Initialization state
 Operation state
 Teardown state
3. Flow of the code:
 The FSM is set to the Initialization state and manual mode
initially.
 Initialization state is used to initialize all the sensors, input and
output devices involved in the FSM, later the trigger for the
Operation state is activated.
 Operation state uses User_Interface and Sensor_Interface classes
to receive the required inputs continuously. The inputs are
checked and in case of errors, the trigger for the Teardown state
is activated.
 Teardown State makes sure that the sensors and all processes are
shut down temporarily and the control is transferred to the
Initialization state or terminate the process (if required).
 The user is also given the option to activate the Automatic_Mode
class to change between the state when indicated.

C. If we select the optimal approach to handle the way the code is

really executed by the processor, we can take advantage of a
 number of opportunities. Embedded Linux, bare metal, and basic
RTOS are popular choices.

1. What is an Operating System (OS)?

An Operating System is a system software which serves as a medium of
communication between the user and the various components of the system. It
has various other uses like managing the resource usage by the programs,
memory allocation and de-allocation to the programs, making the applications
attractive and user friendly, acting as a communication channel between the
system software and system hardware, and many more. These are the very
first set of codes that are run when a computer is switched on. Some examples
of the Operating System are Windows and MAC OS.
Source: Difference between Operating System and Kernel - GeeksforGeeks

2. What role does the OS Kernel play within an operating system?

A kernel is the core component of an operating system that controls
computer and hardware functions. It basically handles memory and CPU
activities. The kernel serves as a link between programs and data processing at
the hardware level, enabling inter-process communication and system calls. It
also serves as an interface between software applications and computer
hardware. The kernel also oversees system resources like as the CPU usage,
memory, and devices, ensuring that everything functions properly and
effectively.

3. What does "Bare Metal" mean in the context of computing?

BareMetal is an exokernel based single address space operating system
implying that it is like a server that is solely dedicated to single request/client.
It consists of base level programs that interacts directly with the hardware
processes. It has various features like attaining higher control on the hardware
processes, faster processing of the commands, and many more.
Source:
a. BareMetal - Wikipedia
 b. Understanding Bare Metal: Exploring the Meaning and Benefits |
Databank
c. Bare Metal vs. RTOS vs. OS: What’s the Best for Your IoT
Solution? (nabto.com)

4. What are the potential benefits of utilizing an operating system

for the central control unit of an Hyperloop system?
Advantages of using an Operating System for the central control unit of an
Hyperloop system are:
 Better task and resource management.
 Better error handling mechanism.
 User friendly control.
 Easier maintenance.

5. What are the possible drawbacks of using an operating system

for the central control unit of an Hyperloop system?
Advantages of using an Operating System for the central control unit of
an Hyperloop system are:
 Lacks real time performance required for the precise control and
quick responses.
 Lacks in efficient memory management.
 OS provides with variety of features which is good and bad in
their own ways, like too many cooks spoils the broth, too many
features lead to unnecessary complexity in handling them.